JPH1130646A - Semiconductor integrated circuit and test circuit to be comprised therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure a semiconductor integrated circuit and a test circuit to be comprised therein, capable of testing a wide range of subject circuits. SOLUTION: A semiconductor integrated circuit is used after converting it into a test mode through power input from a test terminal. When it is turned to the test mode, a clock highly speeded up at nth-fold by a clock multiplicational circuit 2 is inputted into a subject circuit 1, and further, data are inputted through a signal multiplied as far as nth-fold by a data compression circuit 3. Since the subject circuit 1 is inputted with the clock and the data multiplied as far as nth-fold, in the case where the subject circuit 1 is operable at the clock at more nth-fold than a test circuit input clock, it is normally operated, and thereby normal compression data are outputted. The compression data outputted after being compressed at more nth-fold than the subject circuit 1 is converted into 1/n by a compression data depression circuit 4, and thus observation at a large scale integrated circuit tester is made possible to be done.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and a test circuit included therein, and more particularly to a semiconductor integrated circuit capable of performing a high-speed test and a test circuit included therein.

[0002]

2. Description of the Related Art Digital electronic circuits for business use have been formed by semiconductor integrated circuits (LSI) such as gate arrays for a long time. The gate arrays are becoming larger and larger, and the need to reduce test time is increasing. One method of reducing the test time is to increase the clock frequency, and the present invention relates to this method.

Japanese Patent Application Laid-Open No. 63-91578 or Japanese Patent Application Laid-Open No. 4-328476 proposes a method for speeding up a test of a semiconductor integrated circuit using a high-speed clock. Japanese Patent Application Laid-Open No. 4-328476 discloses a method of operating an LSI using a high-speed clock during a test by providing a clock generation circuit for generating a high-speed clock inside the LSI as shown in FIG. Has been proposed.

That is, in a high-speed, high-performance LSI,
A high-speed clock generation circuit 2 'for generating a high-speed clock necessary for testing the LSI is provided, and the LSI test-time selecting circuit 6 uses the high-speed clock generated from the high-speed clock generation circuit 2' to generate the high-speed clock. Since the test (internal) circuit 1 to be tested and evaluated are performed, a clock generation command or a relatively low-frequency clock for high-speed clock generation may be given to the LSI with respect to high-speed clock generation.
It is said that ordinary LSI testers or evaluation devices can sufficiently cope with high-speed, high-performance LSIs.

[0005]

SUMMARY OF THE INVENTION FIG.
In the case of the proposal described in Japanese Patent No. 328476, the clock generated from the high-speed clock generation circuit 2 'is input to the circuit under test 1, and the circuit under test 1 can be tested at high speed. However, in general, LSIs that can observe all operations only by increasing the speed of the clock alone are rare, and it is necessary to input data at the same time at a high speed.
Further, a normal LSI tester is not good at observing the operating state of an LSI operating at a high speed, so that even when the circuit under test 1 is operated at a high speed, it is often difficult to observe the operating state. Although a high-speed clock may be inserted in the circuit under test 1 to partially advance (high-speed operation), it is difficult to create a test pattern. There is no.

An object of the present invention is to provide a semiconductor integrated circuit capable of testing a wide range of circuits under test at high speed and a test circuit included therein.

[0007]

A test circuit according to the present invention comprises a clock multiplying means for multiplying a clock to generate a multiplied clock, and converting a plurality of phases of parallel test data into serial test data synchronized with the multiplied clock. A data compression means for inputting the input data and the serial test data, a data selection means for selecting the serial test data during the test and inputting the data to the circuit under test, and an input clock and the multiplied clock. A clock selecting means for selecting the multiplied clock and inputting the same to the circuit under test during a test, and a compressed data decompressing means for restoring the serial test data output from the circuit under test to the original parallel test data of the plurality of phases. It is characterized by:

The operation of the present invention is as follows. In order to synchronize a high-speed clock generation circuit (clock multiplication circuit) and a high-speed clock with data, a data compression circuit for increasing data speed and an operation result of an LSI can be easily observed outside. , A compressed data decompression (decompression) circuit. As an example of a data compression circuit, a parallel / serial conversion circuit of, for example, n → 1 is used to compress data synchronized with a clock multiplied by n times. Further, as a compressed data decompression (decompression) circuit, for example, a serial / parallel conversion circuit for converting 1 → n is used. The data compression circuit and the compressed data decompression circuit can be used for testing most LSIs to which conventional test circuits cannot be applied.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a semiconductor integrated circuit according to the present invention and a test circuit included therein, and the same parts as those in FIG. 7 are denoted by the same reference numerals.

In FIG. 1, a semiconductor integrated circuit according to the present invention includes a circuit under test 1 and a clock multiplying circuit 2 for multiplying an input clock by, for example, n, for example, data for converting test data of n channels into one serial data. A compression circuit 3, a selection circuit 5 for selecting data during a test, a selection circuit 6 for selecting a clock during a test, and a test circuit including a compressed data decompression circuit 4 for restoring compressed data to, for example, n-channel output monitor data. Is done.

In the operation of the embodiment of the present invention, conventionally, when testing an LSI with an LSI tester, even if the circuit under test 1 can operate at high speed, it is limited to the clock speed of the LSI tester, and the circuit under test 1 can operate at high speed. Even if the test cannot be performed, the semiconductor integrated circuit according to the present invention can be used in a test mode by an input from a test terminal. In the test mode, the circuit under test 1 receives a clock multiplied (multiplied) by n times by the clock multiplication circuit 2, and parallel test data as data and n in the data compression circuit 3. A serial test data signal (compressed data) multiplexed twice is input.

The circuit under test 1 receives the (multiplied) clock and the (compressed) data multiplied by n times, so that the circuit under test 1 operates with a clock that is n times the clock input to the test circuit. If possible, it operates normally and outputs normal compressed data. The compressed data output from the circuit under test 1 after being compressed n times is compressed data decompression circuit 4
As a result, the data is converted (restored) into 1 / n parallel output monitor data, and observation by an LSI tester becomes possible.

FIGS. 3 and 5 are actual circuit examples of the clock multiplication circuit 2. FIG. FIG. 4 is a timing chart of FIG. 3. One of the input clocks is input to the NAND 12, the other is inverted in phase by the gate 11, and then input to the NAND 13. NA
The output signals a and b of the NDs 12 and 13 are passed through delay circuits (delay time: τ) 14 and 15 to output NAN signals c and d.
Return to D13 and D12.

Therefore, when the signals a and b are input to the NAND 16, a double clock having a half clock cycle is obtained as the output of the NAND 16. At this time, the delay time τ of the delay circuits 14 and 15 is set to 1 / the input clock cycle.
If it is set to 4, the duty ratio of the double clock can be made close to 50%. As a result, the input clock can be multiplied to a double speed, so that it is possible to multiply the input clock to 2 ⁿ (power of 2) times by connecting n clocks in tandem.

FIG. 6 is a timing chart of FIG.
In FIG. 5, it is possible to multiply the clock by n times by inputting n phases (# 1 to #n) of different waveforms (clocks) having a duty ratio of 50% and forming a logical sum. Become.

FIG. 2 is a timing chart when, for example, the circuit under test 1 is a 4-bit shift register circuit, and the test circuit according to the present invention multiplies the clock signal four times to operate. In the actual operation of this 4-bit shift register circuit, as shown in FIG. 2A, input data abcd is sequentially shifted by a clock and output as output data abcd.

To test this 4-bit shift register circuit at four times the speed, as shown in FIG. 2B, four-phase test data # 1a to # 4d are input in parallel. When the data is converted into serial (compressed) data abcd by the quadrupled clock multiplied by four and input to the shift register circuit, output (compressed) data abcd is obtained as test data. When this compressed data is converted by the compressed data decompression circuit 4, the output monitor data # 1a to # 4d
Is obtained.

As shown in FIG. 6, when the test circuit of the present invention is used, even if an LST tester that can normally perform only a low-speed test can be used, verification close to actual operation can be performed with a small number of test patterns.

[0020]

As described above, according to the present invention, n data are converted to 1 by using a clock multiplied by n by the multiplication circuit.
/ N, and the circuit under test is operated at high speed with n times the clock and the compressed data, and the data compressed by the compressed data decompression circuit is decompressed n times and observed, so that the LSI test can be performed at high speed. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment of the present invention.

FIG. 3 is a circuit diagram of an example of a clock multiplication circuit.

FIG. 4 is a timing chart of an example of a clock multiplication circuit.

FIG. 5 is a circuit diagram of another example of the clock multiplication circuit.

FIG. 6 is a timing chart of another example of the clock multiplication circuit.

FIG. 7 is a block diagram of an example of a conventional test circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 circuit under test 2 clock multiplying circuit 3 data compression circuit 4 compressed data decompression circuit 5, 6 selection circuit

Claims (4)

[Claims] A clock multiplication means for multiplying a clock to generate a multiplied clock; a data compression means for converting a plurality of phases of parallel test data into serial test data synchronized with the multiplied clock; Data selecting means for inputting test data and selecting the serial test data at the time of testing and inputting the serial test data to the circuit under test; and inputting the input clock and the multiplied clock to select the multiplied clock at the time of testing and performing the test. A test circuit, comprising: a clock selection unit input to a circuit; and a compressed data decompression unit for restoring the serial test data output from the circuit under test to the original parallel test data of the plurality of phases. 2. The method according to claim 1, wherein the clock multiplying means includes a doubling means for multiplying the input clock by a factor of two, and a means for multiplying the input clock by a power of two by connecting the doubling means in tandem. The test circuit according to claim 1. 3. The test circuit according to claim 1, wherein said clock multiplying means is means for generating the multiplied clock by taking a logical sum of test clocks of a plurality of phases. 4. A semiconductor integrated circuit comprising the test circuit according to claim 1, 2 or 3, and the circuit under test.