JPH11306072A - Single chip microcontroller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a single chip microcontroller which can be used for a telephone or facsimile equipment for storing a telephone number and a fax number. SOLUTION: A memory unit 10 has both a static random access memory 1 and a flash EPROM 2 incorporated, and an internal flash EPROM 2 can be directly read in the same way as the static random access memory 1 is. Thus, an external EPROM and its related program for changing data stored there become unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a microcontroller. More specifically, a flash erasable programmable read only memory (flash EPROM) and a static random
The same method of reading data stored in flash erasable programmable read-only memory, incorporating both access memory (SRAM), in a single step, ie, static random access memory A single-chip microcontroller that reads in

[0002]

2. Description of the Related Art In various computers and systems, microcontrollers are often classified into 4-bit microcontrollers, 8-bit microcontrollers, 16-bit microcontrollers, and the like. All microcontrollers have input / output ports, a central processing unit (CPU) and a memory unit, and the input / output ports are provided for receiving, outputting, and sending data in the microcontroller, and the central processing unit has A memory unit is provided for processing data or acquired data, and a memory unit is provided for storing data executed by the central processing unit and related programs, and is usually provided with a ROM (read only memory) and a RAM (random memory). Access memory).

A ROM can retain data even after power is turned off, and is therefore suitable for storing unchangeable data and program applications. ROM
Are usually divided into a mask ROM, an EPROM (erasable programmable ROM) and an EEPROM (electrically erasable programmable ROM). Mask RO
The data of M is pre-written during manufacturing and cannot be changed later. On the other hand, EPROM data
By irradiating the transparent window of the EPROM with ultraviolet light for about 30 minutes, it is written by an EPROM recorder (programmer) and can be reprogrammed repeatedly. Similarly, the data in the EEPROM is written by an EEPROM recorder (programmer). However, since the EEPROM data is replaced and changed by an electronic signal, it is more convenient than the case where ultraviolet light is used for the EPROM.

[0004] Unlike a ROM, a RAM loses data when power is cut off, and is therefore suitable for storing temporarily changing data.

In some applications, such as telephones, faxes, etc., the memory unit must store certain data (such as telephone and fax numbers) for long periods of time and must be able to change the data at certain intervals. . In applications where temporary data must be stored for long periods of time, conventional single-chip microcontroller memory units are not available. Alternatively, the microcontroller may be provided with an external EEPROM (Electrically Erasable Programmable ROM) to store such types of data.

[0006]

However, the use of an external EEPROM requires additional interfaces, associated program control circuitry, and high voltages for recording (programming), and therefore, the cost of a single chip microcontroller. The problem is that the complexity increases substantially. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and to provide a low-cost single-chip microcontroller that can be used for telephone, fax, and the like.

[0007]

SUMMARY OF THE INVENTION In order to achieve the foregoing objects, the present invention provides an internal flash memory that does not require an external EEPROM or an associated device containing a complex program.
Provide a single chip microcontroller with memory. Thus, costs can be reduced, data can be maintained in flash memory (such as telephone and fax numbers) after a power loss, and data can be stored in a single step, similar to random access memory. Can be read.

[0008] The single chip microcontroller of the present invention comprises a memory unit and a central processing unit. The memory unit has a built-in flash memory and random access memory. flash·
When reading memory for a read address, the central processing unit transfers the read data directly to the destination register via the data bus. Further, when writing / erasing the flash memory with respect to the write / erase address and the write / erase data, the central processing unit firstly writes the write / erase address and the write / erase data.
Transfer the erase data to the data / address register, then write / erase the write / erase data to / from the flash memory write / erase address, and then write / erase the data / address register. , Assures completion of writing / erasing as compared with data in the flash memory.

In this single chip microcontroller, the flash memory is divided into several memory blocks sharing the same memory address and enabled by a block select signal stored in another register. There is.

The following detailed description is given by way of example and is not intended to limit the invention to only its embodiments but to be best understood in connection with the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION Conventional memory units for single chip microcontrollers often consist of read only memory (ROM) and random access memory (RAM). However, ROM can only store immutable programs and data, while RAM can only store changing temporary data. Therefore, this memory unit cannot be used to store temporary data such as telephone numbers and fax numbers for long periods of time.

FIG. 1 is a diagram showing the allocation of a memory unit of a single-chip microcontroller according to the present invention. In this embodiment, for simplicity,
Consider a 4-bit single-chip microcontroller as an example. The 4-bit single-chip microcontroller consists of a central processing unit (not shown) and a memory unit, in which both random access memory 1 and flash memory 2 are incorporated. I have.

In FIG. 1, a random access memory 1 (for example, an SRAM) stores a memory address 00
It is positioned at 0H to 1FFH. In addition, flash
Memory 2 (eg, flash EPROM) is located at memory addresses 200H-3FFH. Flash memory 2 shares the same memory address and is divided into four memory blocks, banks 0-3, which are enabled and selected by block select signal BK (not shown). The block selection signal BK is
Table 1 shows the relationship between the block selection signal BK stored in the register and the enabled memory block.

[0014]

[Table 1]

As can be seen from this table, in memory block bank 0, the block selection signal BK is [** 00]
, And memory block bank 1
Is enabled when the block select signal BK is [** 01], the memory block bank 2 is enabled when the block select signal BK is [** 10],
The memory block bank 3 receives the block selection signal BK
Is enabled when [** 11].

The read operation of the flash memory 2 is as follows.
This is the same as the reading operation of the random access memory 1. Single-chip microcontroller
When receiving a "read" instruction and causing the central processing unit to read the flash memory 2 for the read address Mx, the central processing unit transfers the data at the memory address Mx directly to the destination register via the data bus. I do. Next, the reading step will be described as an example.

MOV BK, # 02H; memory block bank 2
MOV A, Mx; Move register Mx value to destination register A

In this example, first, the block selection signal BK
Is set to 2, and memory block bank 2 is selected and enabled. Next, the data stored at the memory address Mx is directly transferred to the destination register A for output.

In contrast to a read operation, in a write / erase operation of the flash memory 2, the data / address register B must store an associated write / erase address My and write / erase data Dy.

FIG. 2 shows a timing sequence of the single-chip microcontroller of the present invention when writing data to the flash memory 2. next,
The writing step is shown as an example.

MOV BK, # 02H; enable memory block bank 2 MOV My, B; move write data Dy of data / address register B to write address My delay1 CLR PROG; set PROG signal to low level Set delay2 set PROG; set PROG signal to high level

In this example, first, the block selection signal B
K is set to 2 and memory block bank 2 is selected and enabled. Next, the write data Dy stored in the data / address register B (which stores the write address and the write data and indicates the write position in the memory block bank 2) is transferred to the memory address My
Pass to. Thereafter, the write data is recorded (programmed) at the memory address My of the memory block bank 2 of the flash memory 2 ("set the PROG signal to low level" as shown in FIG. 2). After recording (programming) for a predetermined period, the write data of the memory address My of the memory block bank 2 is
The data is compared with the data stored in the data / address register B using the comparator, and a write / erase signal EP indicating completion of the write operation is obtained. When the write operation is completed (memory address Mx of memory block bank 2)
Is equal to the data stored in the data / address register A).
Writing (programming) data to the memory is halted ("set PROG signal high" as shown in FIG. 2); otherwise, recording (programming) is performed only for a period sufficient to complete the transfer. ) Is continued.

FIG. 3 is a timing sequence of the single chip microcontroller of the present invention when erasing data from the flash memory 2. The corresponding erasing step is shown as an example.

MOV BK, # 03H; memory block bank 3
MOV Mx, # 300H; Determine erase address 300H delay1 CLR ERASE; Set ERASE signal to low level set ERASE; Set ERASE signal to high level

In this example, first, the block selection signal B
K is set to 3 and memory block bank 3 is enabled. Next, the erase address stored in the data / address register (300H in this example) is
It is passed to the memory address Mx, which indicates the position at which the data at the memory address Mx of the memory block bank 3 is to be erased. Next, data is erased from the memory address Mx of the memory block bank 3 ("set the ERASE signal to low level" as shown in FIG. 3). After erasing for a predetermined period, the data at the memory address Mx of the memory block bank 3 is compared with a default value, and a write / erase signal EP indicating completion of the erasing operation is obtained. If the erase operation is completed, the erase is stopped ("erase signal is set to a high level" as shown in FIG. 3). Otherwise, the erase is continued for a time period during which the transfer is completed. .

As described above, the write / erase signal EP generated in the write operation and the erase operation can be stored in the 4-bit register. Table II shows the relationship between the write / erase signal EP and the completion of the write / erase operation.

[0027]

[Table 2]

When the write operation of the erase operation is completed, the least significant bit of the write / erase signal is set to zero (E
(P0 = 0), otherwise, the least significant bit of the write / erase signal is set to 1 (EP0 = 1).

FIG. 4 is an internal block diagram of the single chip microcontroller of the present invention. single·
The chip microcontroller is the memory unit 1
0, data / address register 20, block select register 30, write / erase register 40, and comparator 5
Consists of zero. The memory unit 10 includes two random access memories MEM0 to MEM1 and two flash EPROMS, MEM2 to MEM3.

A single chip microcontroller receives a "read" command and issues a flash EPRO
When the data stored in M is read, the data stored in the memory address Mx of the enabled memory block (determined by the block signal BK) is transferred to the destination register via the data bus, bus 1. A is forwarded directly to A. A single chip microcontroller issues a "write / erase" instruction (MOVM
x, A) and the memory of the flash EPROM
When writing / erasing data to / from the address Mx, first, the data and write / erase data stored at the memory address Mx of the enabled memory block are latched in the data / address register 20. After writing / erasing for a predetermined period, a signal CR is generated, the comparator 50 is triggered, and the data at the memory address Mx is compared with the data stored in the data / address register 20.

FIG. 5 is a diagram showing the control signals inside the single chip microcontroller of the present invention. When executing the write / erase operation, first, the data at the memory address Mx and the write / erase data are
Stored in data / address register 20. next,
The flash EPROM 2 is recorded (programmed) for a predetermined period. Thereafter, a signal CR is generated, which triggers the above-described comparison operation, and ensures that the write / erase operation is completed.

In summary, the present invention provides a single chip microcontroller with internal flash memory, thereby eliminating the need for an external EEPROM and its associated devices and programs. Therefore, E
EPROM and its associated devices and programs can be omitted, data (telephone numbers, fax numbers, etc.) can be stored in flash memory and, using a single instruction, identical to data in random access memory Can be read directly.

The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description only. This is not exhaustive and does not limit the invention to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been chosen and described in such a way as to best explain the principles of the invention and its practical application, so that those skilled in the art can contemplate the various embodiments and various modifications that are contemplated for a particular use. The present invention can be understood. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.

[0034]

According to the single-chip microcontroller of the present invention, a memory unit has a static random access memory and a flash EPRO.
M are both built-in and internal flash EPR
The OM can be read directly, similar to a static random access memory, thereby eliminating the need for an external EPROM and its associated programs to modify the data stored therein.

[Brief description of the drawings]

FIG. 1 is a diagram showing the allocation of a memory unit according to the present invention.

FIG. 2 is a timing sequence of the single-chip microcontroller of the present invention when writing data to a flash memory.

FIG. 3 is a timing sequence of the single-chip microcontroller of the present invention when erasing data from a flash memory.

FIG. 4 is an internal block diagram of the single-chip microcontroller of the present invention.

FIG. 5 is a diagram showing control signals in the single-chip microcontroller of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Random access memory 2 Flash memory 10 Memory unit 20 Data / address register 30 Block selection register 40 Write / erase register 50 Comparator

Claims (9)

[Claims] 1. A single-chip microcontroller having an internal flash memory, comprising: reading from a memory unit having a flash EPROM and a static RAM; and reading a read address from the flash EPROM and the static RAM. A central processing unit for directly transferring data at an address to a destination register via a data bus, wherein the central processing unit writes or erases the flash EPROM with respect to a write / erase address and write / erase data. First, the write / erase address and the write / erase data are stored in the data / address register, and then the write / erase address is written /
Write / erase erase data, then write / erase data in the data / address register and the flash E
A single chip microcontroller characterized by comparing data in a PROM. 2. The single-chip microcontroller of claim 1, wherein the flash RAM includes a plurality of blocks sharing the same memory address and enabled by a block select signal. 3. The single-chip microcontroller according to claim 2, wherein the block selection signal is stored in a parameter register. 4. A program for comparing a write / erase data in the flash EPROM with data in a data / address register for a predetermined period after writing or erasing in the flash EPROM, and outputting a signal for guaranteeing completion. The single-chip microcontroller according to claim 1, further comprising a detector. 5. A memory device having a flash memory and a RAM, a data bus, and when reading the flash memory with respect to a read address, transferring data at the read address to a destination register via the data bus. A central processing unit that transfers data directly to the flash memory when writing / erasing the flash memory with respect to the write / erase address and the write / erase data. Storing in the data / address register via the bus, then writing / erasing the flash memory, comparing the write / erase data in the flash memory with the data in the data / address register, Microcontroller that guarantees completion. 6. The microcontroller according to claim 5, wherein the flash memory is an EEPROM. 7. The microcontroller of claim 5, wherein the flash memory comprises a plurality of blocks sharing the same memory address and enabled by a block select signal. 8. The microcontroller according to claim 7, further comprising a parameter register for storing a block selection signal. 9. The microcontroller according to claim 7, further comprising a write / erase register for storing a result of the comparison.