KR20030095820A - Access control device for memory and method thereof - Google Patents

Abstract

PURPOSE: An apparatus for controlling a memory access and a method for the same are provided to reduce the number of access to the memory and to increase the speed of access. CONSTITUTION: An apparatus for controlling a memory access includes a memory detection unit(210), a first mapping unit(232) and a controller(240). The memory detection unit(210) detects the number of memories connected thereto and the size of the page of each memory. The first mapping unit(232) divides the management address in the unit of page in response to the detected number of memories and the size of the page and maps each page of the divided management addresses to each page of the memories, subsequently. And. the controller(240) controls perform a recording operation as to the memories(260-1,260-2,260-3,260-4) based on the mapping result of the first mapping unit(232), subsequently.

Description

Memory access control device and method

The present invention relates to a memory access control apparatus and method, and more particularly, to a memory access control apparatus and method that can improve the number of times and the access speed of the memory.

The flash memory is a removable memory device that deletes data in units of blocks and writes data in units of pages. The erase operation for the flash memory proceeds serially. According to the prior art, the address of each connected flash memory is serially mapped to the management address. The flash controller selects and accesses a corresponding flash memory among the corresponding flash memories based on the mapped address.

However, unlike a general memory, a flash memory must first perform a block-by-block erasing operation to write data. According to the prior art of serially managing an address, attempting to write data over a plurality of blocks continuously accesses the same flash memory.

On the other hand, the erasing operation in the flash memory takes much longer than other operations. Therefore, the flash memory is configured to delete several data at the same time, that is, block by block. However, this configuration has the disadvantage that it takes as much time as the number of blocks to be deleted since the next block must be deleted after one block is deleted.

In addition, when controlling the address of the flash memory serially as in the prior art, since the data must be written after the erase operation, there is a problem that the operation speed is slow. For example, if data is to be recorded over five blocks, five erase operations and five write operations must be performed. This is due to the structure of flash memory, which, unlike general memory, cannot write 1s and 0s directly into memory, but only 0s. That is, the erase operation is performed to change all the data in the flash memory to 1, and then the write operation is performed to write 0 to the required position. For this reason, the flash memory always has to be erased before writing data.

In addition, according to the related art, since the flash memory cannot delete several blocks at the same time from the same flash memory, it is necessary to perform the delete operation and the write operation on the next block after performing the delete operation and the write operation on one block. There are disadvantages.

It is an object of the present invention to provide an access control apparatus and method capable of reducing the number of accesses to a memory and improving the access speed.

1 is a diagram illustrating an internal structure of a flash memory;

2 is a block diagram showing the configuration of an embodiment of a memory access control apparatus according to the present invention;

3 is a flowchart illustrating a process of performing an embodiment of a memory access control method according to the present invention;

4 is a diagram illustrating an example of an address mapping table for deletion according to the present invention;

5 is a diagram showing an example of a recording address mapping table according to the present invention.

In accordance with another aspect of the present invention, there is provided a memory access control apparatus, including: a memory detector configured to detect a number of connected memories and a page size of each of the memories; A first mapping unit for dividing a management address into page units according to the number of detected memories and the page size, and cyclically mapping each of the divided pages of the management address with each of the detected pages; And a controller configured to cyclically perform a write operation on the memory based on the mapping result of the first mapping unit.

Preferably, the second mapping unit divides the management address into block units according to a size of a block composed of a plurality of pages, and cyclically maps the divided management address to each of the detected blocks. The controller further controls to simultaneously perform an erase operation on the plurality of memories based on the mapping result of the second mapping unit.

The first mapping unit sequentially maps pages of a corresponding rank for each of the management address divided by the page and the memory, and sequentially maps pages of a corresponding next rank, and the second mapping unit sequentially blocks. The blocks of ranks corresponding to the management addresses divided by the memory are sequentially mapped to each of the memories, and the blocks of the next ranks corresponding to the next rank are sequentially mapped.

The control unit controls to perform a write operation on another memory at a program time occurring during the execution of a write operation on a specific memory.

Preferably, the memory is a flash memory in which a data erasing operation is performed in units of blocks and a data operation is performed in units of pages constituting the block, and data is simultaneously deleted for a plurality of connected flash memories. An operation is performed and data recording operation is performed in a sequential order.

According to another aspect of the present invention, there is provided a memory access control method, including: detecting a number of connected memories and a page size of each of the memories; A first dividing step of dividing a management address into page units according to the detected number of memories and the page size; A first mapping step of cyclically mapping each of the divided pages of the management address with each of the detected pages of the memory; and cyclically writing operations to the memory based on the mapping result of the first mapping step. It includes; recording step to perform.

Preferably, the second division step of dividing the management address in block units according to the size of the block consisting of a plurality of the page; A second mapping step of cyclically mapping the divided management address with each detected block of the memory; And a deleting step of simultaneously deleting a plurality of the memories based on the mapping result of the second mapping step.

The first mapping step sequentially maps the management address divided by the page unit and the pages of the corresponding ranks for each of the memories, and sequentially maps the pages of the next next rank, and the second mapping step. Sequentially maps the blocks of ranks corresponding to each of the management addresses divided by the block unit and the memory, and then sequentially maps the blocks of the next rank corresponding thereto.

The write step performs a write operation on another memory at a program time occurring during the execution of the write operation on a particular memory.

Preferably, the memory is a flash memory in which a data erasing operation is performed in units of blocks and a data operation is performed in units of pages constituting the block, and data is simultaneously deleted for a plurality of connected flash memories. An operation is performed and data recording operation is performed in a sequential order.

As a result, when the erase operation is performed, the erase operation may be simultaneously performed on a plurality of connected memories, and when the write operation is performed, the write operation may be performed on other memories during the program time. It is shortened.

Hereinafter, a memory access control apparatus and method according to the present invention will be described in detail with reference to the accompanying drawings.

Among the various memory devices, flash memory is a storage medium used in various devices such as digital mobile phones, digital cameras, LAN switches, PC cards of notebook computers, digital set-top boxes, and internal controllers. Flash memory is a non-volatile memory that is continuously powered, and can erase data in units of blocks and write data in units of pages. Flash memory is one of the variants of EEPROM, which is faster than EEPROM because it operates in blocks, unlike EEPROM, which writes and deletes data in bytes.

1 is a diagram illustrating an internal structure of a flash memory. The size of the block 110 of the flash memory 100 is different depending on the size of the flash memory 100. In general, one block 110 is composed of 16 pages, 32 pages, or 64 pages, and FIG. 2 shows an internal structure of a flash memory in which one block 110 is composed of 16 pages. When one page 120 uses 528 bytes of flash memory, one block may be erased to record 8K or 16K bytes of data. In such flash memory, erasing is performed block by block and writing is performed by page.

2 is a block diagram illustrating an embodiment of a memory access control apparatus according to the present invention, and FIG. 3 is a flowchart illustrating a process of performing an embodiment of the memory access control method according to the present invention.

2 and 3, the flash memory access control apparatus 200 includes a flash memory detector 210, a size detector 220, an address mapping unit 230, and a controller 240.

When the power is supplied, the flash memory detector 210 detects the flash memories 260-1 through 260-4 connected through the control bus 250 and the data bus 252 (S300). The detection result of the flash memory detector 210 may be provided to the controller 240, and the controller 240 may determine the number of flash memories 260-1 to 260-4 connected based on the detection result. The detection operation of the flash memory detector 210 may be performed in a flag and play manner. That is, if a flash memory is additionally connected to the bus regardless of whether power is supplied, a method of increasing the number of flash memories may be employed.

Meanwhile, the size detector 220 detects a page size and a block size including a plurality of pages for each of the connected flash memories 260-1 to 260-4 (S310). The timing of performing the detection operation of the size detector 220 is the same as the timing of performing the detection operation of the flash memory detector 220. In addition, the flash memory detector 210 may be configured to perform the function of the size detector 220. The detection result of the size detector 220 is provided to the controller 240.

The address mapping unit 230 may determine the number of flash memories 260-1 to 260-4, the page size and the block size of each of the flash memories 260-1 to 260-4 connected from the controller 240. A mapping table is created by mapping the management addresses and blocks and pages of the flash memories 260-1 to 260-4. The address mapping unit 230 includes a deletion address mapping unit 232 and a recording address mapping unit 234. The address mapping unit 230 may include the number of flash memories 260-1 to 260-4 connected from the flash memory detector 210 and the size detector 220, and the flash memories 260-1 to 260-4. You can also directly input the page size and block size for each.

The deletion address mapping unit 232 may delete the address mapping table based on the number of the flash memories 260-1 to 260-4 connected and the block sizes of the flash memories 260-1 to 260-4. It creates (S320). 4 shows an example of an address mapping table for deletion created by the address mapping unit 232 for deletion.

Referring to FIG. 4, the management address 410 is divided into predetermined units (for example, one unit is 16 pages) to form a management block. In this case, pages 0 to 15 correspond to the first management block, and pages 16 to 31 correspond to the second management block. Each management block also corresponds to a block of each flash memory 260-1 to 260-4 in a sequential order. That is, the first management block with pages 0 to 15 corresponds to the first block of the first flash memory 260-1, and the second management block with pages 16 to 31 is the first block of the second flash memory 260-2. Corresponds to.

When the erase operation is performed on the plurality of flash memories 260-1 to 260-4, all of the connected flash memories 260-1 to 260-4 are simultaneously enabled. Then, the erase command and the page are recorded, and the erase operation is simultaneously performed on blocks (for example, the first block of each flash memory) at the same position (S340). In contrast, while performing an erase operation on an arbitrary block of the first flash memory 260-1, an erase operation is performed on an arbitrary block of the second flash memory 260-2, and then continuously performed on all flash memories. The delete operation may be performed.

When the address is divided and managed in units of blocks as in the present invention, the erase operation is performed on the first flash memory 260-1 while the erase operation is performed on the second flash memory 260-2. The delete operation may be performed on four blocks. That is, when the erase operation is performed over five blocks, the erase operation may be performed on the four flash memories 260-1 to 260-4 at the same time, and then the erase operation may be performed on only one flash memory. Only two block deletions are required.

The write address mapping unit 234 may write a write address mapping table based on the number of flash memories 260-1 to 260-2 connected and the page sizes of the flash memories 260-1 to 260-2. It creates (S420). FIG. 5 shows an example of a recording address mapping table created by the recording address mapping unit 234. As shown in FIG.

Referring to FIG. 5, the first page of the first flash memory 260-1, the first page of the second flash memory 260-2,. It corresponds to the last page of the fourth flash memory 260-4. In this configuration, the address 7 corresponds to the second page of the fourth flash memory 260-4.

The data is cyclically recorded in the flash memories 260-1 to 260-4 using the created write address mapping table (S350). At this time, data recording is performed in units of pages. According to the cyclic sequential recording method, data of page 1 is written in page 1 of the first flash memory 260-1 and data of page 2 is written in page 1 of the second flash memory 260-2. do. As described above, if the address is managed such that data is written to each of the flash memories 260-1 to 260-4 in a sequential order, only about three block writing times are required when writing data over five blocks.

Even if data is input to the flash memory, it takes about 200 ~ 500uSec extra program time internally. Therefore, data can be written to the second flash memory 260-2 while data is written to the first flash memory 260-1 and internally programmed, so that data can be written with only about three block write times. do. As a result, the total time required to record data over five blocks is the sum of two block erase times and about three block write times.

In the above-described embodiment, the case of using the erasing and writing mapping table for address mapping is exemplified. However, the addresses may be mapped in units of blocks or pages in software. In the above-described embodiment, the flash memory has been described as an example. In addition, the memory access control apparatus and method according to the present invention can be applied to other memory devices that delete data in units of blocks or store data in units of pages.

The invention can also be embodied as computer readable code on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, and floppy. Disks, optical data storage, and the like, and also include those implemented in the form of carrier waves (eg, transmission over the Internet). The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

Although the preferred embodiments of the present invention have been shown and described above, the present invention is not limited to the specific preferred embodiments described above, and the present invention belongs to the present invention without departing from the gist of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and such changes are within the scope of the claims.

According to the present invention, it is possible to simultaneously perform an erase operation on a plurality of memories that are connected when performing an erase operation by mapping an address in units of blocks, and different program times during execution of a write operation by mapping addresses in units of pages. Since the write operation to the memory can be performed, the data writing time of the entire memory is shortened. This shortening effect increases as the number of memories increases.

Claims (13)

A memory detector detecting a number of connected memories and a page size of each of the memories; A first mapping unit for dividing a management address into page units according to the number of the detected memory and the page size, and cyclically mapping each of the divided pages of the management address with each of the detected pages; And And a controller configured to perform a cyclical sequential write operation on the memory based on the mapping result of the first mapping unit. The method of claim 1, A second mapping unit for dividing the management address into block units according to a size of a block composed of a plurality of pages, and cyclically mapping the divided management address with each of the detected blocks; , And the control unit controls to simultaneously perform a deletion operation on the plurality of memories based on the mapping result of the second mapping unit. The method of claim 2, The second mapping unit sequentially maps the blocks of ranks corresponding to each of the management addresses divided by the block and the memories in sequence, and sequentially maps the next blocks of the next rank. . The method according to claim 1 or 2, The first mapping unit sequentially maps pages of a corresponding rank to each of the management address divided by the page unit and the memory, and sequentially maps pages of a corresponding next rank. . The method according to claim 1 or 2, And the control unit controls to perform a write operation on another memory at a program time occurring during the execution of a write operation on a specific memory. The method according to any one of claims 1 to 5, The memory is a flash memory in which a data erasing operation is performed in units of blocks and a data operation is performed in units of pages constituting the block. And a data erasing operation for a plurality of connected flash memories simultaneously and a data writing operation in a sequential order. A detection step of detecting the number of connected memories and the page size of each of the memories; Dividing a management address into page units according to the detected number of memories and the page size; A first mapping step of circularly mapping each divided page of the management address with each detected page of the memory; and And a write step of performing a write operation sequentially on the memory based on the mapping result of the first mapping step. The method of claim 7, wherein A second dividing step of dividing the management address into block units according to a size of a block composed of a plurality of pages; A second mapping step of cyclically mapping the divided management address with each detected block of the memory; And And a deleting step of simultaneously deleting a plurality of the memories on the basis of the mapping result of the second mapping step. The method of claim 8, The second mapping step may sequentially map blocks having a rank corresponding to each of the management address divided by the block and each of the memories, and sequentially map the next blocks having the next rank. Way. The method according to claim 7 or 8, The first mapping step may sequentially map the management addresses divided in page units and the pages of the corresponding ranks to the respective memories, and then sequentially map pages of the corresponding next ranks. Control method. The method according to claim 7 or 8, And the writing step performs a writing operation on the other memory at a program time occurring during the execution of the writing operation on the specific memory. The method according to claim 7 or 8, The memory is a flash memory in which a data erasing operation is performed in units of blocks and a data operation is performed in units of pages constituting the block. And simultaneously deleting data and simultaneously writing data to the plurality of connected flash memories. Detecting a number of connected memories and a page size of each of the memories; A first dividing step of dividing a management address into page units according to the detected number of memories and the page size; A first mapping step of circularly mapping each divided page of the management address with each detected page of the memory; and A recording step of performing a recording operation on the memory in a sequential order based on the mapping result of the first mapping step; and reading a program for executing the memory access control method on a computer by using a computer. Recording media.