經濟部中央標準局員工消費合作社印製 A7 丨 <5 / ^ Ο ώ Ο Β7 五、發明説明（i) 本發明是有關於一種單晶片微控制器，且特別是有關 於一種内建快閃記憶體之單晶片微控制器，其記憶體裝置 中兼具有快閃式可抹除且可程式唯讀記憶體（flash EPROM) 及靜態隨機存取記憶體（SRAM)，且，此單晶片微控制器可 直接讀取（以單一指令）快閃式可抹除且可程式唯讀記憶體 中之資料，與一般靜態存取記憶體之讀取程序完全相同。 目前，單晶片微控制器雖然可分為4位元、8位元、 16位元...等等，不過，其基本架構均必須包含以下三大部 分，亦即： 1. 中央處理單元（CPU); 2. 輸入/輸出埠（I/O port);以及 3. 記憶體裝置（Memory)。 而記憶體裝置便是本發明所要探討之重點。 一般而言，單晶片微處理器之記憶體裝置主要是用來 儲存程式與資料，其可分為唯讀記憶體(R Ο Μ)及隨機存取 記憶體（RAM)兩大部分。 1.唯讀記憶體（ROM)，主要是用來儲存程式與固定不 變的資料，當電源消失時，其内容仍然存在。可分為： (a) 罩幕式唯讀記憶體(Mask ROM) 此種記憶體之内容於製造商生產過程中便已儲存， 無法予以更改。 (b) 可抹除且可程式唯讀記憶體（EPROM) 此種記憶體之内容係利用燒錄器燒錄進去（亦即，以 紫外線照射記憶體上方透明窗口約30分鐘，藉以將 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁)A7 printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 丨 &5; ^ 〇 〇 〇 Β7 V. Description of the invention (i) The present invention relates to a single-chip microcontroller, and in particular to a built-in flash memory A single-chip micro-controller of a memory, which has both a flash erasable and programmable read-only memory (flash EPROM) and a static random access memory (SRAM) in the memory device. The microcontroller can directly read (with a single command) the flash-eraseable and programmable data in the read-only memory, which is exactly the same as the normal static access memory. At present, although single-chip microcontrollers can be divided into 4-bit, 8-bit, 16-bit ... etc., their basic architecture must include the following three major parts, namely: 1. Central processing unit ( CPU); 2. I / O port; and 3. Memory. The memory device is the focus of the present invention. Generally speaking, the memory device of a single-chip microprocessor is mainly used to store programs and data. It can be divided into read-only memory (R 0 M) and random access memory (RAM). 1. Read-only memory (ROM) is mainly used to store programs and fixed data. When the power disappears, its content still exists. It can be divided into: (a) Mask ROM This memory has been stored during the manufacturer's production process and cannot be changed. (b) Erasable and Programmable Read-Only Memory (EPROM) The contents of this memory are burned in with a writer (that is, the transparent window above the memory is irradiated with ultraviolet rays for about 30 minutes. Standards are applicable to China National Standard (CNS) A4 specifications (210X297 mm) (Please read the precautions on the back before filling this page)
五、發明説明（2 ) 内容清除），且，可以重覆使用。 0)可電除且可程式唯讀記憶體（EEPROM) 此種記憶體之功能與可抹除且可程式唯讀記憶體 (EPROM)相同，亦須經由燒錄器燒錄，不過，這種 記憶體之内容可以電子訊號直接清除，不須透過紫 外線照射。 2.隨機存取記憶體(ram)，主要是用來存取可變動、 暫存之資料，當電源消失時，内容亦消失。 不過’在許多單晶片微控制器的應用（如電話系統） 中，卻有部分系統參數或資料（如電話號碼）是需要長期儲 存，且可能在一段時間後加以修改的。因此，習知單晶片 微控制器便無法達到這方面的要求。 通常，為長期儲存這些系統參數或資料，單晶片微控 制器可以在外部增加一組可電除且可程式唯讀記憶體 (EEPR0M) ’用來儲存這些系統參數或資料。不過，這組 可電除且可程式唯讀記憶體卻必須搭配其他界面裝置及控 制電路，使得硬體成本增加。此外，由於可電除且可程式 唯頃記憶體之存取必須依賴煩複的燒錄、讀取程序（有時亦 扁要尚坚）因此，硬體線路與程式編寫的複雜度亦會大幅 提高。 有鑑於此，本發明的主要目的便是在提出一種内建快 問記憶體之單晶片微控制器，其不僅可以省去外接可電除 且可程式唯讀記憶體（EEpR〇M)而衍生之硬體成本以及硬 體線路/程式編寫難度，同時亦可以克服靜態隨機存取記憶 請 先 閣 讀 背 之 i )裝 頁 線 )! 經濟部中央標準局β;工消費合作社印製 Μ Β7 經濟部中央標準局員工消費合作杜印製 五、發明説明（3 ) ' ~~~ 體（SRAM)無法長期儲存資料之困境。 為達成本發明之上述和其他目的，本發明乃提出—種 内，决閃3己憶體之單晶片微控制器，其記憶體裝置中兼具 有▲靜態隨機存取記憶體（SRAM)及快閃式可抹除且可程^ 唯項§己憶體(EPROM)，因此可應用於電話傳真系統中儲存 電話號碼等資料。並且，由於本發明單晶片微控制器可直 接讀取快閃式可抹除且可程式唯讀記憶體之資料，亦即與 靜態隨機存取記憶體之讀取程序完全相同，因此亦可省去 外接快閃式可電除且可程式唯讀記憶體所衍生之硬體成本 及煩瑣之程式編寫。 在本發明中，内建快閃記憶體之單晶片微控制器係具 有-中央處理器單元及一記憶體裝置。其中，記憶體裝置 中同時叹有快閃式可抹除且可程式唯讀記憶體及靜態隨機 存取記憶體。快閃記憶體之讀取動作，係根據一讀取位址， 直接將對應資料由資料匯流排，送至目的暫存器。而快閃 =憶體之寫入/清除動作則是將一寫入位址及一寫入 料二暫存於資料/位址暫存器中，待寫入/清除動作完成 預疋時間後比較快閃記憶體及資料/位址暫存器之資料， 以確認寫入/清除動作之完成。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易It，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式 第1圖係本發明單晶片微控制器中記憶體装置之記憶 資 藉 請 先 閱 讀 背 之 注 意— 事 項 再^ 填 ，r)寻 頁 訂 線 本紙張尺度適 A4規格（210x297公釐） 經濟部中央標準局員工消費合作杜印製 A7 , B7 五、發明説明（4 ) 體配置圖； 第2圖係本發明單晶片微控制器將資料寫入可抹除且 可程式唯讀記憶體之時序示意圖； 第3圖係本發明單晶片微控制器自可抹除且可程式唯 讀記憶體讀取資料之時序示意圖； 第4A圖係本發明單晶片微控制器之内部架構圖；以 及 第4B圖係本發明單晶片微控制器中各控制信號之示 意圖。 實施例 在習知單晶片微控制器之記憶體裝置中，由於唯讀記 憶體（ROM)只能夠儲存程式及固定不變之資料，隨機存取 記憶體(RAM)只能夠儲存可變動及暫時性之資料，因此並 無法應用在如電話或傳真等系統中，用以長期儲存如電話 號碼等資料。且，外接可電除且可程式唯讀記憶體 (EEPROM)又會衍生其他之硬體成本及設計難度。因此， 本發明單晶片微控制器乃將記憶體裝置中部分隨機存取記 憶體以快閃式可抹除且可程式唯讀記憶體(EPROM)取代。 請參考第1圖，此為本發明單晶片微控制器中記憶體 裝置之配置圖。其中，為說明方便起見，本實施例係以4 位元單晶片微控制器為例。圖中，隨機存取記憶體1係設 置於位址000H〜1FFH，而快閃式可抹除且可程式唯讀記憶 體2(包括四個記憶體區塊bankO，bankl，bank2，bank3) 則分享相同位址200H〜3FFH，並以區塊選擇信號BK決定 I-I--^------裝-- (請先閲讀背面之注f事項尽填頁) 、1 © 線 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） A7 , B7五、發明説明（5 ) 何者致能，其中bank2、bank3即屬本裝置。區塊選擇信 號BK係儲存於一 4位元區塊參數暫存器中，其内容如下 所列： BK3 BK2 BK1 ΒΚ0 * 氺 0 0 * * 0 1 氺 氺 1 0 * 氺 1 1 請 it 閱 經濟部中央標準局員工消費合作社印製 選擇記憶體區塊bankO 選擇記憶體區塊bankl 選擇記憶體區塊bank2 選擇記憶體區塊bank3註 當區塊選擇信號BK為[**00]時，記憶體區塊bankO致 能；當區塊選擇信號BK為[**01]時，記憶體區塊bankl致 能；當區塊選擇信號BK為[**10]時，記憶體區塊bank2致 能；而當區塊選擇信號BK為[**11]時，則記憶體區塊bank3 致能。 接下來，說明本發明單晶片微控制器如何對快閃式可 抹除且可記憶體裝置進行讀寫。 1.將資料"寫入"快閃式可抹除且可程式唯讀記憶體 之程序 請參考第2圖，此為本發明單晶片微控制器將資料” 寫入"快閃式可抹除且可程式唯讀記憶體之時序示意圖。 其範例如下所列： MOVBK，#02H ;選擇記憶體區塊bank2 MOV Mx 5 A ;將A的值搬入Mx位址内 delay 1 CLR PROG ; PROG訊號拉至低電位 *=don't care yi} 事 項 再-5. Description of the invention (2) Content removal), and can be used repeatedly. 0) Erasable and Programmable Read-Only Memory (EEPROM) This kind of memory has the same function as erasable and Programmable Read-Only Memory (EPROM) and must be programmed by a writer. However, this kind of memory The contents of the memory can be directly cleared by electronic signals, and do not need to be exposed to ultraviolet rays. 2. Random access memory (ram) is mainly used to access variable, temporary data. When the power disappears, the content also disappears. However, in many single-chip microcontroller applications (such as telephone systems), some system parameters or information (such as telephone numbers) require long-term storage and may be modified after a period of time. Therefore, conventional single-chip microcontrollers cannot meet this requirement. Generally, for long-term storage of these system parameters or data, a single-chip micro-controller can externally add a set of removable and programmable read-only memory (EEPR0M) 'to store these system parameters or data. However, this set of removable and programmable read-only memory must be equipped with other interface devices and control circuits, which increases the hardware cost. In addition, because the removable memory and programmable memory must rely on the tedious programming and reading procedures (sometimes it is too tough), the complexity of the hardware circuit and programming will also be greatly increased. improve. In view of this, the main object of the present invention is to propose a single-chip microcontroller with built-in memory, which can not only be derived from externally removable and programmable read-only memory (EEpROM). The hardware cost and the difficulty of programming the hardware circuit / program, but also can overcome the static random access memory. Please read the first i) Page binding line)! Central Standards Bureau of the Ministry of Economy β; printed by industrial and consumer cooperatives Β7 Economy The consumer cooperation of the Ministry of Standards, the Ministry of Standards, and the printing of the five. Invention Description (3) '~~~ The dilemma of the inability of the SRAM to store data for a long time. In order to achieve the above and other objectives of the present invention, the present invention proposes a single-chip microcontroller with a flash memory of 3 flash memory, which has a ▲ static random access memory (SRAM) and The flash type can be erased and can be programmed ^ § § Memory (EPROM), so it can be used to store phone numbers and other information in the telephone fax system. In addition, since the single-chip microcontroller of the present invention can directly read the data of the flash-type erasable and programmable read-only memory, that is, the same read process as the static random access memory, it can also save The external flash type can be removed and the hardware cost and cumbersome programming derived from programmable read-only memory. In the present invention, the single-chip microcontroller with built-in flash memory has a central processing unit and a memory device. Among them, the flash memory can be simultaneously erased and programmed with read-only memory and static random access memory. The reading operation of the flash memory is to directly send the corresponding data from the data bus to the destination register according to a reading address. The flashing = memory write / clear operation is to temporarily store a write address and a write material in the data / address register, and compare them after the write / clear operation is completed. Flash memory and data / address register data to confirm the completion of the write / erase operation. In order to make the above and other objects, features, and advantages of the present invention more obvious, it will be described in detail below with reference to a preferred embodiment and the accompanying drawings. The first diagram of the present invention is a single unit of the present invention. Read the memory information of the memory device in the chip microcontroller first. Please read the note below ^ Fill in, r) Page-finding and alignment. The paper size is suitable for A4 size (210x297 mm). Print A7, B7 V. Description of the invention (4) Body configuration diagram; Figure 2 is a timing diagram of the single-chip microcontroller of the present invention writing data into erasable and programmable read-only memory; Figure 3 is this Timing diagram of self-erasable and programmable read-only memory for inventing a single-chip microcontroller; Figure 4A is an internal architecture diagram of the single-chip microcontroller of the present invention; and Figure 4B is a single-chip microcontroller of the present invention Schematic diagram of the control signals in the controller. Example In a memory device of a conventional single-chip microcontroller, since a read-only memory (ROM) can only store programs and fixed data, a random access memory (RAM) can only store variable and temporary data. It cannot be used in systems such as telephone or fax for long-term storage of information such as telephone numbers. In addition, the externally removable and programmable read-only memory (EEPROM) will incur other hardware costs and design difficulties. Therefore, the single-chip microcontroller of the present invention replaces a portion of the random access memory in the memory device with a flash-type erasable and programmable read-only memory (EPROM). Please refer to FIG. 1, which is a configuration diagram of a memory device in a single-chip microcontroller of the present invention. Among them, for the convenience of description, this embodiment takes a 4-bit single-chip microcontroller as an example. In the figure, the random access memory 1 is set at the address 000H ~ 1FFH, and the flash-type erasable and programmable read-only memory 2 (including four memory blocks bankO, bankl, bank2, bank3) is Share the same address 200H ~ 3FFH, and use the block selection signal BK to decide II-^ ------ install-- (please read the note f on the back and fill in the page first), 1 China National Standard (CNS) Λ4 specification (210X297 mm) A7, B7 V. Invention description (5) Which one is enabled, of which bank2 and bank3 belong to this device. The block selection signal BK is stored in a 4-bit block parameter register. The contents are as follows: BK3 BK2 BK1 ΒΚ0 * 氺 0 0 * * 0 1 氺 氺 1 0 * 氺 1 1 Printed by the Consumer Standards Cooperative of the Ministry of Standards and Standards of the People's Republic of China Select memory block bankO Select memory block bankl Select memory block bank2 Select memory block bank3 Note When the block selection signal BK is [** 00], the memory Block bankO is enabled; when the block selection signal BK is [** 01], the memory block bank1 is enabled; when the block selection signal BK is [** 10], the memory block bank2 is enabled; When the block selection signal BK is [** 11], the memory block bank3 is enabled. Next, how the single-chip microcontroller of the present invention reads and writes to a flash-type erasable and memory device. 1. Please refer to Fig. 2 for the procedure of "writing data" into the flash-type erasable and programmable read-only memory. This is the "write-in" data of the single-chip microcontroller of the present invention. The timing diagram of the erasable and programmable read-only memory. Examples are listed below: MOVBK, # 02H; Select the memory block bank2 MOV Mx 5 A; Move the value of A into the Mx address delay 1 CLR PROG; PROG signal is pulled to low potential * = don't care yi}
裝 頁 訂 Θ、. 線 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 經濟部中央標準局員工消費合作社印製 A 7 ( B7 五、發明説明（6 ) delay2 set PROG ； PROG訊號恢復高電位 在這個範例中，首先將區塊選擇信號BK設為2，表 示選擇記憶體區塊bank2 ;然後，將暫存器A之内容寫入 Mx位址，Mx表示記憶體區塊bank2中之位址，而A則是 欲寫入資料存放之位址。接著，進行寫入動作（如圖中所示 之？^信號），並在動作結束後以寫入/清除信號EP判斷資 料是否成功寫入，如果不成功，則可調整delay2來延長寫 入時間（寫入/清除信號EP係暫存於一寫入/清除暫存器 中，用以表示寫入或清除動作之完成與否）。 2. ”清除"快閃式可抹除且可程式唯讀記憶體中資料之 程序 請參考第3圖，此為本發明單晶片微控制器”清除"快 閃式可抹除且可程式唯讀記憶體中資料之時序示意圖。 其範例如下所列： MOV BK，#03H ;選擇記憶體區塊bank3 MOV Mx，#300H ;選擇位址 300H delay 1Binding, Θ,. The size of the paper is applicable to the Chinese National Standard (CNS) A4 (210X297mm). Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. A 7 (B7 V. Description of the invention (6) delay2 set PROG; The signal returns to high potential. In this example, first set the block selection signal BK to 2 to select the memory block bank2; then, write the contents of the register A to the Mx address, and Mx means the memory block bank2 Address, and A is the address where the data is to be written. Then, perform the write operation (shown as the? ^ Signal in the figure), and judge the data by the write / clear signal EP after the operation is completed. Whether the write was successful. If it is unsuccessful, you can adjust delay2 to extend the write time (the write / clear signal EP is temporarily stored in a write / clear register to indicate the completion of the write or clear action and No). 2. "Erase" flash erasable and programmable data in the read-only memory Please refer to Figure 3, this is a single chip microcontroller of the present invention "Erase" flash erasable Programmable read-only data . Sequence schematic examples of which are listed below: MOV BK, # 03H; selected memory block bank3 MOV Mx, # 300H; select the address 300H delay 1
CLR ERASE delay2 set ERASE 在這個範例中，首先將區塊選擇信號BK設為3，表 示選擇記憶體區塊bank3 ;然後，將Mx指定位址定為 300H，其中，Mx表示記憶體區塊bank2中之位址。接著， 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） I!:———δι———訂！iol (請先閱讀背面之注意事項再填寫本頁) A 7 , B7 五、發明説明（7 ) 進行清除動作（如圖中所示之信號），並在動作結束後 以寫入/清除信號EP判斷資料是否成功寫入，經由以上程 序，即可將位址300H之内容清除為”OFH"，同樣地，使用 者亦可以寫入/清除信號EP判斷資料是否成功清除。 在上述”寫入π或”清除"的動作中，EP信號係儲存於4 位元之暫存器中，用以判斷存取動作是否成功，内容如下 所列： EP3 EP2 EP1 EP0 其中，ΕΡΟ表示結果；ΕΡ1表示寫入資料；ΕΡ2表示 清除資料；而ΕΡ3則為保留位元。當進行”寫”或"清除”程 序後，如果成功，ΕΡ0=0，否則ΕΡ0=1。 3.自快閃式可抹除且可程式唯讀記憶體中讀取資料之 程序 此程序與與一般靜態隨機存取記憶體相同，其範例如 下所列： MOV ΒΚ，#02Η MOV A，Μχ 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 經由此程序，即可將記憶體區塊bank2中Mx位址之 内容讀出放入A暫存器中。 第4A圖為本發明單晶片微控制器之内部架構圖，包 括記憶體裝置1，資料位址暫存器2，區塊參數暫存器3， 寫入/清除暫存器4及比較器5，其中，記憶體裝置1又包 括兩個靜態隨機存取記憶體MEMO，MEM1以及兩個快閃 式可抹除且可程式唯讀記憶體MEM2，MEM3。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 五、 A7 B7 經濟部中央標準局員工消費合作社印製 發明説明（ 當單晶片微控制器對記憶體裝置1中快閃 :式唯讀t已憶體(MEM2或MEM3)進行讀取動作時（當下 A，Mx指令時)，τ訊號係直接將快閃式可抹除且 。王式唯讀記憶體（根據區塊參數暫存器3之區塊選擇信 位址之資料放在資料匯流排MW， 並搬 5 A DUSZ 、& A暫存器。而當單晶片微控制器欲將資料寫入快閃 式可抹除且可程式唯讀記憶體或清除快閃式可抹除且可程 %靖圯憶體中資料時（當下MOV Mx，A指令時），Μχ =，iAddress)和Α暫存器所指之内容首先閉鎖（iatch)在資 厂/位址暫存器2(Data Address Reg)上，待執行完"寫入 Ο及OG)或"清除"(ERASE)動作後計數一預定時間（machine CyCle)以產生一比較訊號CR ,藉以讀*MX位址内容與資 料/位址暫存器閉鎖之資料進行比較（如圖中之比較器5)， 右比較結果相同則寫入/清除暫存器4之EP〇=〇，代表動作 無誤’不相同則EP0=1，代表有錯誤發生。 請參考第4B圖，此為第4A圖單晶片微控制器中各控 制仏號之時序示意圖。當進行寫入/清除（而^或瓦動 作時’ Μχ位址及a暫存器所指的内容首先存放於資料/ 位址暫存器2中（如圖示中Address Reg及Data Reg)等待 寫入/清除動作之進行（如圖示中prog信號)。待寫入/清除 動作結束後，可計數一 循環周期（Machine cycle)，並在隨 後產生—比較信號CR(Compare read)，用以比較Mx位址 内容與資料/位址暫存器2閉鎖之資料。 '综上所述，本發明單晶片微控制器不但可省去因外接 8 本紙張尺度適用中國國家操準（CNS)八4規格（210x297公籍） (請先閱讀背面之注意事項再填寫本頁) 、" Γ 〇 經濟部中央標準局負工消費合作社印製 A 7 , B7 五、發明説明（9 ) 記憶體而衍生之硬體線路及煩瑣燒錄程序，並且可自動比 較"寫入"及"清除"結果，使可靠度達到更高的水準。另外， 本發明單晶片微控制器之内部資料記憶隨機存取裝置可提 供使用者以軟體程式編輯，在不經燒錄器煩複處理的情況 下對記憶内容進行更改。又，本發明單晶片微控制器之資 料讀取和一般靜態隨機存取記憶體一樣便利，可由中央處 理單元直接讀出（只需MOV A，Address —道指令）。 雖然本發明已以一較佳實施例揭露如下，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可做些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (諳先聞讀背面之注意事項再填寫本頁)CLR ERASE delay2 set ERASE In this example, first set the block selection signal BK to 3 to select the memory block bank3; then, set the designated address of Mx to 300H, where Mx represents the memory block bank2 Address. Then, 8 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) I!: ——— δι ——— Order! iol (Please read the precautions on the back before filling this page) A 7, B7 V. Description of the invention (7) Perform the clear operation (signal shown in the figure), and write / clear the signal EP after the operation ends Determine whether the data was successfully written. After the above procedure, the content of the address 300H can be cleared to "OFH". Similarly, the user can also write / clear the signal EP to determine whether the data was successfully cleared. In the "clear" action, the EP signal is stored in a 4-bit register to determine whether the access operation is successful. The contents are as follows: EP3 EP2 EP1 EP0 where EP0 indicates the result; EP1 indicates the write Enter data; EP2 means to clear data; EP3 is a reserved bit. After the "write" or " clear "procedure, if successful, EP0 = 0, otherwise EP0 = 1. 3. Self-flashing erasable and programmable data-only memory. This procedure is the same as the general static random access memory. Examples are as follows: MOV ΒΚ, # 02Η MOV A, Μχ Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) After this procedure, the contents of the Mx address in the memory block bank2 can be read into the A register . FIG. 4A is an internal architecture diagram of the single-chip microcontroller of the present invention, including a memory device 1, a data address register 2, a block parameter register 3, a write / clear register 4 and a comparator 5 Among them, the memory device 1 further includes two static random access memories MEMO, MEM1 and two flash-type erasable and programmable read-only memories MEM2, MEM3. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 5. A7 B7 printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs printed a description of the invention (when the single-chip microcontroller flashes to the memory device 1): When the read-only t memory (MEM2 or MEM3) is performing a read operation (when the A or Mx instruction is issued), the τ signal is directly erasable and flash-type. Wang-type read-only memory (temporarily based on block parameters) The data of the block selection address of register 3 is placed on the data bus MW, and the 5 A DUSZ, & A register is moved. When the single-chip microcontroller wants to write the data to the flash type, it can be erased Programmable read-only memory or erasable flash memory, erasable and programmable data in the memory (when MOV Mx, A instruction), Μχ =, iAddress) and the contents of the A register First, it is latched (Iatch) on the factory / address register 2 (Data Address Reg), and after executing the "Write 0 and OG) or" Clear "(ERASE) action, count a predetermined time ( machine CyCle) to generate a comparison signal CR to read * MX address content and data / address register latched data into Comparison (as shown in Comparative 5), the same result is written to the right comparison / 4 of the cleared register EP〇 = square, representative of correct operation 'is not the same as the EP0 = 1, signifies an error. Please refer to Figure 4B. This is a timing diagram of each control key in the single-chip microcontroller in Figure 4A. When writing / erasing (and ^ or tile action), the contents of the Μχ address and a register are first stored in the data / address register 2 (as shown in the figure, Address Reg and Data Reg) and wait The write / clear operation is performed (such as the prog signal in the figure). After the write / clear operation is completed, a cycle can be counted (Machine cycle), and a subsequent comparison signal CR (Compare read) is generated. To compare the contents of Mx address with the data latched by the data / address register 2. In summary, the single-chip microcontroller of the present invention not only eliminates the need for external 8 paper standards for China National Standards (CNS) 8 4 specifications (210x297 citizenship) (Please read the notes on the back before filling out this page), " Γ 〇 Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives A 7, B7 V. Description of the invention (9) Memory The derived hardware circuit and cumbersome programming procedures can automatically compare the results of "write" and "clear" to achieve a higher level of reliability. In addition, the inside of the single-chip microcontroller of the present invention Data memory random access device provides users It is edited with a software program, and the memory content can be changed without the troublesome processing of the writer. In addition, the data reading of the single-chip microcontroller of the present invention is as convenient as general static random access memory and can be processed by the central The unit reads directly (only MOV A, Address — channel instruction). Although the present invention has been disclosed as a preferred embodiment as follows, it is not intended to limit the present invention. Any person skilled in the art will not depart from the present invention. Within the spirit and scope, some changes and retouching can be done, so the scope of protection of the present invention shall be determined by the scope of the attached patent application. This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm) ) (谙 First read the notes on the back before filling out this page)