GB2338321A

GB2338321A - Single chip micro-controller with an internal flash memory

Info

Publication number: GB2338321A
Application number: GB9812642A
Authority: GB
Inventors: Shih-Fu Hsieh; Mao-Song Chen; Shih-Chang Wu
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 1998-06-11
Filing date: 1998-06-11
Publication date: 1999-12-15
Anticipated expiration: 2018-06-11
Also published as: GB9812642D0; GB2338321B

Abstract

A single-chip micro-controller with both a static random access memory and a flash EPROM built into the memory unit 10, which can be used in a telephone or a fax machine for storing telephone or fax numbers. The internal flash EPROM can be directly read in a single step, in the same manner as the static RAM. When performing writing/erasing operations on the flash memory with respect to a write/erase address and write/erase data, the central processing unit first transfers the write/erase data to a data/address register 20, then writes the write/erase data to the write/erase address of the flash memory, and compares the write/erase data in the data/address register with that in the flash memory to ensure that the write/erase is completed. The need for an external EPROM and its related programs for changing data stored therein is eliminated.

Description

2338321 -1 SINGLE-CHIP MICRO-CONTROLLER WITH AN INTERNAL FLASH MEMORY is

The present invention relates to a micro-controller. More particularly, but not exclusively, it relates to a single-chip microcontroller including both a flash erasable programmable read only memory (Flash EPROM) and a static random access memory (SRAM) built into its memory unit, in which the data stored in the flash erasable programmable read only memory is read in a single step, in other words, in the same manner that data stored in static random access memory is read.

For different computers and systems, micro controllers are often divided into 4-bit microcontrollers, 8-bit micro-controllers, 16-bit microcontrollers and so on. Every micro-controller is provided with an I/0 port, a central processing unit (CPU) and a memory unit, wherein the I/0 port is provided for receiving, outputting and transmitting data within the micro-controller; the central processing unit is provided for manipulating the data received or obtained, and the memory unit is provided for storing the data and related programs executed by the central processing unit and usually consists of ROMs (read only memory) and RAMs (random access memory).

A ROM can keep its data even after the power is shut down, thus being suited for the storage of unchanging data or program applications. ROMs are usually classified into mask ROMs, EPROMs (erasable programmable ROM) and EEPROMs (electrically erasable programmable ROM). The data of a mask ROM is pre-written when in production, and cannot be changed thereafter. The data of a EPROM, on the other hand, is written with an EPROM recorder (programmer) by i 1 i irradiating ultraviolet light on a transparent window of the EPROM for about 30 minutes, and can be repeatedly reprogrammed. Similarly, the data of an EEPROM is written with an EEPROM recorder (programmer). However, EEPROM data is replaced or changed by electronic signals, making it more convenient compared to the use of ultraviolet light for EPROMs.

Unlike ROM, a RAM loses its data when the power is shut down, thus being suited for the storage of variable and temporary data.

In some applications, for example a telephone or a fax machine, the memory unit needs to store specific data (like phone numbers or fax numbers) for a long time, but also be able to change the data at certain intervals. For applications requiring the storage of long term temporary data, the memory unit of a conventional single-chip micro-controller cannot be used. Instead, an external EEPROM (electrically erasable programmable ROM) is often provided in the micro-controller to store such kinds of data. But with the external EEPROM arises the need for additional interfaces, control circuits with related programs, and high voltages for recording (programming), therefore substantially increasing the cost and complexity of the single-chip microcontroller.

According to the present invention, there is provided a singlechip microcontroller with an internal flash memory, comprising: a memory unit having a flash EPROM and a static random access memory; and a central processing unit which when reading the flash EPROM and the static random access memory with respect to a read address, directly transfers data at the read address through a data bus to a destination register, and wherein the central processing unit, when writing or erasing the flash EPROM with respect to a write/erase address and write/erase data, first stores the write/erase address and the write/erase data into a data/address register, then writes/erases the write/erase data into/from the write/erase address, and compares the written/erased data in the data/address register with that in the flash EPROM.

An embodiment of the present invention can thus provide a single-chip micro-controller with an internal flash memory, which does not need an external EEPROM or its related devices with complicated programs. Therefore, the cost can be lowered, the data (like phone numbers or fax numbers) can be kept in the flash memory even after the power is shut down, and the data can be read in a single step like that of random access memory.

A single-chip micro-controller embodying the present invention consists of a memory unit and a central processing unit. The memory unit includes both a flash memory and a random access memory built inside. When reading the flash memory with respect to a read address, the central processing unit directly transfers the read data through a data bus to a destination register. In addition, when performing writing/erasing operations on the flash memory with respect to a write/erase address and write/erase data, the central processing unit first transfers the write/erase address and the write/erase data to a data/address register, then puts (stores)/ removes the write/erase data to/from the write/erase address of the flash memory, and compares the write/erase data in the data/address register with that in the flash memory to ensure the write/erase is completed.

In this single-chip micro-controller, the flash memory may be divided into several memory blocks that share the same memory addresses and are enabled by a block-select signal stored in another register.

The following detailed description, given by way is of example and not intended to limit the invention solely to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which:

Fig. 1 is a diagram showing address allocation in a memory unit of a single-chip micro-controller embodying the present invention; Fig. 2 is a timing sequence of the single-chip micro-controller.when writing data to the flash memory; Fig. 3 is a timing sequence of the single-chip micro-controller when erasing data from the flash memory; Fig. 4A is an internal block diagram of the single-chip micro-controller; and Fig. 4B is a diagram showing control signals inside the single-chip microcontroller.

The conventional memory unit of a single-chip micro-controller often consists of a read only memory (ROM) and a random access memory (RAM). However, the ROM can only save unchanged programs and data, while the RAM can only save variable and temporary data, so the memory unit cannot be used to store long term temporary data, like telephone numbers or fax numbers.

Fig. 1 is a diagram indicating the allocation of the memory unit for a single-chip micro-controller embodying the present invention. A 4-bit single-chip microcontroller is taken as an example for the sake of simplicity. The 4-bit single-chip micro-controller consists of a central processing unit (not shown) and a memory unit, the memory unit including both a random access memory 1 and a flash memory 2 built inside.

In Fig. 1, the random access memory 1 (e.g., a SRAM) is located at the memory address 000HlFFE. And the flash memory 2 (e.g., a flash EPROM) is located at the memory address 200H-3FFH. The flash memory 2 is divided into four memory blocks, BankOBank3, which share the same memory address and are enabled and selected by a block- select signal BK (not shown). The block-select signal BK is stored in a register, and the relationship between the block-select signal BK and the enabled memory block is listed in Table I:

Enabled block BK3 BK2 BK1 BKO BankO 0 0 Bankl 0 1 Bank2 1 0 Bank3 1 1 Table 1

Reading from this table, the memory block Banko i enabled when the blockselect signal BK is [001; the memory block Bankl is enabled when the block-select signal BK is [011; the memory block Bank2 is enabled when the block-select signal BK is [101; and the memory block Bank3 is enabled when the block-select signal BK is [111.

The read operation over the flash memory 2 is identical to that over the random access memory 1. When the single-chip micro-controller receives a read, instruction and has the central processing unit read the flash memory 2 with respect to a read address Mx, the central processing unit immediately transfers the data at the memory address Mx through a data bus to a destination register. The following reading steps are listed as an example:

MOV BK,#02H MOV A,Mx enable memory block Bank2 move the value of register Mx into register A In this example, the block-select signal BK is S first set to 2, selecting and enabling the memory block Bank2. Then, the data stored in the memory address Mx is immediately transferred to the destination register A for output.

As opposed to the read operation, the write/erase operation over the flash memory 2 requires a data/address register A to store related write/erase address and write/erase data.

Fig. 2 is a timing sequence for the single-chip micro-controller when writing data to the flash memory 2. The following writing steps are listed as an example..

MOV BK, #02H MOV Mx, A delayl CLRPROG delay2 set PROG enable memory block Bank2 move the value of register A into register Mx set PROG signal to low level set PROG signal to high level In this example, the block-select signal BK is first set to two, selecting and enabling the memory block Bank2. Then, the write data stored in the data/address register A (which stores the write address and the write data and indicates the position to be written in the memory block Bank2) is passed to the memory address Mx. Thereafter, the write data is recorded (programmed) to the flash memory 2 at the memory address Mx of the memory block Bank2 (see 'set PROG signal to low level' above, and Fig. 2). After recording (programming) for a predetermined period, the written data at the memory address Mx of the memory block Bank2 is compared with that stored in the is data/address register A using a comparator to obtain a write/erase signal EP indicating the completion of the write operation. If the write operation is completed (the written data at the memory address Mx of the memory block Bank2 and that stored in the data/address register A are equal), recording (programming) data to the flash memory 2 is stopped (in the above, rset PROG signal to high level,); otherwise, recording (programming) is continued for a sufficient period of time to complete the transfer.

Fig. 3 is a timing sequence of the single-chip micro-controller when erasing data from the flash memory 2. The corresponding erasing steps are listed as an example:

MOV 13K, #03H MOV Mx, COOH delayl CLR ERASE delay2 set ERASE enable memory block Bank2 determine erase address 300H set ERASE signal to low level set ERASE signal to higli level In this example, the block-select signal BK is first set to three, enabling the memory block Bank3. Then, the erase address stored in the data/address register (300H in this case) is passed to the memory address Mx, which indicates the position to erase data at the memory address Mx of the memory block Bank3. Thereafter, data is erased from the memory address Mx of the memory block Bank3 Pset ERASE signal to low level, shown above, as indicated in Fig.3). After erasing for a predetermined period of time, the data at the memory address Mx of the memory block Bank3 is compared with a default value to obtain a write/erase d signal EP indicating the completion of the erase operation. If the erase operation is completed, erasing is stopped (the above set ERASE signal to high level,, also shown in Fig. 3), otherwise, erasing is continued for an extra time period to complete the transfer.

As mentioned above, the write/erase signal EP generated in the write operation and the erase operation can be stored in a 4-bit register, and the relationship between the write/erase signal EP and the completion of write/erase operation is listed in Table II:

EP3 EP2 EPI EPO result write data erase data reserved Table II

When the write operation of the erase operation is completed, the least significant bit of the write/erase signal is set to zero (EPO=O), otherwise, the least significant bit of the write/erase signal is set to one (EPO=1).

Fig. 4A is an internal block diagram of the single-chip micro-controller of this embodiment. The single-chip micro-controller consists of a memory unit 10, a data/address register 20, a block-select register 30, a write/erase register 40 and a comparator 50. The memory unit 10 includes two random access memories, MEMO-MEM1, and two flash EPROMs, MEM2-MEM3.

When the single-chip micro-controller receives a 'read' instruction (MOV A, Mx) and reads the data stored in the flash EPROM, the data stored at the memory address Mx of the enabled memory block (determined by block signal BK) is directly transferred through a data bus Busl to the destination register A. When the single-chip micro-controller receives a is write/erase, instruction (MOV Mx, A) and writes/erases data to/from the memory address Mx of the flash EPROM, the data stored at the memory address Mx of the enabled memory block and the write/erase data are first latched in the data/address register 20. After writing/erasing for a predetermined period of time, a signal CR is generated to trigger the comparator 50 to compare the data at the memory address Mx and that stored in the data/address register A.

Fig. 4B is a diagram showing control signals inside the single-chip micro-controller of Fig. 4A.

When performing a write/erase operation, the data at the memory address Mx and the write/erase data are first stored in the data/address register 20. Then, the flash EPROM 2 is recorded (programmed) for a predetermined period. A signal CR is generated thereafter to trigger the comparing operation described above and ensure the completion of the write/erase operation.

In sum, the invention may provide a single-chip micro-controller with an internal flash memory, thereby eliminating the need for an external EEPROM and its related devices and programs. Therefore, the cost of the EEPROM and its related devices and programs can be saved, and data (like phone numbers or fa x numbers) can be stored in the flash memory and read directly like data in the random access memory, utilizing a single instruction.

The foregoing description of a preferred embodiment of the present invention has been provided for the purposes of illustration and description only.

It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to practitioners skilled in this art. The embodiment was chosen and described to best explain the principles of 10- the present invention and its practical application, thereby enabling those who are skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the following claims and their equivalents.

Claims

CLAIMS is 1. A single-chip micro-controller with an internal flash memory,

comprising: a memory unit having a flash EPROM and a static random access memory; and a central processing unit which, when reading the flash EPROM and the static random access memory with respect to a read address, directly transfers data at the read address through a data bus to a destination register, and wherein the central processing unit, when writing or erasing the flash EPROM with respect to a write/erase address and write/erase data, first stores the write/erase address and the write/erase data into a data/address register, then writes/erases the write/erase data into/from the write/erase address, and compares the written/erased data in the data/address register with that in the flash EPROM.
2. The single-chip micro-controller as claimed in Claim 1, wherein the flash EPROM includes a plurality of blocks that share the same memory addresses and are enabled by a block-select signal.
3. The single-chip micro-controller with an internal flash memory as claimed in Claim 2, wherein the block-select signal is stored in a parameter register.
4. The single-chip micro-controller with an internal flash memory as claimed in Claim 1, 2 or 3, further comprising a comparator for comparing the written/erased data in the flash EPROM with that in the data/address register for a predetermined period after writing or erasing the flash EPROM, and outputting a signal to ensure completion.
5. A micro-controller, comprising: a memory device having a rewritable, nonvolatile memory and a random access memory; a data bus; and a central processing unit which is so arranged that when reading the non- volatile memory vith respect to a read address, data at the read address is directly transferred through the data bus to a destination register, and when writing/erasing the non-volatile memory with respect to a write/erase address and write/erase data, the write/erase address and the write/erase data are first stored via the data bus to a data/address register, then the non-volatile memory is rewritten/erased and the written/erased data in the flash memory is compared with that in the data/address register to verify the completion of said writing/erasing.
6. The micro-controller as claimed in Claim 5, wherein the non-volatile memory is a flash EPROM.
7. The micro-controller as claimed in Claim 5, or 6, wherein the nonvolatile memory consists of a plurality of blocks that share the same memory addresses and are enabled by a block-select signal.
8. The micro-controller as claimed in Claim 7, further comprising a parameter register for storing the block-select signal.
9. The micro-controller as claimed in any of claims 5 to 8, further comprising a write/erase register for storing the outcome of the comparison.
10. A micro-controller substantially as hereinbefore described with reference to the accompanying drawings.

10. A micro-controller substantially as hereinbefore described with reference to the accompanying drawings.

1 Amendments to the claims have been filed as follows 1. A single-chip micro-controller with an internal flash memory, comprising: a memory unit having a flash EPROM and a static random access memory; and a central processing unit which, when reading the flash EPROM and the static random access memory with respect to a read address, directly transfers data at the read address through a data bus to a destination register, and wherein the central processing unit, when writing or erasing the flash EPROM with respect to a write/erase address and write/erase data, first stores the write/erase address and the write/erase data into a data/address register, then writes/erases the write/erase data into/from the write/erase address, and compares the written/erased data in the data/address register with that in the flash EPROM.

2. The single-chip micro-controller as claimed in Claim 1, wherein the flash EPROM includes a plurality of blocks that share the same memory addresses and are enabled by a blockselect signal.

3. The single-chip micro-controller with an internal flash memory as claimed in Claim 2, wherein the block-select signal is stored in a parameter register.

4. The single-chip micro-controller with an internal flash memory as claimed in Claim 1, 2 or 3, further comprising a comparator for comparing the written/erased data in the flash EPROM with that in the data/address register after writing or erasing the flash EPROM for a predetermined period, and outputting a signal to ensure completion.

1 - is 5. A micro-controller, comprising: a memory device having a rewritable, nonvolatile memory and a random access memory; a data bus; and a central processing unit which is so arranged that when reading the non-volatile memory with respect to a read address, data at the read address. is directly transferred through the data bus to a destination register, and when writing/erasing the non-volatile memory with respect to a write/erase address and write/erase data, the write/erase address and the write/erase data are first stored via the data bus to a data/address register, then the non-volatile memory is rewritten/erased and the written/erased data in the non-volatile memory is compared with that in the data/address register to verify the completion of said writing/erasing.

6. The micro-controller as claimed in claim 5, wherein the non-volatile memory is a flash EPROM.

7. The micro-controller as claimed in Claim 5, or 6, wherein the nonvolatile memory consists of a plurality of blocks that share the same memory addresses and are enabled by a block-select signal.

8. The micro-controller as claimed in Claim 7, further comprising a parameter register for storing the block-select signal.

9. The micro-controller as claimed in any of claims 5 to 8, further comprising a write/erase register for storing the outcome of the comparison.