JPH11297769A - Manufacture of bga wiring tape - Google Patents
Manufacture of bga wiring tapeInfo
- Publication number
- JPH11297769A JPH11297769A JP9928898A JP9928898A JPH11297769A JP H11297769 A JPH11297769 A JP H11297769A JP 9928898 A JP9928898 A JP 9928898A JP 9928898 A JP9928898 A JP 9928898A JP H11297769 A JPH11297769 A JP H11297769A
- Authority
- JP
- Japan
- Prior art keywords
- solder ball
- hole
- tape
- dummy sheet
- wiring tape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＣＳＰ（Chip Scale
Package）、特に半田ボールを搭載するＢＧＡ（Ball G
rid Array ）構造用の配線テープの製造方法に関するも
のである。[0001] The present invention relates to a CSP (Chip Scale).
Package), especially BGA (Ball G
rid Array) The present invention relates to a method for manufacturing a wiring tape for a structure.
【０００２】[0002]
【従来の技術】図３には一般的なＢＧＡ構造パッケージ
の横断面を示してある。2. Description of the Related Art FIG. 3 shows a cross section of a general BGA structure package.
【０００３】５はＢＧＡ用配線テープで、基材テープ５
ａに接着剤６が塗布されたものから成る。この配線テー
プ５は、半田ボール４が搭載される穴部分が打ち抜か
れ、導通用の貫通穴（ビアホール）９を具備した配線テ
ープ（テープキャリア）となる。ここで、この配線テー
プ５の基材テープ５ａはポリイミドなどが主な材料とな
る。打ち抜かれた配線テープ５は銅箔８に貼り付けら
れ、エラストマ２を介して半導体チップ１が接着され、
モールド樹脂７で封止される。[0005] Reference numeral 5 denotes a wiring tape for BGA,
a) to which an adhesive 6 is applied. The wiring tape 5 is punched out of a hole portion where the solder ball 4 is mounted, and becomes a wiring tape (tape carrier) having a through hole (via hole) 9 for conduction. Here, the main material of the base tape 5a of the wiring tape 5 is polyimide or the like. The punched wiring tape 5 is attached to a copper foil 8, the semiconductor chip 1 is adhered via an elastomer 2,
It is sealed with a mold resin 7.
【０００４】半導体チップ１は様々の手段によって銅箔
８のパターンと導通が図られるが、図ではボンディング
ワイヤ３を用いた例を示した。The semiconductor chip 1 can be electrically connected to the pattern of the copper foil 8 by various means. In the figure, an example using the bonding wires 3 is shown.
【０００５】ここで貫通穴９の形成は、打ち抜き、レー
ザ、エッチングなどによって行われるのが一般的であ
る。Here, the formation of the through holes 9 is generally performed by punching, laser, etching, or the like.
【０００６】[0006]
【発明が解決しようとする課題】図４には打ち抜きによ
って形成された貫通穴９の断面を示してある。配線テー
プ５は接着剤６の表面に、カバーフィルム１２が積層さ
れたままで打ち抜かれるが、その積層構造に起因して、
穿孔された穴１０は、どうしても半田ボール４側が狭く
なるような穴形状となってしまう。このような半田ボー
ル側が狭くなった穴１０では半田ボール４に基材テープ
５ａのエッジが食い込み、繰り返し熱応力が加わったと
きの亀裂の起点になる。亀裂が進展すると半田が剥がれ
るなど、半導体パッケージとしての信頼性が低下するこ
とになる。FIG. 4 shows a cross section of a through hole 9 formed by punching. The wiring tape 5 is punched out while the cover film 12 is laminated on the surface of the adhesive 6, but due to the laminated structure,
The perforated hole 10 has a hole shape in which the solder ball 4 side is inevitably narrowed. In such a hole 10 where the solder ball side is narrowed, the edge of the base tape 5a bites into the solder ball 4 and becomes a starting point of a crack when repeated thermal stress is applied. If the cracks develop, the solder peels off, and the reliability as a semiconductor package decreases.
【０００７】図５には、良好な穴形状として、半田ボー
ル４側が広くなった穴形状の穴１１を示しているが、こ
のようにボールを受ける形状の穴であれば、上記した半
田ボールのクラックを防ぐことが可能となる。このよう
な半田ボール４側が広くなった穴１１の形成は、エッチ
ング、レーザなどの加工方法によって実現できるが、量
産性を考えると金型を用いた打ち抜き法を用いる必要が
あり、打ち抜きによって、図５に示す穴１１のように半
田ボール４側が広くなった穴形状を実現する必要があ
る。FIG. 5 shows a hole 11 having a hole shape in which the solder ball 4 side is widened as a good hole shape. Cracks can be prevented. The formation of such a hole 11 having a wider solder ball 4 side can be realized by a processing method such as etching or laser. However, in view of mass productivity, it is necessary to use a punching method using a die. It is necessary to realize a hole shape in which the solder ball 4 side is widened like the hole 11 shown in FIG.
【０００８】そこで、本発明の目的は上記した従来技術
の欠点を解消し、半田ボール側で広くなった断面形状の
半田ボール穴を打ち抜きによって得ることができるＢＧ
Ａ用配線テープの製造方法を提供することにある。Accordingly, an object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to obtain a BG which can be obtained by punching a solder ball hole having a wider cross section on the solder ball side.
An object of the present invention is to provide a method for manufacturing a wiring tape for A.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するた
め、本発明によるＢＧＡ用配線テープの製造方法は、半
田ボールを搭載する穴をパンチにより打ち抜こうとする
配線テープのダイ側にダミーシートを配置し、そのダミ
ーシートを介して打ち抜きを行なうことにより、半田ボ
ール側で広くなった断面形状の穴を形成するものである
（請求項１）。前記ダミーシートには、ポリエチレンテ
レフタレート（ＰＥＴ）、テフロン、ポリエチレン等の
軟質シートを用い（請求項２）、そのダミーシートの厚
さは、打ち抜かれるテープ基材の０．５〜１倍程度の厚
さのもの（請求項３）とするのが好ましい。In order to achieve the above object, a method of manufacturing a wiring tape for BGA according to the present invention comprises a dummy sheet on a die side of a wiring tape in which holes for mounting solder balls are to be punched out by a punch. Are formed, and punching is performed through the dummy sheet to form a hole having a wider cross-sectional shape on the solder ball side (claim 1). A soft sheet such as polyethylene terephthalate (PET), Teflon, or polyethylene is used for the dummy sheet (Claim 2), and the thickness of the dummy sheet is about 0.5 to 1 times the thickness of the tape base material to be punched. (Claim 3).
【００１０】本発明の要旨は、ＢＧＡ用配線テープの製
造方法において、貫通穴を加工する際に配線テープのダ
イ側に、ダミーシートとしてＰＥＴなどの軟質シートを
敷いたことにある。このようにダミーシートを介して打
ち抜きを行なうと、半田ボール側で広くなった断面形状
の穴を形成することができる。従って、本発明によれ
ば、打ち抜きによる加工法でありながら、穴の断面形状
がボールを受ける形になるため、半田ボールに対する基
材テープのエッジの食い込みがなくなり、繰り返し熱応
力が加わったときに穴が亀裂の起点になる現象の発生を
避けることができる。よって、半田ボール側が狭くなっ
た穴の場合に較べ、パッケージとしての信頼性を向上す
ることができる。The gist of the present invention is that, in the method of manufacturing a wiring tape for BGA, a soft sheet such as PET is laid as a dummy sheet on the die side of the wiring tape when the through hole is processed. When punching is performed through the dummy sheet as described above, a hole having a wider cross section can be formed on the solder ball side. Therefore, according to the present invention, the cross-sectional shape of the hole becomes a shape for receiving the ball, even though it is a processing method by punching, so that the edge of the base tape does not bite into the solder ball, and when the thermal stress is repeatedly applied. The occurrence of a phenomenon in which a hole becomes a starting point of a crack can be avoided. Therefore, the reliability as a package can be improved as compared with the case where the hole on the solder ball side is narrowed.
【００１１】[0011]
【発明の実施の形態】以下、本発明を図示の実施形態に
基づいて説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on the illustrated embodiment.
【００１２】図２に、これまでの打ち抜き方法で加工さ
れたＢＧＡ用配線テープ５の貫通穴９の断面を示してい
る。打ち抜かれる配線テープ５は、ポリイミドなどを材
料とする基材テープ５ａ、接着剤６、および接着剤のカ
バーフィルム１２から構成されている。この配線テープ
５は、打ち抜き後にカバーフィルム１２が剥がされてＣ
ｕ箔がラミネートされるため、打ち抜きはカバーフィル
ム１２と同時に行なわれ、またその打ち抜き方向も、Ｃ
ｕ箔のラミネートを良好とするため、カバーフイルム１
２側からパンチが入る方向とする必要がある。FIG. 2 shows a cross section of the through hole 9 of the BGA wiring tape 5 processed by the conventional punching method. The punched wiring tape 5 includes a base tape 5a made of polyimide or the like, an adhesive 6, and a cover film 12 of the adhesive. After the punching, the cover film 12 is peeled off,
Since the u-foil is laminated, punching is performed simultaneously with the cover film 12, and the punching direction is C
In order to improve the lamination of u foil, cover film 1
The direction must be such that the punch enters from two sides.
【００１３】この打ち抜き方向ではパンチとダイ各々か
ら独立にクラックが進展し、図４のように開口部が閉じ
た状態になるのは避けられない。In this punching direction, cracks independently propagate from the punch and the die, and it is inevitable that the opening is closed as shown in FIG.
【００１４】図１に本発明の打ち抜き方法による一実施
形態を示す。本実施形態では、ＢＧＡ用配線テープ５の
基材テープ５ａのダイ側に、軟質のダミーシート１３を
敷き、そのシートを一緒に打ち抜く。本打ち抜きに使用
する軟質のダミーシート１３は、ＰＥＴ（ポリエチレン
テレフタレート）、テフロン、ポリエチレン等の軟質の
もので、打ち抜かれるテープ基材である基材テープ５ａ
の０．５〜１倍程度の厚さを有するものが好ましい。あ
まり薄いとダミーシートの効果がなく、また、あまり厚
いと必要とする打ち抜き力が大きくなるからである。FIG. 1 shows an embodiment according to the punching method of the present invention. In the present embodiment, a soft dummy sheet 13 is laid on the die side of the base tape 5a of the BGA wiring tape 5, and the sheet is punched out together. The soft dummy sheet 13 used for the main punching is a soft material such as PET (polyethylene terephthalate), Teflon, or polyethylene, and is a base tape 5a which is a tape base to be punched.
It is preferable to have a thickness of about 0.5 to 1 times the thickness. If the thickness is too thin, the effect of the dummy sheet is not obtained, and if the thickness is too thick, the required punching force becomes large.
【００１５】このようにダミーシート１３を介して打ち
抜くと、ダミーシート１３の穴は図示したように開口部
が閉じた形状（半田ボール側が狭くなった断面形状）と
なるが、基材テープ５ａのクラックは進展が遅れ、パン
チからのクラック進展を待って剪断が行われる。そのた
め、上下の亀裂が会合するようにクラックが進展し、図
１に示すように基材テープ５ａの穴１４の形状は、開口
部が開いた形状（半田ボール側が広くなった断面形状）
となり、ボールを受けるのに適した良好な形となる。よ
って、半田ボール４に対する基材テープ５ａのエッジの
食い込みがなくなり、繰り返し熱応力が加わったときに
穴９が亀裂の起点になる現象の発生を避けることができ
る。よって、半田ボール側が狭くなった穴の場合に較
べ、パッケージとしての信頼性を向上することができ
る。When punching through the dummy sheet 13 as described above, the hole of the dummy sheet 13 has a shape in which the opening is closed (the cross-sectional shape in which the solder ball side is narrowed) as shown in FIG. The crack progresses slowly, and shearing is performed waiting for the crack to progress from the punch. As a result, the cracks develop so that the upper and lower cracks meet, and as shown in FIG. 1, the shape of the hole 14 of the base tape 5a has a shape with an opening (a cross-sectional shape with a wider solder ball side).
And a good shape suitable for receiving the ball. Therefore, the edge of the base tape 5a does not bite into the solder ball 4, and a phenomenon that the hole 9 becomes a starting point of a crack when repeated thermal stress is applied can be avoided. Therefore, the reliability as a package can be improved as compared with the case where the hole on the solder ball side is narrowed.
【００１６】[0016]
【発明の効果】以上説明したように、本発明によるＢＧ
Ａ用配線テープの製造方法は、半田ボールを搭載する穴
をパンチにより打ち抜こうとする配線テープのダイ側
に、ダミーシートを配置し、そのダミーシートを介して
打ち抜きを行なうことにより、半田ボール側で広くなっ
た断面形状の穴を形成するものである。従って、本発明
によれば、打ち抜きによる加工法でありながら、穴の断
面形状がボールを受ける形になるため、半田ボールに対
する配線テープのエッジの食い込みがなくなり、繰り返
し熱応力が加わったときに穴が亀裂の起点になる現象の
発生を避けることができる。よって、半田ボール側が狭
くなった穴の場合に較べ、半田ボールの信頼性を維持し
てパッケージとしての信頼性を向上することができる。As described above, the BG according to the present invention is
The method of manufacturing the wiring tape for A is such that a dummy sheet is arranged on the die side of the wiring tape in which a hole for mounting a solder ball is to be punched by a punch, and punching is performed through the dummy sheet. This is to form a hole having a wider cross section on the side. Therefore, according to the present invention, since the hole has a cross-sectional shape receiving the ball while being a processing method by punching, the edge of the wiring tape does not bite into the solder ball, and the hole is cut when thermal stress is repeatedly applied. Can be prevented from becoming a starting point of the crack. Therefore, the reliability of the package can be improved by maintaining the reliability of the solder ball as compared with the case where the hole on the solder ball side is narrowed.
【図１】本発明の製造方法により打ち抜いたＢＧＡ用配
線テープの穴の形状を示した断面図である。FIG. 1 is a cross-sectional view showing the shape of a hole in a BGA wiring tape punched out by a manufacturing method of the present invention.
【図２】通常の打ち抜き方法により打ち抜いたＢＧＡ用
配線テープの穴の形状を示した断面図である。FIG. 2 is a cross-sectional view showing the shape of a hole in a BGA wiring tape punched by a normal punching method.
【図３】一般的なＢＧＡパッケージの構造を示す断面図
である。FIG. 3 is a cross-sectional view illustrating a structure of a general BGA package.
【図４】従来の打ち抜きにより形成される貫通穴の断面
形状を示した断面図である。FIG. 4 is a cross-sectional view showing a cross-sectional shape of a through hole formed by conventional punching.
【図５】従来のレーザにより形成される貫通穴の断面形
状を示した断面図である。FIG. 5 is a cross-sectional view showing a cross-sectional shape of a through hole formed by a conventional laser.
１ 半導体チップ ２ エラストマ ３ ボンディングワイヤ ４ 半田ボール ５ 配線テープ ５ａ 基材テープ（テープ基材） ６ 接着剤 ７ モールド樹脂 ８ 銅箔パターン ９ 導通用の貫通穴 １０ 半田ボール側が狭くなった穴 １１ 半田ボール側が広くなった穴 １２ カバーフィルム １３ ダミーシート １４ 基材テープの穴 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Elastomer 3 Bonding wire 4 Solder ball 5 Wiring tape 5a Base tape (tape base material) 6 Adhesive 7 Mold resin 8 Copper foil pattern 9 Through hole for conduction 10 Hole with narrow solder ball side 11 Solder ball Hole with wider side 12 Cover film 13 Dummy sheet 14 Hole in base tape
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉岡 修 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Osamu Yoshioka 3550 Kida Yomachi, Tsuchiura City, Ibaraki Pref.
Claims (3)
ち抜こうとする配線テープのダイ側にダミーシートを配
置し、そのダミーシートを介して打ち抜きを行なうこと
により、半田ボール側で広くなった断面形状の穴を形成
することを特徴とするＢＧＡ用配線テープの製造方法。A dummy sheet is arranged on a die side of a wiring tape on which a hole for mounting a solder ball is to be punched out by a punch, and punching is performed through the dummy sheet, so that the solder ball becomes wider on the solder ball side. A method of manufacturing a wiring tape for BGA, wherein a hole having a cross-sectional shape is formed.
タレート、テフロン（登録商標）、ポリエチレン等の軟
質シートを用いることを特徴とする請求項１記載のＢＧ
Ａ用配線テープの製造方法。2. The BG according to claim 1, wherein a soft sheet made of polyethylene terephthalate, Teflon (registered trademark), polyethylene or the like is used as the dummy sheet.
A method for manufacturing a wiring tape for A.
基材の０．５〜１倍程度の厚さのものを用いることを特
徴とする請求項２記載のＢＧＡ用配線テープの製造方
法。3. The method of manufacturing a BGA wiring tape according to claim 2, wherein the dummy sheet has a thickness of about 0.5 to 1 times a thickness of a tape base material to be punched.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9928898A JPH11297769A (en) | 1998-04-10 | 1998-04-10 | Manufacture of bga wiring tape |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9928898A JPH11297769A (en) | 1998-04-10 | 1998-04-10 | Manufacture of bga wiring tape |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11297769A true JPH11297769A (en) | 1999-10-29 |
Family
ID=14243468
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9928898A Pending JPH11297769A (en) | 1998-04-10 | 1998-04-10 | Manufacture of bga wiring tape |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11297769A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100690999B1 (en) * | 2001-06-28 | 2007-03-08 | 주식회사 하이닉스반도체 | Method for mounting ball grid array package |
| JP2009023017A (en) * | 2007-07-17 | 2009-02-05 | Nippon Mektron Ltd | Composite sheet member punching method |
-
1998
- 1998-04-10 JP JP9928898A patent/JPH11297769A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100690999B1 (en) * | 2001-06-28 | 2007-03-08 | 주식회사 하이닉스반도체 | Method for mounting ball grid array package |
| JP2009023017A (en) * | 2007-07-17 | 2009-02-05 | Nippon Mektron Ltd | Composite sheet member punching method |
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