JPH11297623A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce disconnection on a gate electrode and to improve yield by forming a non-single crystal semiconductor film on an insulating substrate, crystallizing the non-single crystal semiconductor film, and oxidizing a part of the crystallized non-single crystal semiconductor film in a pressurized atmosphere. SOLUTION: A ground film 11 made of silicon oxide is placed on an insulating substrate 10 by using a sputtering method, and a non-single crystal amorphous silicon film 12 is formed on the ground film 11 by using a plasma CVD method. Next, a silicon nitride film is successively formed thereon, and only the silicon nitride film is etched so as to form mask films 13a and 13b used for an oxidization process. And then, the amorphous silicon film 12 is crystallized in an atmosphere of nitrogen at 1 atmospheric pressure. Parts of the crystallized amorphous silicon film 12, that are not covered with the mask films 13a and 13b, are oxidized to the bottoms so as to form silicon oxide regions 14a to 14c. Thus, the amorphous silicon film 12 is divided into regions 15a and 15b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure and a manufacturing method of a semiconductor integrated circuit having at least two thin film transistors (TFTs) on the same substrate. The semiconductor integrated circuit manufactured by the present invention is used for an active matrix of a liquid crystal display and the like.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor is formed by patterning a thin film semiconductor region (active layer) into an island shape to separate it from other thin film transistors.
An insulating film was formed by a VD method or a sputtering method, and a gate electrode was formed thereon.

FIG. 2 shows an example of a manufacturing process of a semiconductor integrated circuit having a thin film transistor according to a conventional method. First, a base film 22 and a silicon film 23 are formed on a substrate 21. Then, films 24a and 24b of a material such as a photoresist are selectively formed on the silicon film 23. Coatings 24a, 2
A thin film of silicon oxide or silicon nitride may be provided between 4b and the silicon film 23 to prevent contamination. (Figure 2
(A)) Thereafter, the silicon film 23 is etched using the coatings 24a and 24b as masks to form island-shaped silicon regions (active layers) 25a and 25b. At the same time, the underlying film 22 is also partially etched. Therefore, the step increases by the overetch x in addition to the thickness of the silicon film. (Figure 2
(B))

After that, an insulating film 26 functioning as a gate insulating film is formed on the entire surface, and further, a gate electrode / wiring 27 is formed.
n, 27p and 27c are formed. At this time, if the step of the active layer is large, the gate electrode may be disconnected. After forming the gate electrode, impurities are implanted by means such as ion doping and ion implantation, and this is thermally annealed.
Activation is performed by laser annealing, lamp annealing, or the like to obtain impurity regions 28n (n-type) and 28p (p-type). Thereafter, an interlayer insulator 29 is deposited, a contact hole is formed therein, and an electrode 30 is formed in the impurity region of the TFT.
a, 30b and 30c are formed.

[0005]

In such a conventional method, over-etching of the underlayer indicated by y in FIG. 2B has become a problem. When the step exists, the gate electrode is disconnected, and the yield decreases. In particular, when a film having a large etching rate is used as the base film, the step becomes large. From the viewpoint of mass production, the plasma CV
Although a film produced by the D method or the APCVD method is preferable, such a film cannot be used because of a high etching rate. An object of the present invention is to provide a TFT with a high yield and a method for manufacturing the TFT by reviewing such a conventionally used method of separating elements between TFTs.

[0006]

According to the present invention, electrical isolation is achieved by selectively thermally oxidizing the silicon film at 500 to 650 ° C. instead of separating the silicon film to separate elements. Perform The silicon film to be oxidized may be amorphous or crystalline. The thickness of the silicon film is 100 to 1500 °, preferably 1000 ° or less, more preferably 500 ° or less. The substrate has a strain temperature (strain point) of 750 ° C. as represented by Corning 7059 glass (alkali-free, borosilicate glass).
The following various glass substrates are used.

What is important is that the non-single-crystal silicon such as amorphous or polycrystalline has an oxidation rate about twice as large as that of single-crystal silicon.
Further, in the present invention, in order to further increase the oxidation rate, 0.1 to 100% of water is added to the atmosphere. Thereby, the oxidation rate can be increased by about 10 as compared with the dry atmosphere. FIG. 5 shows the oxidation method (water vapor partial pressure 100
%) Shows the relationship between the thickness of the silicon oxide obtained and the time, and shows that the silicon film of the present invention is entirely oxidized at a low temperature of 550 to 600 ° C.

In order to further improve the oxidation rate, it is preferable to perform oxidation in a pressurized atmosphere of 1 to 15 atm. For example, in a steam atmosphere of 10 atm, an oxidation rate 10 times higher than that in a steam atmosphere of 1 atm can be obtained.
Further, the oxidation temperature can be lowered. FIG. 5 also shows the change in the oxidation rate at 4 atm. In order to stabilize the amount of water vapor in the atmosphere, a so-called pyrogenic oxidation method may be used. This is a method in which pure hydrogen is burned to generate steam. By controlling the inflow of hydrogen, the concentration of steam in the atmosphere is determined.

In order to selectively perform oxidation, a silicon nitride film on a silicon film or a film having a multilayer structure in which silicon nitride is stacked on silicon oxide is selectively formed as a mask film for oxidation, and then thermally oxidized. You just have to let the atmosphere. The oxidation reaction does not proceed on the surface covered by such a mask film.

[0010]

As described above, according to the present invention, since an oxide is formed by thermal oxidation, a step such as that generated in the conventional etching of a silicon film does not occur, so that disconnection of the gate electrode is reduced and the yield is improved. In particular, in the present invention, since there is almost no influence of the underlying film, there is no restriction on the film forming method, and it is possible to increase the total mass productivity.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

[0012]

[Embodiment 1] FIG. 1 shows a manufacturing process of this embodiment. 1A to 1D are cross-sectional views,
(E) shows a view from above. First, the substrate (Corning 7059) was set at a temperature higher than the strain point (593 ° C.) of 600 to
Anneal at 660 ° C., for example, 640 ° C. for 1 to 4 hours, for example, 1 hour, then gradually cool at 0.1 to 0.5 ° C./min, for example, 0.2 ° C./min, and 450 to 590 ° C., for example, 55
It was taken out when the temperature dropped to 0 ° C. It is desirable that this take-out temperature be equal to or lower than the maximum temperature of the subsequent heat treatment step. By such heat treatment, irreversible shrinkage of the substrate can be suppressed even in the subsequent heat treatment.

The substrate 10 thus treated was washed, and a 2000-nm-thick silicon oxide base film 11 was formed by a sputtering method. Then, an intrinsic (I-type) amorphous silicon film 12 having a thickness of 300 to 1000 Å, for example, 500 例 え ば was formed by a plasma CVD method. Then continuously 500-2000 mm thick, for example 10
A silicon nitride film having a thickness of 00 ° was formed. Then, only the silicon nitride film was selectively etched to form mask films 13a and 13b in the oxidation step. (Fig. 1 (A))

Then, at a temperature of 600 ° C. in a nitrogen atmosphere of 1 atm.
For 48 hours to crystallize the silicon film.
Thereafter, 1 atm containing 550 to 650 containing 10% steam.
C., typically at 600 ° C. in an oxygen atmosphere.
By leaving to stand for 5 hours, a region of the silicon film not covered with the mask film was completely oxidized to the bottom surface, and silicon oxide regions 14a to 14c were formed. The control of the pressure of the steam was performed by a pyrogenic oxidation method.
As a result, the silicon film was separated into regions 15a and 15b. (FIG. 1 (B))

Thereafter, the mask films 13a and 13b are removed and TEOS (tetraethoxysilane, Si (OC)
_A silicon oxide film 16 having a thickness of 1200 ° was formed by a plasma CVD method using ₂ H ₅ ) ₄ ) and oxygen as raw materials to form a gate insulating film. Subsequently, a silicon film (containing 0.01 to 0.2% phosphorus) having a thickness of 3000 to 8000, for example, 6000, was formed by LPCVD. Then, the silicon film is patterned to form a gate electrode 17.
n, 17p and 17c were formed.

Next, the ion doping method (plasma doping)
Ping method)
(Configure source / drain, channel)
P or N conductivity type in self-alignment using poles as mask
Impurities to be imparted were added. As doping gas,
OSPHIN (PH_Three) And diborane (B_TwoH₆)
In the former case, the acceleration voltage is 60 to 90 kV, for example,
80 kV, in the latter case 40 to 80 kV, for example 65
kV. Dose amount is 1 × 10^Fifteen~ 8 × 10 ^Fifteenc
m^-2, For example, 2 × 10^Fifteencm^-2, Boron 5 × 1
0^FifteenAnd During doping, one region is
Select each element by covering with photoresist
Doped. As a result, the N-type impurity region 18
An n-type and a P-type impurity region 18p are formed, and a P-channel type
TFT (PTFT) region and N-channel TFT (NT
FT).

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser light is such that the energy density is 200 to 400 mJ / c.
m ² , for example, 250 mJ / cm ^2, and 2
Irradiation was performed for 10 to 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light. (Figure 1
(C))

Subsequently, a silicon oxide film 19 having a thickness of 6000.degree.
Was formed by a plasma CVD method as an interlayer insulator. As the interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, a contact hole is formed, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 2.
0a, 20b and 20c were formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm.
Was completed in a complementary type. (Figure 1
(D) FIG. 1E shows a state in which FIG. 1C is viewed from above. The cross-section taken along the dashed line in FIG.
(D).

[Embodiment 2] FIG. 3 shows a manufacturing process of this embodiment. First, the substrate (Corning 7059) is heated to a temperature higher than the strain point (593 ° C) at 600 to 660 ° C, for example, 64 ° C.
Anneal at 0 ° C. for 1-4 hours, for example 1 hour, then
Slowly cooling at 0.1 to 0.5 ° C / min, for example, 0.2 ° C / min,
It was taken out at a stage when the temperature was lowered to 450 to 590 ° C, for example, 550 ° C.

The substrate 31 thus treated was washed, and a silicon oxide base film 32 having a thickness of 2000 .ANG. Was formed by a sputtering method. Then, by plasma CVD, a thickness of 300 to 1000 Å, for example, 1000 Å
An intrinsic (I-type) amorphous silicon film 33 was formed. Then continuously 500-2000 mm thick, for example 10
A silicon nitride film having a thickness of 00 ° was formed. Then, only the silicon nitride film was selectively etched to form mask films 34a and 34b in the oxidation step. (FIG. 3 (A))

Then, at a temperature of 600 ° C. in a nitrogen atmosphere of 1 atm.
For 48 hours to crystallize the silicon film.
Thereafter, 10 atmospheres containing 100% by volume of steam, 500
By leaving in an atmosphere at 600 ° C., typically 550 ° C. for 3 to 5 hours, a region of the silicon film that is not covered with the mask film is completely oxidized to the bottom surface, and a silicon oxide region 35a〜 35c was formed. As a result, the silicon film was separated into regions 36a and 36b.
(FIG. 3 (B))

Thereafter, the mask films 34a and 34b are removed, and the pressure is again increased to 1 atm containing 100% water vapor, 500 to 6 mm.
In an atmosphere of 00 ° C, typically 550 ° C,
The whole surface was oxidized by being left for 5 hours. By this step, the surfaces of the silicon regions 36a and 36b were oxidized, and the oxide films 37a and 37b having a thickness of about 1000 ° were formed, and the thickness of the silicon regions was reduced to about 500 °.
After the oxidation step is completed, 600 ° C. of dinitrogen monoxide (N ₂
By leaving the substrate in the atmosphere of O), dehydration treatment was performed, and the thermal oxide films 37a and 37b were used as gate insulating films. (FIG. 3 (C)) Subsequently, the thickness of 3000 to 8 is formed by the LPCVD method.
000Å, for example, 6000Å silicon film (0.01 to
(Containing 0.2% phosphorus). Then, the silicon film is patterned to form the gate electrodes 38n, 38p, 38.
c was formed.

Next, the ion doping method (plasma doping)
Ping method)
(Configure source / drain, channel)
P or N conductivity type in self-alignment using poles as mask
Impurities to be imparted were added. As doping gas,
OSPHIN (PH_Three) And diborane (B_TwoH₆)
In the former case, the acceleration voltage is 60 to 90 kV, for example,
80 kV, in the latter case 40 to 80 kV, for example 65
kV. Dose amount is 1 × 10^Fifteen~ 8 × 10 ^Fifteenc
m^-2, For example, 2 × 10^Fifteencm^-2, Boron 5 × 1
0^FifteenAnd During doping, one region is
Select each element by covering with photoresist
Doped. As a result, the N-type impurity region 39
An n-type and a P-type impurity region 39p are formed to form a P-channel type.
TFT (PTFT) region and N-channel TFT (NT
FT).

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser light is such that the energy density is 200 to 400 mJ / c.
m ² , for example, 250 mJ / cm ^2, and 2
Irradiation was performed for 10 to 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light. (FIG. 3
(D))

Subsequently, a silicon oxide film 40 having a thickness of 6000.degree.
Was formed by a plasma CVD method as an interlayer insulator. Polyimide or a two-layer film of silicon oxide and polyimide may be used as the interlayer insulator. Further, a contact hole is formed, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form a TFT electrode and wiring 41
a, 41b and 41c were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete a semiconductor circuit having a complementary TFT. (FIG. 3
(E))

[Embodiment 3] FIG. 4 is a sectional view showing a manufacturing process of this embodiment. First, the substrate (Corning 7059) is annealed at 600 to 660 ° C. higher than the strain point (593 ° C.), for example, 640 ° C. for 1 to 4 hours, for example, 1 hour, and then 0.1 to 0.5 ° C./min. For example, it was gradually cooled at a rate of, for example, 0.2 ° C./min, and was taken out at a stage when the temperature was lowered to 450 to 590 ° C., for example, 550 ° C. Substrate 4 that has been subjected to such processing
2 was washed, and a 2000-nm-thick silicon oxide base film 43 was formed by a plasma CVD method using TEOS as a raw material. Then, a thickness of 100 to
An intrinsic (I-type) amorphous silicon film 44 of 1000 °, for example, 300 ° was formed. Next, thickness 1000
Silicon oxide film 45 and silicon nitride film 46 having a thickness of 1000
Was deposited and patterned to form a mask film.

Then, by sputtering, a thickness of 5 to 2
A nickel film 47 of 0 °, for example, 10 ° was formed. Since this nickel film is extremely thin, it does not strictly exhibit a shape as a film. The above figures of the film thickness are average.
In this case, it was preferable to heat the substrate to 150 to 300 ° C. Nickel introduced in this step has a catalytic action to promote crystallization of the amorphous silicon film.
(FIG. 4 (A))

Then, in a nitrogen atmosphere of 1 atm.
It was crystallized by thermal annealing at 00 ° C. for 4 hours. At this time, as indicated by the arrow, crystal growth progressed in the lateral direction (the direction parallel to the substrate) from the region where the nickel film was selectively formed to the region covered with the mask film. As a result, the amorphous silicon film is crystallized, and the crystalline silicon film 48
It became. (FIG. 4 (B))

Next, 10 atm containing 100% water vapor,
By leaving the substrate in an atmosphere of 500 to 600 ° C., typically 550 ° C. for one hour, the region of the silicon film that is not covered with the mask film is completely oxidized to the bottom surface, and the silicon oxide regions 49a and 49b are removed. Formed. (FIG. 4
(C))

After that, a thickness of 1
A silicon oxide film 51 having a thickness of 200 ° was formed to serve as a gate insulating film. Subsequently, a thickness of 60
A film of aluminum (containing 0.01 to 0.2% scandium) of 00 to 8000 °, for example, 6000 ° was formed. Then, the aluminum film was patterned to form a gate electrode. Further, the surface of the aluminum electrode was anodized to form an oxide layer on the surface. This anodization was performed in an ethylene glycol solution containing tartaric acid at 1 to 5%. The thickness of the resulting oxide layer is 200
It was 0 °. Note that this oxide has a thickness for forming an offset gate region in a later ion doping process, and thus the length of the offset gate region can be determined in the anodic oxidation process. Thus, the gate electrode portion (gate electrode and anodic oxide layer around it) 52
n, 52p and 52c were formed.

Next, the ion doping method (plasma doping)
Ping method) to the crystalline silicon region 50
Using the gate electrode as a mask, P or
An impurity imparting N conductivity type was added. Doping gas
Phosphine (PH _Three) And diborane (B_Two
H₆), And in the former case, the accelerating voltage is 60 to 90 k.
V, for example 80 kV, in the latter case 40-80 kV,
For example, it was set to 65 kV. Dose amount is 1 × 10^Fifteen~ 8 × 1
0^Fifteencm^-2, For example, 2 × 10^Fifteencm^-2, Boron
5 × 10^FifteenAnd For doping, one area
Each element by covering with a photoresist
Was selectively doped. As a result, N-type impurity regions
A region 53n and a P-type impurity region 53p are formed, and a P channel is formed.
Flannel type TFT (PTFT) region and N-channel type TFT
(NTFT) could be formed.

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser light is such that the energy density is 200 to 400 mJ / c.
m ² , for example, 250 mJ / cm ^2, and 2
Irradiation was performed for 10 to 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light. As described above, the impurity region and the gate electrode have a thickness y of the anodic oxide layer.
Only the offset state. (FIG. 4 (D))

Subsequently, a silicon oxide film 54 having a thickness of 6000.degree.
Was formed by a plasma CVD method as an interlayer insulator. Further, a contact hole is formed, and TF is formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
T electrodes / wirings 55a, 55b, and 55c were formed. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete a semiconductor circuit having a complementary TFT. (FIG. 4E)

[Embodiment 4] FIG. 6 is a sectional view showing a manufacturing process of this embodiment. This embodiment is a manufacturing process of a TFT type active matrix circuit used for a liquid crystal display or the like. First, the substrate (Corning 7059) was placed at the strain point (5
93 ° C.) higher than 600-660 ° C., for example 640 ° C.
For 1 to 4 hours, for example, 1 hour.
1 to 0.5 ° C./min, for example, 0.2 ° C./min.
It was taken out when the temperature was lowered to 0 to 590 ° C, for example, 550 ° C. The substrate 56 thus treated was washed, and a 2000-nm-thick silicon oxide base film 57 was formed by a plasma CVD method using TEOS as a raw material. Then, the thickness is 100 to 1000 by the plasma CVD method.
An intrinsic (I-type) amorphous silicon film 58 having a thickness of, for example, 800 is formed. Next, a silicon oxide film 59 having a thickness of 1000 と and a silicon nitride film 60 having a thickness of 1000 堆積 were deposited and patterned to form a mask film.

Then, by sputtering, a thickness of 5 to 2
A nickel film 61 of 0 °, for example, 10 ° was formed. Since this nickel film is extremely thin, it does not strictly exhibit a shape as a film. The above figures of the film thickness are average.
In this case, it was preferable to heat the substrate to 150 to 300 ° C. Nickel introduced in this step has a catalytic action to promote crystallization of the amorphous silicon film.
Thereafter, boron ions are added by 2 × 10 ^{13 to} 5 × 10 ¹⁵ cm ⁻² , for example, 5 × 10 ¹⁵ cm by an ion doping method.
^The silicon film 58 was introduced at a dose of ^{-2 using} the mask film 60 as a mask. This boron ion forms N at the silicon oxide interface.
It functions as a so-called channel stopper, which prevents a current from leaking due to the formation of a mold layer and further enhances the separation of each TFT. (FIG. 6 (A))

Then, in a nitrogen atmosphere of 1 atm.
It was crystallized by thermal annealing at 00 ° C. for 4 hours. At this time, as indicated by the arrow, crystal growth progressed in the lateral direction (the direction parallel to the substrate) from the region where the nickel film was selectively formed to the region covered with the mask film. After the crystallization step is completed, the silicon film is etched using the mask film 60 as a mask, and the thickness thereof is increased from the initial 800 ° to 400 °.
Halved to Å. (FIG. 6 (B))

Next, 10 atmospheres containing 10% steam, 5
The thin silicon film region 62 which is not covered with the mask film in the silicon film is oxidized by leaving the substrate in an atmosphere of 00 to 600 ° C., typically 550 ° C. for 3 hours, thereby forming silicon oxide regions 63a and 63b. Was formed. The control of the pressure of the steam was performed by a pyrogenic oxidation method. The oxidized portion of the silicon film is changed into a silicon oxide having a thickness about twice as large by the oxidation process. As a result, the region 64 remaining as silicon and the surrounding silicon oxide region 63 have the same high height. It became. (FIG. 6 (C))

Thereafter, a thickness of 1
A 200 ° silicon oxide film 65 was formed to form a gate insulating film. Subsequently, a thickness of 60
A film of aluminum (containing 0.01 to 0.2% scandium) of 00 to 8000 °, for example, 6000 ° was formed. Then, the aluminum film was patterned to form a gate electrode. Further, the surface of the aluminum electrode was anodized to form an oxide layer on the surface. This anodization was performed in an ethylene glycol solution containing tartaric acid at 1 to 5%. The thickness of the resulting oxide layer is 200
It was 0 °. Note that this oxide has a thickness for forming an offset gate region in a later ion doping process, and thus the length of the offset gate region can be determined in the anodic oxidation process. Thus, a gate electrode portion (gate electrode and anodic oxide layer around the gate electrode) 66 was formed. In this embodiment, since the heights of the silicon region 64 and the silicon oxide region 63 are almost the same, there is no disconnection of the gate electrode.

Next, an impurity for imparting the N conductivity type was added to the crystalline silicon region 64 in a self-aligned manner by the ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH ₃ ) is used as a doping gas, and the accelerating voltage is 60 to 90 k.
V, for example, 80 kV, and the dose amount is 1 × 10 ¹⁵ to 8 × 10
¹⁵ cm ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, N-type impurity regions 67a and 67b were formed, and an N-channel TFT (NTFT) region could be formed.

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser light is such that the energy density is 200 to 400 mJ / c.
m ² , for example, 250 mJ / cm ^2, and 2
Irradiation was performed for 10 to 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light. (FIG. 6
(D))

Subsequently, a silicon oxide film 68 having a thickness of 6000.degree.
Was formed by a plasma CVD method as an interlayer insulator. Further, an ITO film having a thickness of 800 mm is formed by sputtering.
A film was formed, and this was patterned to obtain a pixel electrode 69. Then, contact holes were formed in the interlayer insulating film, and the electrodes / wirings 70a and 70b of the TFT were formed of a metal material, for example, a multilayer film of titanium nitride and aluminum. Finally, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete a TFT type active matrix circuit. (FIG. 6E)

[0042]

According to the present invention, the yield of TFT is improved. Further, according to the present invention, there is no restriction on the underlayer, and a method of forming the underlayer suitable for mass production can be adopted. Thus, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 shows an example of a manufacturing process of a TFT of the present invention. (See Example 1)

FIG. 2 shows an example of a manufacturing process of a conventional TFT.

FIG. 3 shows an example of a manufacturing process of a TFT of the present invention. (See Example 2)

FIG. 4 shows an example of a manufacturing process of a TFT of the present invention. (See Example 3)

FIG. 5 shows a state of steam oxidation at a low temperature (600 ° C. or lower).

FIG. 6 shows an example of a manufacturing process of a TFT of the present invention. (See Example 4)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... Base film 12 ... Silicon film 13 ... Mask film with respect to an oxidation process 14 ... Silicon oxide which isolates between elements 15 ... TFT semiconductor region 16 ... Gate Insulating film 17: Gate electrode 18: Impurity region 19: Interlayer insulator 20: Source and drain electrodes

Claims (3)

[Claims] A step of forming a non-single-crystal semiconductor film over an insulating substrate; a step of crystallizing the non-single-crystal semiconductor film; A method of manufacturing a semiconductor device, comprising the steps of: 2. The method for manufacturing a semiconductor device according to claim 1, wherein the crystallization is performed after nickel is selectively introduced into the non-single-crystal semiconductor film. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the oxidation is performed to a bottom surface of the crystallized non-single-crystal semiconductor film.