JPH11289248A - Input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of an input circuit in a high power supply voltage CMOS integrated circuit for receiving a signal from a lower power supply voltage CMOS integrated circuit. SOLUTION: An input signal is directly applied to the gate terminal of an N-channel MOS transistor(TR) MN 6 in a CMOS inverter constituting an input circuit and a signal passed through a level shift circuit for shifting the level of the input signal to a high voltage power supply side is applied to the gate terminal of a P-channel MOS TR MP 5, so that the MOS TR MP 5 is turned off when an input signal is in a high level and the TRs constituting the CMOS inverter are not simultaneously turned on.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input circuit,
In particular, the present invention relates to an input circuit of a high power supply voltage CMOS integrated circuit that receives a signal from a low power supply voltage CMOS integrated circuit.

[0002]

2. Description of the Related Art Power consumption increases due to high integration and high-speed operation of integrated circuits. To reduce this, lower power supply voltages of integrated circuits are being promoted. May be used within. In this case, in the conventional integrated circuit, when an output on the low power supply voltage side is received by an input on the high power supply voltage side, a current of several hundred μA or more is constantly supplied to the input circuit on the high power supply voltage side while the input signal is at a high level. There is a problem that causes an increase in power consumption.

FIG. 5 shows a first conventional example using a general inverter circuit. In FIG. 5, an output circuit of a low power supply voltage side is composed of a P-channel MOS transistor (hereinafter, referred to as a PMOS transistor) MP1 and an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor) MN1. It is connected to the input IN on the power supply voltage side. The input circuit on the high power supply voltage side includes a PMOS transistor MP2 and an NMOS transistor MN2.

When the signal at the input terminal IN from the low power supply voltage side is at low level, the PMOS transistor MP2 is turned on and the NMOS transistor MN2 is turned off. The current flowing from the terminal VDH to the ground terminal GND is very small and poses no problem.

However, when the signal at the input terminal IN is at a high level, if the threshold voltage of the PMOS transistor MP2 is smaller than the difference between the high power supply voltage VDH and the low power supply voltage VDL, the PMOS transistor MP2 is turned on and the NMOS transistor MP2 is turned on.
The transistor MN2 is also turned on, and the power supply terminal VDH
A current of several hundred μA or more flows from the ground terminal GND to
Power consumption increases.

FIG. 6 shows a second conventional example of an input circuit having a level conversion function by feedback in order to improve the first conventional example. In FIG. 6, an input terminal A of an initial stage inverter circuit composed of a PMOS transistor MP2 and an NMOS transistor MN2 and an input terminal I of the input circuit are shown.
During N, the NMOS transistor MNA having a drain connected to the input terminal IN, a source connected to the input terminal A of the first-stage inverter circuit, a gate connected to the high power supply voltage terminal VDH, and a drain connected to the input of the first-stage inverter circuit A PMOS transistor MPA whose source is connected to the high power supply voltage terminal VDH, whose gate is connected to the output terminal B of the first-stage inverter circuit is inserted, and the PMOS transistor M is connected to the output terminal B of the first-stage inverter circuit.
The input of the second-stage inverter circuit composed of P3 and NMOS transistor MN3 is connected.

In this input circuit, when the signal at the input terminal IN is at a low level, the input A of the first-stage inverter circuit goes low through the MNA in the ON state, so that the output terminal B of the first-stage inverter circuit goes high, and the PMOS
The transistor MPA is turned off, and the signal of the output terminal OUT of the second-stage inverter circuit is set to a low level.

On the other hand, when the signal at the input terminal IN is at the high level, the input A of the first-stage inverter circuit goes to the high level (the potential is lower than the low power supply voltage) through the on-state NMOS transistor MNA. The terminal B becomes low level and the PMOS transistor MPA
Is turned on, the potential of the input terminal A of the first-stage inverter circuit is raised to the high power supply voltage VDH.

As a result, the PMOS of the first stage inverter circuit is
Since the transistor MP2 is turned off, the current flowing from the power supply terminal VDH to the ground terminal GND, which is a problem in the first conventional example, becomes very small.

However, in the conventional example 2, the high power supply voltage VDH
Potential difference between the low power supply voltage VDL and the NMOS transistor M
When the voltage is larger than the threshold voltage of NA, the current I as indicated by an arrow in FIG.
The power flows into the low power supply voltage terminal through the path from the S transistor MNA to the PMOS transistor MP1, and the power consumption increases, and the low power supply voltage VDL fluctuates.

In order to improve the second conventional example, the gate potential of the NMOS transistor MNA of the second conventional example is controlled to increase the threshold voltage of the NMOS transistor MNA when the input terminal IN is at a high level. 18378
7 shows the input circuit disclosed in FIG.

In FIG. 7, a PMOS transistor MP
2, a drain is connected to the input terminal IN, a source is connected to the input terminal A of the first-stage inverter circuit, and a gate is provided between the input terminal A of the first-stage inverter circuit constituted by the NMOS transistor MN2 and the input terminal IN of the input circuit. Is an NMOS transistor MNA connected to the output terminal C of the feedback inverter circuit, the drain is connected to the input terminal A of the first-stage inverter circuit, and the source is the high power supply voltage terminal VDH.
Connected to the output terminal B of the first-stage inverter circuit.
Is inserted, the PMOS transistor MPA connected to
The output terminal B of the first-stage inverter circuit is connected to the input of the second-stage inverter circuit composed of the PMOS transistor MP3 and the NMOS transistor MN3, and the output terminal OUT of the second-stage inverter circuit is connected to the input terminal of the feedback inverter circuit. Have been. The feedback inverter circuit is P
MOS transistor MP4 and NMOS transistor MN
4 and resistors R1 and R2 for controlling the output potential.

In this input circuit, when the signal at the input terminal IN is at a low level, the input A of the first-stage inverter circuit is at a low level, so that the output terminal B of the first-stage inverter circuit is at a high level, and the PMOS transistor MPA is turned off. The signal at the output terminal OUT of the second-stage inverter circuit is set to low level, and the input of the feedback inverter circuit is at low level, so that the PMOS transistor MP4 is turned on and outputs high level, and the gate of the NMOS transistor MNA is set to high level. Become.

Next, when the signal at the input terminal IN goes high, the input A of the first-stage inverter circuit goes high (the potential is lower than the low power supply voltage) through the ON-state NMOS transistor MNA. The terminal B becomes low level, and the PMOS transistor MP
In order to turn A on, the potential of the input terminal A of the first-stage inverter circuit is raised to the high power supply voltage VDH.

As a result, the PMOS of the first-stage inverter circuit
Since the transistor MP2 is turned off, the current flowing from the power supply terminal VDH to the ground terminal GND, which is a problem of the first conventional example, becomes very small. Further, since the input of the feedback inverter circuit is at a high level, the PMOS transistor MP4 is turned off and the NMOS transistor MN4 is turned on, so that the high power supply voltage VDH is applied to the output terminal C.
Is divided by R1 and R2 (R2 × VDH / (R1 +
R2)) is output. Therefore, the NMOS transistor MNA to which the output C of the feedback inverter is connected
NMOS transistor MNA because the gate potential of
Has a higher threshold voltage. As a result, there is no current flowing into the low power supply voltage terminal through the path of the PMOS transistor MPA → NMOS transistor MNA → PMOS transistor MP1, which is a problem of the second conventional example.

However, the third conventional example requires a feedback inverter circuit, and if the resistances of the resistors R1 and R2 are not made sufficiently large, there is a problem that the power consumption in the feedback inverter circuit becomes large. For example, when the power supply voltage VDH is 5 V
When the output terminal C is set to 2.5 V and the current is to be suppressed to 1 nA, the resistance of R1 and R2 must be set to a high resistance of 2.5 GΩ. is there.

[0017]

SUMMARY OF THE INVENTION Low power supply voltage CMOS
In the case where a signal is input from the integrated circuit to a CMOS integrated circuit having a high power supply voltage, the first conventional example has a drawback that the PMOS transistor MP2 is not turned off, so that a current constantly flows and power consumption increases.

In the second conventional example, when the potential difference between the high power supply voltage and the low power supply voltage is large, the NMOS transistor MNA does not turn off, and the output on the low power supply voltage side is supplied from the input circuit on the high power supply voltage side through the MNA. Current flows through the circuit,
Not only does the problem of increased power consumption not be solved, but power supply voltage fluctuations on the lower power supply voltage side may occur.

In the third conventional example, the gate potential of the MNA is controlled by improving the second conventional example, and current flowing from the input circuit on the high power supply voltage side to the output circuit on the low power supply voltage side through the MNA is eliminated. However, the power consumption in the control circuit for controlling the gate potential of the MNA is large, and the problem cannot be solved. Further, since high resistance on the order of giga is required to suppress power consumption, there is a problem that the element area increases.

An object of the present invention is to reduce the power consumption of an input circuit of a high power supply voltage CMOS integrated circuit that receives a signal from a low power supply voltage CMOS integrated circuit.

[0021]

SUMMARY OF THE INVENTION The present invention comprises an inverter circuit and a level shift circuit for level shifting an input signal. The input circuit of a high power supply voltage CMOS integrated circuit receives a signal from a low power supply voltage CMOS integrated circuit. Wherein the inverter circuit includes an N-channel MOS transistor provided between a power supply terminal and a ground terminal.
And a P-channel MOS transistor of
The source electrode of the N-channel MOS transistor is connected to the ground terminal, the gate electrode is connected to the input terminal and the input terminal of the level shift circuit, and the first P-channel MOS transistor
The source electrode of the OS transistor is connected to the power terminal,
A gate electrode is connected to the output terminal of the level shift circuit, and N
A connection point between the drain electrode of the channel type MOS transistor and the drain electrode of the first P-channel type MOS transistor is used as an output terminal of the input circuit, and the level shift circuit comprises a second P-channel type MOS transistor and a third P-type MOS transistor.
Channel type MOS transistor, first capacitive element and second
Of the second P-channel type MOS
A gate electrode of the transistor serves as an input terminal of the level shift circuit, a source electrode of the third P-channel MOS transistor serves as an output terminal of the level shift circuit, and a second P-channel MOS transistor and a third P-channel MOS transistor Is connected to the power supply terminal,
The drain electrode of the second P-channel MOS transistor is connected to the ground terminal, the source electrode of the second P-channel MOS transistor is connected to the gate electrode and the drain electrode of the third P-channel MOS transistor,
Is connected between the input terminal of the level shift circuit and the source electrode of the second P-channel MOS transistor, and the second capacitive element is connected to the input terminal of the level shift circuit and the third terminal.
And a source electrode of the P-channel MOS transistor.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the input circuit of the present invention. The input circuit shown in FIG. 1 includes an inverter circuit and a level shift circuit. The inverter circuit includes a PMOS transistor MP5 and an NMOS transistor MN6.
The source terminal of the S transistor MP5 is a high voltage power supply VDH.
, The gate terminal is connected to the output terminal B of the level shift circuit, and the drain terminal is connected to the output terminal OUT. The source terminal of the NMOS transistor MN6 is connected to the ground terminal GND, and the gate terminal is connected to the input terminal IN.
, And the drain terminal is connected to the output terminal OUT.

The level shift circuit comprises input terminals IN and PM
It is connected between the gate terminals of the OS transistor MP5, and is composed of PMOS transistors MP1 and MP2 and capacitive elements C1 and C2. The gate terminal of the PMOS transistor MP1 is connected to the input terminal IN, the drain terminal is connected to the ground terminal GND, and the source terminal is connected to the gate terminal and the drain terminal of the PMOS transistor MP2. The gate terminal and the drain terminal of the PMOS transistor MP2 are connected to the PMOS transistor MP1.
, And the source terminal is connected to the gate terminal of the PMOS transistor MP5 as the output of the level shift circuit. The capacitance element C1 is connected to the input terminal IN
And the source terminal of the PMOS transistor MP1, and the capacitor C2 is connected between the input terminal IN and the source terminal of the PMOS transistor MP2.

The operation of this embodiment will now be described with reference to FIG.
This will be described in detail with reference to the timing chart shown in FIG. From the circuit of the low voltage power supply, a signal VI whose high level is the low voltage power supply potential and whose low level is the ground potential is supplied to the input terminal IN.
N is input.

The input signal is supplied to an NMO
Input to the gate terminal of S transistor MN6, NMO
The S transistor MN6 is turned on when it is at a high level and turned off when it is at a low level.

On the other hand, a signal obtained by level-shifting the input signal to the higher power supply voltage side is input to the gate terminal of the PMOS transistor MP5 constituting the inverter, and the high level of the level-shifted signal is applied to the PMOS transistor MP5.
Are turned off when the threshold voltage is equal to or lower than the threshold voltage VT, and turned on when the level-shifted signal is at a low level.

Since the back gate potential of the PMOS transistor MP1 of the level shift circuit is the high voltage power supply potential, the PMOS transistor MP1 is in the ON state regardless of the input signal from the low voltage power supply circuit. When the input signal changes, the change in the input voltage is transmitted to the source potential of the PMOS transistor MP1 without delay by the capacitor C1, and the source potential is stabilized at a potential level-shifted toward the high-voltage power supply by the threshold voltage VT1.

Similarly, since the back gate potential of the PMOS transistor MP2 is the high voltage power supply potential,
The transistor MP2 is on regardless of the input signal. When the input signal changes, the change in the input voltage is transmitted to the source potential of the PMOS transistor MP2 without delay by the capacitor C2, and the source potential is changed to the threshold voltage VT2.
It is stabilized at the potential level shifted to the high voltage power supply side only.

As described above, the PMOS transistor MP
5, a potential of VIN + VT1 + VT2 is applied to the gate terminal, and when the input is at a high level, the threshold voltage VT of the PMOS transistor MP5 is higher than VDH− (VIN + VT).
Since the value of (1 + VT2) can be reduced, the PMOS transistor MP5 is turned off.

Therefore, the NMOS constituting the inverter
The transistor MN6 and the PMOS transistor MP5 are not simultaneously turned on.

In the above-described embodiment, the level shift circuit is composed of the PMOS transistor MP1, the capacitor C1, and the PMOS transistor MP1.
Although the transistor MP2 and the capacitor C2 have a two-stage configuration, the threshold voltage of the PMOS transistor of the level shift circuit and the level shift amount of the input signal necessary to turn off the PMOS transistor MP5 when the input is at the high level are determined. It may have a single-stage configuration or a configuration having three or more stages.

In the above embodiment, the same operation is performed even when the drain terminal of the PMOS transistor MP2 connected to the source terminal of the PMOS transistor MP1 is connected to the ground terminal GND.

As another embodiment of the present invention, an example in which a level shift circuit is modified will be described. The basic configuration and operation are the same as in the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the input circuit of the present invention. The embodiment shown in FIG. 3 differs from the first embodiment shown in FIG. 1 in that point B, which is a floating terminal without a fixed potential, is connected to a high-voltage power supply with high impedance.

In this embodiment, even if the input signal changes little and the input signal is DC, the current path is formed by connecting the floating point B to the high-voltage power supply with high impedance, and the potential at the point B is increased. Is trying to be stable.

FIG. 4 is a circuit diagram showing a third embodiment of the input circuit of the present invention. The embodiment shown in FIG. 4 is different from the first embodiment shown in FIG.
The capacitor C2 connected between N and the source of the PMOS transistor MP2 is connected between the source of the PMOS transistor MP1 and the source of the PMOS transistor MP2. The circuit operation is the same as in the first embodiment shown in FIG.

It should be noted that the present invention is not limited to the above embodiments, and it is apparent that the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[0039]

As described above, according to the input circuit of the present invention, when the output on the low power supply voltage side is received by the input on the high power supply voltage side, the PMOS is turned on regardless of the input signal.
Based on a basic configuration having a level shift circuit for applying a signal obtained by level-shifting an input signal to a high power supply voltage side to a gate terminal of a transistor, a PMOS is used when an input is at a high level.
The transistor can be turned off, so that an input circuit with low power consumption can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of an input circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment;

FIG. 3 is a circuit diagram showing a second embodiment of the input circuit of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the input circuit of the present invention.

FIG. 5 is a circuit diagram showing a first conventional example of an input circuit.

FIG. 6 is a circuit diagram showing a second conventional example of an input circuit.

FIG. 7 is a circuit diagram showing a third conventional example of an input circuit.

[Explanation of symbols]

VDH power supply terminal GND ground terminal IN input terminal OUT output terminal MN6 N-channel type MOS transistor MP1, MP2, MP5, MPH P-channel type MOS transistor
Transistor C1, C2 Capacitance element

Claims (6)

[Claims] An inverter circuit and a level shift circuit for level shifting an input signal are provided.
High power supply voltage CMO for receiving signals from MOS integrated circuits
In the input circuit of the S integrated circuit, the inverter circuit includes an N-channel MOS transistor and a first P-channel MOS transistor provided between a power supply terminal and a ground terminal. A source electrode is connected to a ground terminal, a gate electrode is connected to an input terminal and an input terminal of the level shift circuit, a source electrode of the first P-channel MOS transistor is connected to a power supply terminal, and a gate electrode is connected to the level shift circuit. And a connection point between the drain electrode of the N-channel type MOS transistor and the drain electrode of the first P-channel type MOS transistor as an output terminal of the input circuit. The level shift circuit includes a second P-channel type MOS transistor. And a second P-channel MOS The gate electrode of the transistor is used as the input terminal of the level shift circuit, the source electrode is used as the output terminal of the level shift circuit, the back gate electrode is connected to the power supply terminal, the drain electrode is connected to the ground terminal, and the capacitor is connected to the level shift circuit. An input circuit, which is connected between an input terminal and an output terminal. 2. The level shift circuit according to claim 1, wherein said level shift circuit comprises a second P-channel MOS transistor, a third P-channel MOS transistor, a first capacitor, and a second capacitor. The gate electrode of the MOS transistor is used as the input terminal of the level shift circuit, the source electrode of the third P-channel MOS transistor is used as the output terminal of the level shift circuit, and the second P-channel MOS transistor and the third P-channel MOS transistor are used. The back gate electrode of the transistor is connected to the power supply terminal, the drain electrode of the second P-channel MOS transistor is connected to the ground terminal, and the source electrode of the second P-channel MOS transistor is connected to the third P-channel MOS transistor Is connected to the gate electrode and the drain electrode of the level shift circuit. When connected between the source electrode of the second P-channel type MOS transistor, the input terminal and the third P-channel type of the second capacitor element level shift circuit MO
2. The input circuit according to claim 1, wherein the input circuit is connected between a source electrode of the S transistor and the source electrode. 3. The input circuit according to claim 2, wherein said second capacitance element is connected between a gate electrode and a source electrode of a third P-channel MOS transistor. 4. The level shift circuit includes three or more P-channel MOS transistors and the same number of capacitive elements as the P-channel MOS transistors. The gate electrode of the first-stage P-channel MOS transistor is connected to the level shift circuit. An input terminal, a source electrode of the last-stage P-channel MOS transistor is used as an output terminal of the level shift circuit, and a back gate electrode of the first-stage to the last-stage P-channel MOS transistor is connected to a power supply terminal. The drain electrode of the MOS transistor is connected to the ground terminal, and the source electrode of the P-channel MOS transistor between the first stage and the first to last stages is connected to the gate electrode and the drain electrode of the next-stage P-channel MOS transistor. The capacitive element is connected to the input end of the level shift circuit and Input circuit according to claim 1, characterized in that it is connected between the source electrode of the channel type MOS transistor. 5. The input circuit according to claim 4, wherein each of said capacitance elements is connected between a gate electrode and a source electrode of a P-channel MOS transistor in a first stage to a last stage. 6. The input circuit according to claim 1, wherein a high impedance element is connected between an output terminal of said level shift circuit and a power supply terminal.