JPH11289063A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH11289063A
JPH11289063A JP10091262A JP9126298A JPH11289063A JP H11289063 A JPH11289063 A JP H11289063A JP 10091262 A JP10091262 A JP 10091262A JP 9126298 A JP9126298 A JP 9126298A JP H11289063 A JPH11289063 A JP H11289063A
Authority
JP
Japan
Prior art keywords
insulating film
conductive film
film
semiconductor device
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10091262A
Other languages
Japanese (ja)
Inventor
Toshiya Nitta
敏也 新田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP10091262A priority Critical patent/JPH11289063A/en
Publication of JPH11289063A publication Critical patent/JPH11289063A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for improving reliability or yield by preventing the generation of a particle cansing a problem on a micro-processing and for increasing a capacitor capacity in a low temperature process. SOLUTION: In this method for manufacturing a semiconductor device, an insulating film 11 is accumulated by the oxidation of an organic compound containing silicon on a substrate, an opening 12 is formed in the insulating film 11, the surface of the insulating film is turned into a rough face 13 by operating a chemical processing, a conductive film 14 is formed on the whole face, the conducive film other than the conductive film formed inside the opening is removed, the conductive film 14 is buried into the opening, and the insulating film 11 is removed. Also, an organic compound containing silicon is obtained as an organic silane, oxidation is attained as oxidation by atmosphere containing ozone, and the chemical processing is attained as exposure to atmosphere containing hydrogen fluoride as main components. Also, the removal of the conductive film other than the conductive film formed inside the opening is operated by mechanical/chemical grinding or etch-back.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、半導体メモリ電
荷蓄積用キャパシタの蓄積容量向上等のために、電極表
面を粗面化した半導体装置の製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having a rough electrode surface for improving the storage capacity of a capacitor for storing charge in a semiconductor memory.

【0002】[0002]

【従来の技術】情報機器分野おいて広く用いられるDR
AM(記憶保持動作が必要な随時書き込み読み出しメモ
リ)は、キャシパターによる電荷保持によって情報を記
憶する。DRAMにおいてデータの読み出しは、キャパ
シタに蓄積された電荷をトランジスタのスイッチを介し
てビット線と接続され、電荷の流出によるビット線の電
位の変化を差動アンプによって増幅してデータとして読
み出す。
2. Description of the Related Art DR widely used in the field of information equipment
An AM (randomly read / write memory that requires a storage holding operation) stores information by holding charges by a capacitor. In reading data in a DRAM, the charge stored in a capacitor is connected to a bit line through a switch of a transistor, and a change in the potential of the bit line due to the outflow of charge is amplified by a differential amplifier and read as data.

【0003】しかし、キャパシタに蓄積される電荷は時
間が経過するにつれて減少していくために、DRAMで
は定期的にキャパシタの電荷を読み出して再度書き込む
リフレッシュ動作をおこなっている。このことからDR
AMではデータ読み出しの信頼性向上、ソフトエラーの
防止、そして低消費電力の面から定期的に行うリフレッ
シュ動作の回数を減らすために、キャパシタ容量はでき
るだけ大きくしなければならない。しかし、微細化によ
りメモリ容量の増加と高密度な集積化に伴い、チップ内
でキャパシタの占有する領域はますます小さくなり、キ
ャパシタの電荷蓄積容量を増大させることが困難になっ
てきている。そのため、データホールドタイムの減少や
ソフトエラーの問題が顕著になってきている。この問題
を避けるため、キャパシタの占有面積を増やさず容量を
増大させる技術としてHSG構造(Hemispher
ical Grain構造)が用い始められている。H
SG構造はキャパシタの電極表面を粗面にすることで電
極表面の面積を増やし、キャパシタ容量の増大を図るも
のである。
However, since the charge stored in the capacitor decreases with time, the DRAM periodically performs a refresh operation of reading and rewriting the charge of the capacitor. DR from this
In the AM, the capacitance of the capacitor must be increased as much as possible in order to improve the reliability of data reading, prevent soft errors, and reduce the number of periodic refresh operations in view of low power consumption. However, with an increase in memory capacity and high-density integration due to miniaturization, the area occupied by a capacitor in a chip has become smaller and smaller, and it has become difficult to increase the charge storage capacity of the capacitor. For this reason, the problems of the data hold time and the soft error have become remarkable. To avoid this problem, an HSG structure (Hemisphere) is used as a technique for increasing the capacity without increasing the occupied area of the capacitor.
ical grain structure) has begun to be used. H
The SG structure is intended to increase the area of the electrode surface by roughening the electrode surface of the capacitor, thereby increasing the capacitance of the capacitor.

【0004】図3は、一般的なHSG構造をもつキャパ
シタの製造工程を示している。図3において、まず下地
絶縁膜30にコンタクト孔31を開口した後、ポリシリ
コンでキャパシタの下部電極32を形成し、下部電極3
2の上にアモルファスシリコン33を堆積する(図3
(A))。次に、この状態で600〜700℃の熱処理
を加えると、アモルファスシリコン33は固相成長によ
って多結晶化し、半球状の凹凸表面を有する下部電極3
2′となる(図3(B))。多結晶シリコンの結晶粒は
キャパシタの下部電極32′以外の領域にも形成されて
いるため、これをエッチバックによって除去する(図3
(C))。そして、容量絶縁膜33,ポリシリコン膜の
上部電極34を順次堆積して、図3(D)のようなHS
G構造を持つキャパシタが得られる。図3(D)から明
らかなように、凹凸が生じ表面積が大きくなった上部電
極34および下部電極32′を有するキャパシタを製造
でき、容量が増加した構造となっている。
FIG. 3 shows a process of manufacturing a capacitor having a general HSG structure. In FIG. 3, first, a contact hole 31 is opened in a base insulating film 30, and then a lower electrode 32 of the capacitor is formed of polysilicon.
2 is deposited on the amorphous silicon 33 (FIG. 3).
(A)). Next, when a heat treatment at 600 to 700 ° C. is applied in this state, the amorphous silicon 33 is polycrystallized by solid phase growth, and the lower electrode 3 having a hemispherical uneven surface is formed.
2 '(FIG. 3 (B)). Since the crystal grains of polycrystalline silicon are also formed in a region other than the lower electrode 32 'of the capacitor, they are removed by etch-back (FIG. 3).
(C)). Then, a capacitor insulating film 33 and an upper electrode 34 of a polysilicon film are sequentially deposited to form an HS electrode as shown in FIG.
A capacitor having a G structure is obtained. As is clear from FIG. 3D, a capacitor having the upper electrode 34 and the lower electrode 32 'having a large surface area with unevenness and having a large surface area can be manufactured, and the structure has an increased capacity.

【0005】[0005]

【発明が解決しようとする課題】しかしながらこの製造
方法では、形成された粗面の凹凸は粒状のポリシリコン
であるため、プロセス工程の途中で剥がれやすく、パー
ティクルの原因になって製品の信頼性や歩留を低下させ
るという問題がある。また、エッチバック条件が適当で
ないと、必要のない部分にポリシリコンが残存しショー
トの原因となることもある。さらに、アモルファスシリ
コン33の固相成長時に600〜700℃程度の高温熱
処理が必要であるが、寸法が微細化されていくと、この
熱処理による拡散層の横方向への広がりによって電気的
特性に与える影響が無視できなくなる。すなわち、ショ
ートチャネル効果や接合抵抗増加の防止に必要なシャロ
ージャンクションの形成に支障をきたす。そのため、微
細化には上記のような高温プロセスを避けることが不可
欠となってくる。
However, in this manufacturing method, the unevenness of the formed rough surface is granular polysilicon, so that it is easily peeled off in the course of the process step, which causes particles to cause the reliability and the reliability of the product. There is a problem of lowering the yield. In addition, if the etch-back conditions are not appropriate, polysilicon may remain in unnecessary parts and cause a short circuit. Further, a high-temperature heat treatment of about 600 to 700 ° C. is required during the solid phase growth of the amorphous silicon 33. However, as the dimensions are miniaturized, the diffusion of the diffusion layer in the lateral direction due to this heat treatment affects the electrical characteristics. The effects cannot be ignored. That is, formation of a shallow junction necessary for preventing a short channel effect and an increase in junction resistance is hindered. Therefore, it is indispensable for miniaturization to avoid the high temperature process as described above.

【0006】この発明は上記従来の問題を解決するもの
であり、微細化プロセスに問題となるパーティクルの発
生を防止できて信頼性や歩留が高く、かつ低温プロセス
でキャパシタ容量を増加させることのできる半導体装置
の製造方法を提供することを目的とする。
The present invention solves the above-mentioned conventional problems, and can prevent the generation of particles which are a problem in the miniaturization process, thereby increasing the reliability and yield, and increasing the capacitance of the capacitor in a low-temperature process. It is an object of the present invention to provide a method of manufacturing a semiconductor device which can be performed.

【0007】[0007]

【課題を解決するための手段】請求項1記載の半導体装
置の製造方法は、基板上にシリコンを含む有機化合物の
酸化により絶縁膜を堆積し、絶縁膜に開口を設け、絶縁
膜表面に化学的処理を施し粗面にし、全面に導電膜を形
成し、開口内部に形成された導電膜以外の部分の導電膜
を除去して開口に導電膜を埋め込み、絶縁膜を除去する
ものである。
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: depositing an insulating film on a substrate by oxidizing an organic compound containing silicon; forming an opening in the insulating film; A conductive film is formed over the entire surface, a conductive film is formed over the entire surface, a portion of the conductive film other than the conductive film formed inside the opening is removed, the conductive film is buried in the opening, and the insulating film is removed.

【0008】なお、シリコンを含む有機化合物は有機シ
ラン、酸化はオゾンを含む雰囲気による酸化、化学的処
理はフッ化水素を主成分とする雰囲気に暴露することで
ある。また、開口内部に形成された導電膜以外の部分の
導電膜の除去は、機械的化学研磨またはエッチバックに
よってなされる。請求項1記載の半導体装置の製造方法
によると、シリコンを含む有機化合物の酸化により堆積
させた絶縁膜の表面を、フッ化水素を主成分とする雰囲
気に暴露することで、当該表面を凹凸のある粗面にする
ことができる。この粗面に導電膜を形成すれば、凹凸が
転写された導電膜となる。このようにして形成された導
電膜上の凹凸は、アモルファスシリコンの固相成長によ
って形成された粒状のポリシリコンとは異なり、剥がれ
落ちによるパーティクルが発生しない。また、エッチバ
ックによる結晶粒の除去工程がないので、粒状ポリシリ
コンが残存せず、信頼性や歩留りが高くなる。さらに、
固相反応を行わないために低温プロセスでキャパシタ容
量を増加させることができる。
The organic compound containing silicon is organic silane, the oxidation is oxidation in an atmosphere containing ozone, and the chemical treatment is exposure to an atmosphere containing hydrogen fluoride as a main component. In addition, removal of the conductive film other than the conductive film formed inside the opening is performed by mechanical chemical polishing or etch back. According to the method of manufacturing a semiconductor device according to claim 1, the surface of the insulating film deposited by oxidizing an organic compound containing silicon is exposed to an atmosphere containing hydrogen fluoride as a main component, so that the surface has irregularities. It can be a rough surface. If a conductive film is formed on this rough surface, the conductive film will have the transferred irregularities. The irregularities on the conductive film thus formed do not generate particles due to peeling off, unlike the granular polysilicon formed by the solid phase growth of amorphous silicon. In addition, since there is no step of removing crystal grains by etch back, no granular polysilicon remains, and reliability and yield are increased. further,
Since the solid phase reaction is not performed, the capacity of the capacitor can be increased by a low temperature process.

【0009】請求項2記載の半導体装置の製造方法は、
基板上に導電膜を形成し、導電膜を選択的に除去し、導
電膜の表面にシリコンを含む有機化合物の酸化により絶
縁膜を堆積し、絶縁膜表面に化学的処理を施し粗面に
し、絶縁膜および導電膜の表面部分を同時にエッチング
して導電膜に粗面の形状を転写しかつ絶縁膜を除去する
ものである。
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
A conductive film is formed on a substrate, the conductive film is selectively removed, an insulating film is deposited on the surface of the conductive film by oxidation of an organic compound containing silicon, and a chemical treatment is performed on the insulating film surface to roughen the surface. The surface portion of the insulating film and the conductive film are simultaneously etched to transfer a rough surface shape to the conductive film and to remove the insulating film.

【0010】なお、シリコンを含む有機化合物は有機シ
ラン、酸化はオゾンを含む雰囲気による酸化、化学的処
理はフッ化水素を主成分とする雰囲気に暴露することで
ある。また、絶縁膜および導電膜の表面部分のエッチン
グは、等方性エッチングで行われる。請求項2記載の半
導体装置の製造方法によると、導電膜の表面にシリコン
を含む有機化合物の酸化により堆積させた絶縁膜の表面
を、フッ化水素を主成分とする雰囲気に暴露すること
で、当該表面を凹凸のある粗面にすることができる。こ
の絶縁膜および導電膜の表面部分を同時にエッチングす
ることで、導電膜に粗面の形状が転写される。このよう
にして形成された導電膜上の凹凸は、アモルファスシリ
コンの固相成長によって形成された粒状のポリシリコン
とは異なり、剥がれ落ちによるパーティクルが発生しな
い。また、エッチバックによる結晶粒の除去工程がない
ので、粒状ポリシリコンが残存せず、信頼性や歩留りが
高くなる。さらに、固相反応を行わないために低温プロ
セスでキャパシタ容量を増加させることができる。
The organic compound containing silicon is organic silane, the oxidation is oxidation in an atmosphere containing ozone, and the chemical treatment is exposure to an atmosphere containing hydrogen fluoride as a main component. The etching of the surface portions of the insulating film and the conductive film is performed by isotropic etching. According to the method of manufacturing a semiconductor device according to claim 2, by exposing the surface of the insulating film deposited by oxidizing an organic compound containing silicon on the surface of the conductive film to an atmosphere containing hydrogen fluoride as a main component, The surface can be roughened with irregularities. By etching the surface portions of the insulating film and the conductive film at the same time, the rough surface shape is transferred to the conductive film. The irregularities on the conductive film thus formed do not generate particles due to peeling off, unlike the granular polysilicon formed by the solid phase growth of amorphous silicon. In addition, since there is no step of removing crystal grains by etch back, no granular polysilicon remains, and reliability and yield are increased. Further, since no solid-phase reaction is performed, the capacitance of the capacitor can be increased by a low-temperature process.

【0011】[0011]

【発明の実施の形態】第1の実施の形態 図1は、この発明の第1の実施の形態における半導体装
置の製造方法を説明するためのキャパシタ部分の製造工
程断面図である。図1(A)において、10は半導体基
板上に形成した下地絶縁膜であり、11はキャパシタの
下部電極の形状を作るための絶縁膜であり、下地絶縁膜
10ならびに絶縁膜11にコンタクト孔(開口)12を
形成する。次工程(図1(B))において、絶縁膜11
の表面が粗面化されるように、絶縁膜11は、65℃で
窒素によるバブリングにより気化させたテトラエトキシ
シラン(Si (OC2 54 )を窒素流量で1.8S
LMと、20g/Nm3 のオゾンを含んだ酸素7.5S
LMと、窒素1.0SLMの混合気体を主原料として、
堆積温度410℃で熱分解反応により形成したTEOS
膜にて形成する。なお、SLMとは標準状態(1気圧,
20℃)の元でのl/minを示しており、またg/N
3 も標準状態(1気圧,20℃)の元でのg/m3
示している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a cross-sectional view showing a manufacturing process of a capacitor portion for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention. In FIG. 1A, reference numeral 10 denotes a base insulating film formed on a semiconductor substrate, reference numeral 11 denotes an insulating film for forming a shape of a lower electrode of a capacitor, and contact holes (contact holes) in the base insulating film 10 and the insulating film 11. (Opening) 12 is formed. In the next step (FIG. 1B), the insulating film 11
The insulating film 11 is made of tetraethoxysilane (Si (OC 2 H 5 ) 4 ) vaporized by bubbling with nitrogen at 65 ° C. at a nitrogen flow rate of 1.8 S so that the surface of the insulating film 11 is roughened.
LM and 7.5S oxygen containing 20g / Nm 3 ozone
LM and a mixed gas of nitrogen 1.0 SLM as a main raw material,
TEOS formed by thermal decomposition reaction at a deposition temperature of 410 ° C
It is formed by a film. The SLM is in a standard state (1 atm,
20 / ° C.) and g / N
m 3 also indicates g / m 3 under standard conditions (1 atm, 20 ° C.).

【0012】このような条件で堆積した絶縁膜(TEO
S膜)11において、実験より以下のことが判明した。
上記の絶縁膜(TEOS膜)11の形成において、オゾ
ン量を100g/Nm3 と20g/Nm3 で形成して、
気相フッ化水素でエッチングを行い表面状態を観察した
ところ、オゾン量が100g/Nm3 の場合、フラット
な表面が観察された。一方、オゾン量が20g/Nm3
の場合、0.06μm程度の凹凸が発生していた。
An insulating film (TEO) deposited under these conditions
In S film 11, the following was found from experiments.
In the formation of the insulating film (TEOS film) 11, the amount of ozone is formed at 100 g / Nm 3 and 20 g / Nm 3 ,
When etching was performed using gas-phase hydrogen fluoride and the surface state was observed, a flat surface was observed when the amount of ozone was 100 g / Nm 3 . On the other hand, the ozone amount is 20 g / Nm 3
In the case of the above, irregularities of about 0.06 μm were generated.

【0013】このような現象は、分子レベルで見ると次
のように考えられる。絶縁膜(TEOS膜)11の成長
にオゾン含有量の少ない酸素を用いると、水分が長い鎖
状のシリコンを主成分とする副生成物に囲まれた状態の
膜が形成される。このような膜は、気相フッ化水素(以
下HF蒸気と記す)に暴露すると、前記水分が膜中から
放出されてしまうことによって表面が荒れると考えられ
る。結局、この実施の形態で用いた絶縁膜(TEOS
膜)11は、HF蒸気中に暴露することで粗面な表面状
態となる性質を有するのであり、この発明はこうした新
規な現象を利用したものである。
[0013] Such a phenomenon is considered as follows when viewed at the molecular level. When oxygen having a low ozone content is used for growing the insulating film (TEOS film) 11, a film is formed in which the moisture is surrounded by by-products mainly composed of long chain silicon. When such a film is exposed to gas-phase hydrogen fluoride (hereinafter referred to as HF vapor), it is considered that the surface is roughened due to the release of the water from the film. After all, the insulating film (TEOS) used in this embodiment is used.
The film (film) 11 has the property of becoming a rough surface state when exposed to HF vapor, and the present invention utilizes such a novel phenomenon.

【0014】図1(B)は、絶縁膜(TEOS膜)11
の表面を粗面にするために70〜80℃のHF蒸気に暴
露する工程であり、絶縁膜(TEOS膜)11の表面を
粗面13にする。図1(C)は、全面にキャパシタの下
部電極(導電膜)14となるポリシリコンを堆積する工
程である。この下部電極14は粗面13である絶縁膜
(TEOS膜)11上に形成されているために、下部境
界は凹凸状になっている。図1(D)は、図1(C)で
堆積したポリシリコンの下部電極14のうち、コンタク
ト孔12の内部に形成された下部電極14以外の部分を
除去してコンタクト孔12に下部電極14を凹状に埋め
込むために、堆積したポリシリコンをプラズマエッチン
グによってエッチバックする工程である。これは機械的
化学研磨によっても可能である。図1(E)は、下部電
極14の凹凸面を露出するために絶縁膜(TEOS膜)
11を除去する工程である。絶縁膜(TEOS膜)11
はフッ化水素溶液によって除去される。絶縁膜(TEO
S膜)11を除去した後の下部電極14の表面は凹凸状
の粗面15となって現れる。図1(F)は、表面が粗面
状の下部電極14上に容量絶縁膜16となる酸化膜ー窒
化シリコン膜ー酸化膜(ONO膜)を堆積し、さらに上
部電極17となるポリシリコンを堆積する工程である。
これらの工程を経ることで電極表面積を増やしたキャパ
シタ構造が完成する。
FIG. 1B shows an insulating film (TEOS film) 11.
Is a step of exposing the surface of the insulating film (TEOS film) 11 to a rough surface 13 in order to make the surface of the insulating film (TEOS film) 11 rough. FIG. 1C shows a step of depositing polysilicon to be a lower electrode (conductive film) 14 of the capacitor on the entire surface. Since the lower electrode 14 is formed on the insulating film (TEOS film) 11 which is the rough surface 13, the lower boundary is uneven. FIG. 1D shows a portion of the lower electrode 14 of polysilicon deposited in FIG. 1C other than the lower electrode 14 formed inside the contact hole 12 and the lower electrode 14 is formed in the contact hole 12. This is a step of etching back the deposited polysilicon by plasma etching in order to embed in a concave shape. This is also possible by mechanical chemical polishing. FIG. 1E shows an insulating film (TEOS film) for exposing the uneven surface of the lower electrode 14.
This is a step of removing 11. Insulating film (TEOS film) 11
Is removed by a hydrogen fluoride solution. Insulating film (TEO
After the removal of the (S film) 11, the surface of the lower electrode 14 appears as an uneven rough surface 15. FIG. 1F shows an oxide film, a silicon nitride film, and an oxide film (ONO film) to be a capacitor insulating film 16 deposited on a lower electrode 14 having a rough surface. This is a deposition step.
Through these steps, a capacitor structure with an increased electrode surface area is completed.

【0015】このように構成された半導体装置の製造方
法によると、絶縁膜(TEOS膜)11の表面の凹凸を
下部電極14に転写することで粗面15としたので、従
来のようなアモルファスシリコンの固相成長によって形
成された粒状のポリシリコンとは異なり、剥がれ落ちに
よるパーティクルが発生しない。また、エッチバックに
よる結晶粒の除去工程がないので、粒状ポリシリコンが
残存せず、信頼性や歩留りが高くなる。さらに、固相反
応を行わないために低温プロセスでキャパシタ容量を増
加させることができる。
According to the method of manufacturing a semiconductor device having the above-described structure, the rough surface 15 is formed by transferring the irregularities on the surface of the insulating film (TEOS film) 11 to the lower electrode 14, so that the conventional amorphous silicon Unlike granular polysilicon formed by solid phase growth, no particles are generated due to peeling off. In addition, since there is no step of removing crystal grains by etch back, no granular polysilicon remains, and reliability and yield are increased. Further, since no solid-phase reaction is performed, the capacitance of the capacitor can be increased by a low-temperature process.

【0016】また、今後さらに微細化が進むと、より微
細な領域に十分な容量を確保したキャパシタを形成する
ために、容量絶縁膜として上記ONO膜に代えて高誘電
率膜や強誘電体膜が必要となるが、それに対応して上部
電極17に代えてRu,TiN,W,Ptなどの金属膜
を電極にして容量拡大を図る必要性が生じる。従来のH
SG構造の半導体装置の製造方法は、アモルファスシリ
コンが熱による固相反応で粒状になる性質を利用した技
術であったが、この発明によれば、キャパシタ電極表面
の凹凸形状をシリコン以外の金属でも形成可能となる。
As the miniaturization further progresses in the future, a high dielectric constant film or a ferroelectric film is used instead of the ONO film as a capacitance insulating film in order to form a capacitor having a sufficient capacitance in a finer region. However, it is necessary to use a metal film of Ru, TiN, W, Pt or the like instead of the upper electrode 17 to increase the capacity. Conventional H
The method of manufacturing a semiconductor device having an SG structure is a technique utilizing the property that amorphous silicon becomes granular by a solid-phase reaction due to heat. However, according to the present invention, the unevenness of the surface of the capacitor electrode is made of metal other than silicon. It can be formed.

【0017】第2の実施の形態 図2は、この発明の第2の実施の形態における半導体装
置の製造方法を説明するためのキャパシタ部分の製造工
程断面図である。図2(A)は、キャパシタの下部電極
を形成する工程であり、コンタクト孔21が開口された
下地絶縁膜20の上に下部電極(導電膜)22となるポ
リシリコンを堆積した後、選択的エッチングによって凸
形状にする。図2(B)では、下部電極22上に第1の
実施の形態で形成したのと同条件で薄い絶縁膜(TEO
S膜)23を堆積する。図2(C)では、絶縁膜(TE
OS膜)23の表面を粗面24にするために70〜80
℃のHF蒸気に暴露する。図2(D)では、絶縁膜(T
EOS膜)23の凹凸形状を下部電極22であるポリシ
リコンに転写するために、絶縁膜(TEOS膜)23の
上よりCl2 ,HBr,He,O2 の混合ガスを用いた
ドライエッチングを施している。このエッチング条件で
は絶縁膜(TEOS膜)23と下部電極22のエッチン
グ速度の選択比が低いため、下部電極22のポリシリコ
ンには絶縁膜(TEOS膜)23の凹凸状が転写され粗
面25となる。図2(E)では、表面を粗面状にした下
部電極22上に容量絶縁膜26となるONO膜を堆積
し、さらに上部電極27となるポリシリコンを堆積す
る。これらの工程を経ることによって電極表面積を増や
したキャパシタ構造が完成する。
Second Embodiment FIG. 2 is a cross-sectional view illustrating a manufacturing process of a capacitor portion for explaining a method of manufacturing a semiconductor device according to a second embodiment of the present invention. FIG. 2A shows a step of forming a lower electrode of the capacitor. After depositing polysilicon to be a lower electrode (conductive film) 22 on a base insulating film 20 in which a contact hole 21 is opened, a step of selectively forming the lower electrode is performed. A convex shape is formed by etching. In FIG. 2B, a thin insulating film (TEO) is formed on the lower electrode 22 under the same conditions as those formed in the first embodiment.
(S film) 23 is deposited. In FIG. 2C, the insulating film (TE
70 to 80 in order to make the surface of the OS film) 23 rough
Exposure to HF vapours. In FIG. 2D, the insulating film (T
In order to transfer the concavo-convex shape of the (EOS film) 23 to polysilicon serving as the lower electrode 22, dry etching using a mixed gas of Cl 2 , HBr, He, and O 2 is performed from above the insulating film (TEOS film) 23. ing. Under this etching condition, the selectivity of the etching rate between the insulating film (TEOS film) 23 and the lower electrode 22 is low, so that the unevenness of the insulating film (TEOS film) 23 is transferred to the polysilicon of the lower electrode 22 and the rough surface 25 is formed. Become. In FIG. 2E, an ONO film serving as a capacitance insulating film 26 is deposited on the lower electrode 22 having a roughened surface, and polysilicon serving as an upper electrode 27 is further deposited. Through these steps, a capacitor structure with an increased electrode surface area is completed.

【0018】このように構成された半導体装置の製造方
法によると、導電膜の表面にシリコンを含む有機化合物
の酸化により堆積させた絶縁膜の表面を、フッ化水素を
主成分とする雰囲気に暴露することで、当該表面を凹凸
のある粗面にすることができる。この絶縁膜および導電
膜の表面部分を同時にエッチングすることで、導電膜に
粗面の形状が転写される。このようにして形成された導
電膜上の凹凸は、アモルファスシリコンの固相成長によ
って形成された粒状のポリシリコンとは異なり、剥がれ
落ちによるパーティクルが発生しない。また、エッチバ
ックによる結晶粒の除去工程がないので、粒状ポリシリ
コンが残存せず、信頼性や歩留りが高くなる。さらに、
固相反応を行わないために低温プロセスでキャパシタ容
量を増加させることができる。
According to the method of manufacturing a semiconductor device thus configured, the surface of the insulating film deposited on the surface of the conductive film by oxidation of an organic compound containing silicon is exposed to an atmosphere containing hydrogen fluoride as a main component. By doing so, the surface can be made a rough surface having irregularities. By etching the surface portions of the insulating film and the conductive film at the same time, the rough surface shape is transferred to the conductive film. The irregularities on the conductive film thus formed do not generate particles due to peeling off, unlike the granular polysilicon formed by the solid phase growth of amorphous silicon. In addition, since there is no step of removing crystal grains by etch back, no granular polysilicon remains, and reliability and yield are increased. further,
Since the solid phase reaction is not performed, the capacity of the capacitor can be increased by a low temperature process.

【0019】また、第2の実施の形態ではキャパシタ電
極にポリシリコンを用いているが、キャパシタ電極を第
1の実施の形態と同様に金属膜にした場合でも、Ru,
TiN,W,Ptなどの金属膜とTEOS膜のエッチン
グ選択比が小さい条件を用いれば適用できる。なお、第
1および第2の実施の形態において、TEOSの代わり
にTMOS[SiC4 124 ]、OMCTS[Si4
8 244 ]、TMCTS[Si44 164 ]、
SOBC[((CH3 3 SiO2 )B]、SOP
[(CH33 SiO)3 PO]、DADBS[SiC
12246 ]を用いても同様の効果が得られる。
Although polysilicon is used for the capacitor electrode in the second embodiment, even when the capacitor electrode is formed of a metal film as in the first embodiment, Ru,
The present invention can be applied by using a condition in which the etching selectivity between a metal film such as TiN, W, and Pt and a TEOS film is small. In the first and second embodiments, TMOS [SiC 4 H 12 O 4 ], OMCTS [Si 4
C 8 H 24 O 4 ], TMCTS [Si 4 C 4 H 16 O 4 ],
SOBC [((CH 3 ) 3 SiO 2 ) B], SOP
[(CH 3 ) 3 SiO) 3 PO], DADBS [SiC
12 H 24 O 6] the same effect be used is obtained.

【0020】[0020]

【発明の効果】請求項1記載の半導体装置の製造方法に
よると、シリコンを含む有機化合物の酸化により堆積さ
せた絶縁膜の表面を、フッ化水素を主成分とする雰囲気
に暴露することで、当該表面を凹凸のある粗面にするこ
とができる。この粗面に導電膜を形成すれば、凹凸が転
写された導電膜となる。このようにして形成された導電
膜上の凹凸は、アモルファスシリコンの固相成長によっ
て形成された粒状のポリシリコンとは異なり、剥がれ落
ちによるパーティクルが発生しない。また、エッチバッ
クによる結晶粒の除去工程がないので、粒状ポリシリコ
ンが残存せず、信頼性や歩留りが高くなる。さらに、固
相反応を行わないために低温プロセスでキャパシタ容量
を増加させることができる。
According to the method of manufacturing a semiconductor device according to the first aspect, the surface of the insulating film deposited by oxidizing an organic compound containing silicon is exposed to an atmosphere containing hydrogen fluoride as a main component. The surface can be roughened with irregularities. If a conductive film is formed on this rough surface, the conductive film will have the transferred irregularities. The irregularities on the conductive film thus formed do not generate particles due to peeling off, unlike the granular polysilicon formed by the solid phase growth of amorphous silicon. In addition, since there is no step of removing crystal grains by etch back, no granular polysilicon remains, and reliability and yield are increased. Further, since no solid-phase reaction is performed, the capacitance of the capacitor can be increased by a low-temperature process.

【0021】請求項2記載の半導体装置の製造方法によ
ると、導電膜の表面にシリコンを含む有機化合物の酸化
により堆積させた絶縁膜の表面を、フッ化水素を主成分
とする雰囲気に暴露することで、当該表面を凹凸のある
粗面にすることができる。この絶縁膜および導電膜の表
面部分を同時にエッチングすることで、導電膜に粗面の
形状が転写される。このようにして形成された導電膜上
の凹凸は、アモルファスシリコンの固相成長によって形
成された粒状のポリシリコンとは異なり、剥がれ落ちに
よるパーティクルが発生しない。また、エッチバックに
よる結晶粒の除去工程がないので、粒状ポリシリコンが
残存せず、信頼性や歩留りが高くなる。さらに、固相反
応を行わないために低温プロセスでキャパシタ容量を増
加させることができる。
According to the second aspect of the present invention, the surface of the insulating film deposited on the surface of the conductive film by oxidation of the organic compound containing silicon is exposed to an atmosphere containing hydrogen fluoride as a main component. Thus, the surface can be made a rough surface having irregularities. By etching the surface portions of the insulating film and the conductive film at the same time, the rough surface shape is transferred to the conductive film. The irregularities on the conductive film thus formed do not generate particles due to peeling off, unlike the granular polysilicon formed by the solid phase growth of amorphous silicon. In addition, since there is no step of removing crystal grains by etch back, no granular polysilicon remains, and reliability and yield are increased. Further, since no solid-phase reaction is performed, the capacitance of the capacitor can be increased by a low-temperature process.

【0022】さらに、今後半導体集積回路の微細化が進
行していく上でキャパシタの電極材料を金属などのシリ
コン以外に置き換える必要性が出てくる可能性は大き
い。この時、この発明の半導体装置の製造方法を用いる
ことで、電極となる材料を限定することなく電極表面を
粗面にすることが可能となる。
Furthermore, as the miniaturization of semiconductor integrated circuits progresses in the future, it is highly likely that it will be necessary to replace the electrode material of the capacitor with a material other than silicon, such as metal. At this time, by using the method for manufacturing a semiconductor device of the present invention, it is possible to roughen the electrode surface without limiting the material to be the electrode.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の第1の実施の形態における半導体装
置の製造方法の工程断面図である。
FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

【図2】この発明の第2の実施の形態における半導体装
置の製造方法の工程断面図である。
FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

【図3】従来の半導体装置の製造方法の工程断面図であ
る。
FIG. 3 is a process sectional view of a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

11 絶縁膜(TEOS膜) 12 コンタクト孔(開口) 13,15 粗面 14 下部電極(ポリシリコンの導電膜) 16 容量絶縁膜(ONO膜) 17 上部電極(ポリシリコン膜) 22 下部電極(ポリシリコン膜) 23 絶縁膜(TEOS膜) 24,25 粗面 26 容量絶縁膜(ONO膜) 27 上部電極(ポリシリコン膜) DESCRIPTION OF SYMBOLS 11 Insulating film (TEOS film) 12 Contact hole (opening) 13, 15 Rough surface 14 Lower electrode (polysilicon conductive film) 16 Capacitive insulating film (ONO film) 17 Upper electrode (polysilicon film) 22 Lower electrode (polysilicon) 23) Insulating film (TEOS film) 24, 25 Rough surface 26 Capacitive insulating film (ONO film) 27 Upper electrode (polysilicon film)

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 基板上にシリコンを含む有機化合物の酸
化により絶縁膜を堆積する工程と、前記絶縁膜に開口を
設ける工程と、前記絶縁膜表面に化学的処理を施し粗面
にする工程と、全面に導電膜を形成する工程と、前記開
口内部に形成された前記導電膜以外の部分の前記導電膜
を除去して前記開口に前記導電膜を埋め込む工程と、前
記絶縁膜を除去する工程とを含む半導体装置の製造方
法。
A step of depositing an insulating film on a substrate by oxidizing an organic compound containing silicon, a step of providing an opening in the insulating film, and a step of performing a chemical treatment on the surface of the insulating film to roughen the surface. Forming a conductive film on the entire surface, removing the conductive film in a portion other than the conductive film formed inside the opening to bury the conductive film in the opening, and removing the insulating film A method for manufacturing a semiconductor device, comprising:
【請求項2】 基板上に導電膜を形成する工程と、前記
導電膜を選択的に除去する工程と、前記導電膜の表面に
シリコンを含む有機化合物の酸化により絶縁膜を堆積す
る工程と、前記絶縁膜表面に化学的処理を施し粗面にす
る工程と、前記絶縁膜および前記導電膜の表面部分を同
時にエッチングして前記導電膜に前記粗面の形状を転写
しかつ前記絶縁膜を除去する工程とを含む半導体装置の
製造方法。
2. A step of forming a conductive film on a substrate, a step of selectively removing the conductive film, and a step of depositing an insulating film on a surface of the conductive film by oxidizing an organic compound containing silicon. A step of performing a chemical treatment on the surface of the insulating film to roughen the surface, and simultaneously etching a surface portion of the insulating film and the conductive film to transfer the shape of the rough surface to the conductive film and remove the insulating film And a method of manufacturing a semiconductor device.
【請求項3】 シリコンを含む有機化合物が有機シラ
ン、酸化がオゾンを含む雰囲気による酸化、化学的処理
がフッ化水素を主成分とする雰囲気に暴露することであ
る請求項1または請求項2記載の半導体装置の製造方
法。
3. The method according to claim 1, wherein the organic compound containing silicon is organic silane, the oxidation is oxidation in an atmosphere containing ozone, and the chemical treatment is exposure to an atmosphere containing hydrogen fluoride as a main component. Of manufacturing a semiconductor device.
【請求項4】 開口内部に形成された導電膜以外の部分
の導電膜を除去する工程が、機械的化学研磨またはエッ
チバックによってなされることを特徴とする請求項1記
載の半導体装置の製造方法。
4. The method according to claim 1, wherein the step of removing the conductive film other than the conductive film formed inside the opening is performed by mechanical chemical polishing or etch back. .
【請求項5】 絶縁膜および導電膜の表面部分のエッチ
ングが等方性エッチングで行われることを特徴とする請
求項2記載の半導体装置の製造方法。
5. The method for manufacturing a semiconductor device according to claim 2, wherein the surface portions of the insulating film and the conductive film are etched by isotropic etching.
JP10091262A 1998-04-03 1998-04-03 Manufacture of semiconductor device Pending JPH11289063A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10091262A JPH11289063A (en) 1998-04-03 1998-04-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10091262A JPH11289063A (en) 1998-04-03 1998-04-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH11289063A true JPH11289063A (en) 1999-10-19

Family

ID=14021515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10091262A Pending JPH11289063A (en) 1998-04-03 1998-04-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH11289063A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059284A (en) * 1999-12-30 2001-07-06 박종섭 A method for forming a capacitor of a semiconductor device
KR100400247B1 (en) * 2000-12-29 2003-10-01 주식회사 하이닉스반도체 Method for forming a bottom electrode of integrated memory device
KR100655788B1 (en) 2005-06-30 2006-12-08 삼성전자주식회사 Method of cleaning a semiconductor device and method of manufacturing semiconductor device using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010059284A (en) * 1999-12-30 2001-07-06 박종섭 A method for forming a capacitor of a semiconductor device
KR100400247B1 (en) * 2000-12-29 2003-10-01 주식회사 하이닉스반도체 Method for forming a bottom electrode of integrated memory device
KR100655788B1 (en) 2005-06-30 2006-12-08 삼성전자주식회사 Method of cleaning a semiconductor device and method of manufacturing semiconductor device using the same

Similar Documents

Publication Publication Date Title
US7432152B2 (en) Methods of forming HSG layers and devices
JPH10303368A (en) Manufacture of integrated circuit capacitor with improved electrode and dielectric layer property and capacitor produced thereby
JP2003338542A (en) Method for forming contact plug with reduced contact resistance
US6544835B2 (en) Method of forming a ruthenium film by CVD
US20060160337A1 (en) Method of manufacturing a hemisperical grain silicon layer and method of manufacturing a semiconductor device using the same
KR19980055746A (en) Electrode Formation Method of Semiconductor Device
JP2002124649A (en) Semiconductor integrated circuit device and the manufacturing method therefor
US6939805B2 (en) Method of etching a layer in a trench and method of fabricating a trench capacitor
JPH10229176A (en) Manufacture of capacitor electrode
JPH11289063A (en) Manufacture of semiconductor device
JPH10275901A (en) Capacitor, and memory structure an its manufacturing method
JP2001223343A (en) Lower electrode of capacitor and its manufacturing method
US6537872B1 (en) Method of fabricating a DRAM cell capacitor
JP2727434B2 (en) Method for manufacturing capacitor
US6368405B1 (en) Apparatus for growing single crystal silicon and method for forming single crystal silicon layer using the same
KR100249917B1 (en) Manufacturing method of capacitor in dram cell
KR100424715B1 (en) Method of manufacturing capacitor in semiconductor device
JP2000150826A (en) Fabrication of semiconductor integrated circuit device
JP3420098B2 (en) Method for manufacturing semiconductor device
KR100329746B1 (en) Method for forming bottom electrode of capacitor
KR100358169B1 (en) Method for forming semiconductor device having BST dielectric
KR100463245B1 (en) Capacitor Manufacturing Method of Memory Device_
JP2002016236A (en) Method of manufacturing semicondutor device
KR100541679B1 (en) method for fabricating capacitor of semiconductor device
KR100475045B1 (en) Method for manufacturing metal layer for capacitor electrode of semiconductor device