KR100358169B1 - Method for forming semiconductor device having BST dielectric - Google Patents
Method for forming semiconductor device having BST dielectric Download PDFInfo
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- KR100358169B1 KR100358169B1 KR1019990064040A KR19990064040A KR100358169B1 KR 100358169 B1 KR100358169 B1 KR 100358169B1 KR 1019990064040 A KR1019990064040 A KR 1019990064040A KR 19990064040 A KR19990064040 A KR 19990064040A KR 100358169 B1 KR100358169 B1 KR 100358169B1
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Abstract
본 발명은 BST막 증착 및 열처리 과정에서 확산 장벽금속막이 산화되는 것을 최소화하면서 BST의 결정성을 확보하여 유전율 저하를 방지할 수 있는 반도체 메모리 소자 제조 방법에 관한 것으로, BST의 증착을 저온에서 실시한 다음 퍼니스 열처리 보다 상대적으로 열적 부담이 적은 RTP를 실시하여 BST를 결정화시키는데 특징이 있다. 저온에서의 BST막 증착 및 급속열처리로 이루어지는 일련의 과정을 반복적으로 실시함으로써 캐패시터의 하부전극과 반도체 기판을 연결하는 플러그를 이루는 확산 장벽금속막의 산화를 방지하고 높은 유전특성을 확보할 수 있다. 특히 BST막을 400 ℃ 보다 낮은 저온에서 증착하고 RTP 열처리를 통하여 결정화시킴에 따라 전극과 벌크 BST 계면의 특성 향상을 통하여 누설전류 특성도 개선되고 비록 저온증착 공정이지만 소자에서 요구되는 캐패시턴스 값을 충족시킬 수 있다.The present invention relates to a method of manufacturing a semiconductor memory device that can prevent the decrease of the dielectric constant by securing the crystallinity of the BST while minimizing the oxidation of the diffusion barrier metal film during the deposition and heat treatment of the BST film, and the deposition of the BST at a low temperature It is characterized by crystallizing BST by carrying out RTP, which has a relatively less thermal burden than furnace heat treatment. By repeatedly performing a series of processes consisting of BST film deposition at a low temperature and rapid thermal treatment, oxidation of the diffusion barrier metal film forming the plug connecting the lower electrode of the capacitor and the semiconductor substrate can be prevented and high dielectric properties can be ensured. Particularly, as BST film is deposited at low temperature below 400 ℃ and crystallized by RTP heat treatment, leakage current characteristics are improved by improving the characteristics of electrode and bulk BST interface, and even though low temperature deposition process, the capacitance value required in the device can be satisfied. have.
Description
본 발명은 반도체 메모리 소자 제조 분야에 관한 것으로, 특히 캐패시터의 유전막으로서 BST((Ba,Sr)TiO3)막을 구비하는 반도체 메모리 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor memory device manufacturing, and more particularly, to a method of manufacturing a semiconductor memory device including a BST ((Ba, Sr) TiO 3 ) film as a dielectric film of a capacitor.
반도체 메모리 소자의 고집적화의 진전으로 3년에 메모리의 용량이 4배씩 증가되어 현재에는 256Mb(mega bit) 및 1Gb(giga bit) DRAM에 대한 연구에 많은 진전을 보이고 있다. 이와 같이 DRAM의 집적도가 높아질수록 전기 신호를 읽고 기록하는 역할을 하는 셀의 면적은 256 Mb DRAM의 경우 0.5 ㎛2이고, 이때 셀의 기본 구성요소 중의 하나인 캐패시터의 면적은 0.3 ㎛2이하로 작아져야 한다. 이러한 이유로 256Mb급 이상의 고집적 소자에서는 종래의 반도체 공정에서 사용되는 기술이 한계를 보이기 시작하고 있다. 즉, 64Mb DRAM에서 지금까지 사용되어 온 유전재료인 SiO2/Si3N4등을 사용하여 캐패시터를 제조할 경우 필요한 캐패시턴스를 확보하기 위해서 박막의 두께를 최대한 얇게 하더라도 캐패시터가 차지하는 면적은 셀 면적의 6배가 넘어야 한다. 캐패시터의 스토리지노드 표면적을 증가시키기 위해서 사용되는 기술은, 스택 캐패시터 구조 또는 트렌치형 캐패시터 구조 또는 반구형 폴리실리콘막을 사용하는 기술 등 여러 가지 기술이 제안된 바 있다. 캐패시터의 단면적을 증가시키기 위해 그 구조를 더 복잡하게 만드는 경우 공정 과정이 단순하지 않기 때문에 제조단가의 상승과 수율이 떨어지는 등의 문제점이 많다. 이에 따라 캐패시터를 3차원적 입체구조로 형성함으로써 캐패시터의 단면적을 증가시켜 저장캐패시턴스를 충족시키는 방법을 256Mb급 이상의 DRAM에 적용하기에는 많은 어려움이 따른다.Due to the high integration of semiconductor memory devices, memory capacity has increased by four times in three years, and now, many studies have been made on 256Mb (mega bit) and 1Gb (giga bit) DRAM. As the density of DRAM increases, the area of a cell that reads and writes an electrical signal is 0.5 μm 2 in 256 Mb DRAM, and the area of a capacitor, which is one of the basic components of the cell, is smaller than 0.3 μm 2 . You must lose. For this reason, the techniques used in the semiconductor process of the 256Mb or higher integrated devices are starting to show a limit. In other words, when manufacturing a capacitor using SiO 2 / Si 3 N 4 , which is a dielectric material used in 64 Mb DRAM, the area occupied by the capacitor is equal to the cell area even if the thickness of the thin film is as small as possible to obtain the necessary capacitance. It should be over six times. As a technique used to increase the storage node surface area of a capacitor, various techniques have been proposed, such as a technique of using a stack capacitor structure, a trench capacitor structure, or a hemispherical polysilicon film. If the structure is more complicated to increase the cross-sectional area of the capacitor, there are many problems such as an increase in manufacturing cost and a low yield since the process is not simple. Accordingly, it is difficult to apply the method of satisfying the storage capacitance by increasing the cross-sectional area of the capacitor by forming the capacitor in a three-dimensional three-dimensional structure to DRAM of 256Mb or more.
이와 같은 문제점을 해결하기 위해서, SiO2/Si3N4계 유전체를 대체할 목적으로 BST((Ba,Sr)TiO3) 등과 같은 고유전율 박막에 대한 연구가 진행되고 있다.In order to solve this problem, a study on a high dielectric constant thin film, such as BST ((Ba, Sr) TiO 3 ) for the purpose of replacing the SiO 2 / Si 3 N 4 -based dielectric.
일반적으로 BST는 높은 유전특성을 얻기 위해서 고온 증착 및 고온 열처리(anneal) 공정이 필요하다. 그러나, 확산 장벽금속막(barrier metal)으로 사용되는 TiN은 BST막 증착 및 열처리를 위한 산소분위기에서 산화되어 TiO2로의 상전이가 일어나 캐패시턴스 값이 작아지는 치명적인 문제가 발생한다. 이러한 문제를 해결하기 위하여 TiSiN, TiAlN 등과 같은 3성분계 확산 장벽금속막에 대한 연구가 진행되고 있다. 그러나, 이와 같은 3 성분계 물질도 산화라는 본질적인 문제를 피할 수 없고 단지 내산화성이 TiN 보다 50 ℃ 내지 100 ℃ 정도 향상될 뿐이다. 따라서 BST의 고유전 특성을 얻기 위해서는 내산화성이 우수한 장벽금속막의 개발도 매우 중요하지만, BST의 증착 및 열처리 공정에 따른 장벽금속막의 열적 부담도 줄이는 것이 필요하다.In general, BST requires high temperature deposition and high temperature annealing to obtain high dielectric properties. However, TiN, which is used as a diffusion barrier metal film, is oxidized in an oxygen atmosphere for BST film deposition and heat treatment to cause a phase transition to TiO 2 , thereby causing a fatal problem of decreasing capacitance value. In order to solve this problem, studies on a three-component diffusion barrier metal film such as TiSiN and TiAlN have been conducted. However, such a three-component material also cannot avoid the inherent problem of oxidation, and merely improves oxidation resistance by about 50 ° C to 100 ° C over TiN. Therefore, in order to obtain the high dielectric properties of the BST, it is very important to develop a barrier metal film having excellent oxidation resistance, but it is also necessary to reduce the thermal burden of the barrier metal film according to the deposition and heat treatment process of the BST.
한편, 고온 증착 공정에서 하부전극과 BST막 계면에 형성되는 비정질 BST에 의해 유전율이 감소되는 문제가 있으므로 이에 대한 개선도 필요한 실정이다.On the other hand, there is a problem that the dielectric constant is reduced by the amorphous BST formed at the interface between the lower electrode and the BST film in the high temperature deposition process, it is also necessary to improve the situation.
상기와 같은 문제점을 해결하기 위한 본 발명은 BST막 증착 및 열처리 과정에서 확산 장벽금속막이 산화되는 것을 최소화하면서 BST의 결정성을 확보하여 유전율 저하를 방지할 수 있는, 반도체 메모리 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention for solving the above problems to provide a semiconductor memory device manufacturing method that can prevent the decrease in the dielectric constant by securing the crystallinity of the BST while minimizing the oxidation of the diffusion barrier metal film during the BST film deposition and heat treatment process The purpose is.
도1 내지 도10은 본 발명의 실시예에 따른 반도체 메모리 소자 제조 공정 단면도.1 to 10 are cross-sectional views of a semiconductor memory device fabrication process in accordance with an embodiment of the present invention.
*도면의 주요부분에 대한 도면 부호의 설명** Description of reference numerals for the main parts of the drawings *
14: 장벽금속막 16: 제1 전도막14: barrier metal film 16: first conductive film
17: BST 유전막 18: 상부전극17: BST dielectric film 18: upper electrode
상기 목적을 달성하기 위한 본 발명은, 반도체 기판상에 형성된 층간절연막을 선택적으로 식각하여 상기 반도체 기판을 노출시키는 콘택홀을 형성하는 단계; 그 상부가 장벽금속막으로 이루어지는 플러그를 상기 콘택홀 내에 형성하는 단계; 상기 플러그와 연결되는 캐패시터의 하부전극을 형성하는 단계; 400℃ 보다 낮은 온도에서 상기 하부전극 상에 (Ba,Sr)TiO3 유전막을 증착하고 상기 (Ba,Sr)TiO3 유전막의 결정화를 위해 급속열처리 하는 단계 - 이와 같은 일련의 과정을 적어도 한번 반복실시함- ; 및 상기 (Ba,Sr)TiO3 유전막 상에 캐패시터의 상부전극을 형성하는 단계를 포함하는 반도체 메모리 소자 제조 방법을 제공한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a contact hole exposing the semiconductor substrate by selectively etching an interlayer insulating layer formed on the semiconductor substrate; Forming a plug in the contact hole, the plug having an upper portion formed of a barrier metal film; Forming a lower electrode of a capacitor connected to the plug; Depositing a (Ba, Sr) TiO 3 dielectric film on the lower electrode at a temperature lower than 400 ° C. and performing rapid heat treatment for crystallization of the (Ba, Sr) TiO 3 dielectric film-repeating this series of steps at least once ; And forming an upper electrode of the capacitor on the (Ba, Sr) TiO 3 dielectric layer.
본 발명은 BST((Ba,Sr)TiO3)막 증착 및 열처리 과정에서 확산 장벽금속막이 산화되는 것을 최소화하면서 BST의 결정성을 확보하여 유전율 저하를 방지하기 위하여, BST의 증착을 저온에서 실시한 다음 퍼니스(furnace) 열처리 보다 상대적으로 열적 부담이 적은 RTP(rapid thermal process)를 실시하여 BST를 결정화시키는데 특징이 있다. 저온에서의 BST막 증착 및 급속열처리로 이루어지는 일련의 과정을 반복적으로 실시함으로써 캐패시터의 하부전극과 반도체 기판을 연결하는 플러그를 이루는 확산 장벽금속막의 산화를 방지하고 높은 유전특성을 확보할 수 있다. 특히 BST막을 400 ℃ 보다 낮은 저온에서 증착하고 RTP 열처리를 통하여 결정화시킴에 따라 전극과 벌크(bulk) BST 계면의 특성 향상을 통하여 누설전류 특성도 개선되고 비록 저온증착 공정이지만 소자에서 요구되는 캐패시턴스(capacitance) 값을 충족시킬 수 있다.In the present invention, in order to minimize the oxidation of the diffusion barrier metal film during the deposition and heat treatment of the BST ((Ba, Sr) TiO 3 ) film and to secure the crystallinity of the BST to prevent the decrease of the dielectric constant, the BST is deposited at a low temperature. It is characterized by crystallizing BST by carrying out a rapid thermal process (RTP), which is relatively less thermally burdened than furnace heat treatment. By repeatedly performing a series of processes consisting of BST film deposition at a low temperature and rapid thermal treatment, oxidation of the diffusion barrier metal film forming the plug connecting the lower electrode of the capacitor and the semiconductor substrate can be prevented and high dielectric properties can be ensured. In particular, as the BST film is deposited at a lower temperature than 400 ° C. and crystallized by RTP heat treatment, the leakage current characteristics are also improved by improving the characteristics of the electrode and the bulk BST interface, and the capacitance required in the device is a low temperature deposition process. ) Can be satisfied.
이하, 첨부된 도면 도1 내지 도10을 참조하여 본 발명의 실시예에 따른 반도체 메모리 소자 제조 방법을 설명한다.Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to the accompanying drawings.
먼저 도1에 도시한 바와 같이, 반도체 기판(10) 전면을 덮는 층간절연막(11)을 선택적으로 식각하여 상기 반도체 기판(10)과 캐패시터를 연결하기 위한 콘택홀을 형성하고, 전체 구조 상에 화학기상증착법으로 500 Å 내지 3000 Å 두께의 도핑된 다결정 실리콘막(12)을 형성하고, 화학적 기계적 연마(chemical mechanical polishing, 이하 CMP라 함) 공정을 실시하여 층간절연막(11)을 노출시키고 다결정 실리콘막(12)이 콘택홀 내부에만 남도록 한다. 상기 층간절연막(11)은 실리콘산화막과 실리콘산화막에 대해 식각선택비가 높은 SiN 또는 SiON 등과 같은 질화물의 적층구조로 이루어지고, 상기 실리콘산화막 및 질화물은 화학기상증착법으로 형성하며 질화물의 두께는 300 Å 내지 1000 Å이 되도록 한다.First, as shown in FIG. 1, an interlayer insulating film 11 covering the entire surface of the semiconductor substrate 10 is selectively etched to form a contact hole for connecting the semiconductor substrate 10 and a capacitor. The vapor deposition method forms a doped polycrystalline silicon film 12 having a thickness of 500 kV to 3000 kV, and performs a chemical mechanical polishing (hereinafter referred to as CMP) process to expose the interlayer insulating film 11 and the polycrystalline silicon film. (12) should remain inside the contact hole only. The interlayer insulating film 11 is formed of a stacked structure of a nitride such as SiN or SiON having a high etching selectivity with respect to the silicon oxide film and the silicon oxide film. The silicon oxide film and the nitride are formed by a chemical vapor deposition method and the thickness of the nitride is 300 m 3 to 1000 Å.
다음으로 도2에 도시한 바와 같이, 식각공정을 실시하여 콘택홀 내의 다결정 실리콘막(12) 일부를 제거하여 리세스(recess)를 형성한다.Next, as shown in FIG. 2, an etching process is performed to remove a portion of the polycrystalline silicon film 12 in the contact hole to form a recess.
이어서 세정 공정을 실시하고, 다결정 실리콘막(12)과 이후에 형성될 장벽금속막 간의 접촉 저항을 감소시키기 위하여 도3에 도시한 바와 같이 전체 구조 상에 100 Å 내지 300 Å 두께의 Ti막(13)을 증착하고 열처리로 Ti막(13)과 다결정 실리콘막(12)을 반응시켜 TiSix막(13A)을 형성한다.Subsequently, a cleaning process is performed, and in order to reduce the contact resistance between the polycrystalline silicon film 12 and the barrier metal film to be formed later, as shown in FIG. The TiSi x film 13A is formed by reacting the Ti film 13 and the polycrystalline silicon film 12 by heat treatment.
다음으로 도4에 도시한 바와 같이 습식식각으로 실리콘과 반응하지 않은 Ti막(13)을 제거하고, 전체 구조 상에 300 Å 내지 1000 Å 두께의 장벽금속막(14)을 증착한다. 상기 장벽금속막(14)은 TiN 또는 3 성분계 확산방지막인 TiSiN, TiAlN, TaSiN, TaAlN을 물리기상증착법(physical vapor deposition) 또는 화학기상증착법(chemical vapor deposition)으로 증착하여 형성한다.Next, as shown in FIG. 4, the Ti film 13 which has not reacted with silicon by wet etching is removed, and a barrier metal film 14 having a thickness of 300 mW to 1000 mW is deposited on the entire structure. The barrier metal film 14 is formed by depositing TiN or TiSiN, TiAlN, TaSiN, TaAlN, which are three-layer diffusion barrier films, by physical vapor deposition or chemical vapor deposition.
다음으로 도5에 도시한 바와 같이 장벽금속막(14)을 화학적기계적 연마하여 층간절연막(11)을 노출시킨다.Next, as shown in FIG. 5, the barrier metal film 14 is chemically mechanically polished to expose the interlayer insulating film 11.
이어서 산화물로 이루어지는 층간절연막과 귀금속으로 이루어지는 하부전극간의 접착력을 향상시키기 위하여 도6에 도시한 바와 같이 전체 구조 상에 50 Å 내지 200 Å 두께의 접착층(glue layer, 15)을 증착한다.Subsequently, in order to improve the adhesion between the interlayer insulating film made of oxide and the lower electrode made of noble metal, a glue layer 15 having a thickness of 50 kPa to 200 kPa is deposited on the entire structure as shown in FIG.
이어서 도7에 도시한 바와 같이, 상기 접착층(15) 상에 하부전극을 이룰 제1 전도막(16)을 형성한다. 제1 전도막(16)은 귀금속류인 It, Pt, Ru으로 형성하거나 또는 페롭스카이트 구조를 갖는 초전도체 산화물로 형성한다.Subsequently, as illustrated in FIG. 7, a first conductive layer 16 forming a lower electrode is formed on the adhesive layer 15. The first conductive film 16 is formed of noble metals It, Pt, Ru, or superconductor oxide having a perovskite structure.
다음으로 도8에 도시한 바와 같이, 제1 전도막(16) 및 접착층(15)을 선택적으로 식각하여 하부전극 패턴을 형성한다. 이때, TiN 또는 SiO2등으로 이루어지는하드마스크(도시하지 않음)를 이용하여 식각한다.Next, as shown in FIG. 8, the first conductive layer 16 and the adhesive layer 15 are selectively etched to form a lower electrode pattern. At this time, etching is performed using a hard mask (not shown) made of TiN or SiO 2 .
이어서 도9에 도시한 바와 같이, 하부전극 형성이 완료된 전체 구조 상에 BST 유전막(17)을 형성한다. BST 유전막(17) 형성 공정은 다음과 같이 이루어진다. 즉, 물리기상증착법 또는 화학기상증착법을 이용하여 50 Å 내지 300 Å 두께의 제1 BST 유전막을 400 ℃ 보다 낮은 온도에서 증착하고, 500 ℃ 내지 700 ℃ 온도의 질소분위기에서 30 초 내지 180 초 동안 RTP를 실시하여 제1 BST 유전막을 결정화시킨다. 이어서, 역시 물리기상증착법 또는 화학기상증착법을 이용하여 100 Å 내지 300 Å 두께의 제2 BST 유전막을 400 ℃ 보다 낮은 온도에서 증착하고, 500 ℃ 내지 700 ℃ 온도의 질소분위기에서 30 초 내지 180 초 동안 RTP를 실시하여 제2 BST 유전막을 결정화시킨다. 이와 같이 증착 및 RTP를 반복적으로 실시하여 BST 유전막(17)을 형성한다.Next, as shown in FIG. 9, the BST dielectric film 17 is formed on the entire structure where the bottom electrode is formed. The process of forming the BST dielectric film 17 is performed as follows. That is, the first BST dielectric film having a thickness of 50 kPa to 300 kPa is deposited at a temperature lower than 400 ° C by using physical vapor deposition or chemical vapor deposition, and RTP is carried out for 30 seconds to 180 seconds in a nitrogen atmosphere of 500 ° C to 700 ° C. To crystallize the first BST dielectric film. Subsequently, a second BST dielectric film having a thickness of 100 kPa to 300 kPa was also deposited at a temperature lower than 400 DEG C, using physical vapor deposition or chemical vapor deposition, and then in a nitrogen atmosphere of 500 DEG C to 700 DEG C for 30 to 180 seconds. RTP is performed to crystallize the second BST dielectric film. As described above, the BST dielectric layer 17 is formed by repeatedly performing deposition and RTP.
다음으로 도10에 도시한 바와 같이 BST 유전막(17) 상에 상부전극을 이룰 제2 전도막(18)을 형성한다. 제2 전도막(18)은 Pt 또는 Ru으로 형성한다.Next, as shown in FIG. 10, the second conductive film 18 forming the upper electrode is formed on the BST dielectric film 17. The second conductive film 18 is made of Pt or Ru.
전술한 바와 같이 이루어지는 본 발명은 저온 BST 증착 및 RTP 열처리를 통하여 장벽금속막의 산화없이 우수한 BST 유전 특성 및 누설전류 특성을 갖는 캐패시터를 제조할 수 있다.The present invention made as described above can produce a capacitor having excellent BST dielectric and leakage current characteristics without oxidation of the barrier metal film through low temperature BST deposition and RTP heat treatment.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 장벽금속막으로서 일반적인 TiN막을 이용하고, TiN막의 산화없이 BST의 고유전 특성을 얻을 수 있다. 따라서 향후 BST막을 화학기상증착법으로 형성하는 경우에도 적용할 수 있다.According to the present invention as described above, a general TiN film is used as the barrier metal film, and high dielectric properties of BST can be obtained without oxidation of the TiN film. Therefore, the present invention can also be applied to the formation of the BST film by chemical vapor deposition.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0927602A (en) * | 1995-07-12 | 1997-01-28 | Sharp Corp | Manufacture of capacitor and large capacitance capacitor |
| JPH09148538A (en) * | 1995-11-27 | 1997-06-06 | Mitsubishi Materials Corp | (ba, sr)tio3 thin film capacitor and its manufacture |
| JPH09219497A (en) * | 1996-02-13 | 1997-08-19 | Mitsubishi Electric Corp | High permittivity thin film structure, high permittivity thin film forming method and device |
| KR19980063642A (en) * | 1996-12-06 | 1998-10-07 | 포만제프리엘 | Method of surface cleaning of dielectric |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0927602A (en) * | 1995-07-12 | 1997-01-28 | Sharp Corp | Manufacture of capacitor and large capacitance capacitor |
| JPH09148538A (en) * | 1995-11-27 | 1997-06-06 | Mitsubishi Materials Corp | (ba, sr)tio3 thin film capacitor and its manufacture |
| JPH09219497A (en) * | 1996-02-13 | 1997-08-19 | Mitsubishi Electric Corp | High permittivity thin film structure, high permittivity thin film forming method and device |
| KR19980063642A (en) * | 1996-12-06 | 1998-10-07 | 포만제프리엘 | Method of surface cleaning of dielectric |
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