JPH10275901A - Capacitor, and memory structure an its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture the semispherical crystalline grain silicon layer with its surface area increased by a method wherein the dielectrics are arranged on the first electrode with irregular polysilicon surface in a specific thickness and then the second electrode is arranged on the dielectrics. SOLUTION: A semispherical crystalline grain silicon 102 having irregularities with smaller thickness about 40 nm or less is formed on the first electode 105 to be the first polysilicon base wherein a polysilicon-made vertical cylinder 104 and a lower side electrode of a cell capacitor are formed so as to match the dielectric 106 with the surface of the semispherical crystalline grain silicon and the polysilicon parts 104-105 between the silicon cystalline grains. Furthermore, the second polysilicon-made electrode 108 is formed on the dielectric 106. Through these procedurees, the semispherical crystalline grain silicon layer 102 in its surface increased by two time can be manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an electronic semiconductor device. More particularly, the present invention relates to capacitor structures and methods of making such structures.

[0002]

With the increasing demand for semiconductor memories and the competing difficulties,
There is a need for a highly integrated dynamic random access memory (DRAM) based on one-transistor and one-capacitor memory cells. But,
Miniaturized capacitors having standard silicon oxide and silicon nitride dielectrics have various problems, including a reduction in the amount of charge stored in the cell. Therefore, DRAM manufacturers are searching for additional dielectrics to increase the dielectric constant of the capacitor, and are searching for additional cell structures to increase the electrode area of the capacitor. For example, U.S. Pat. No. 5,554,557 discloses a fence-type capacitor with a textured polysilicon lower electrode to increase the capacitor's electrode area. This patent deposits a textured polysilicon by decomposing silane at a temperature of 560 ° C. and a pressure of about 200 mTorr, and thereby a layer of hemispherical grains with a maximum thickness of 50 nm to 150 nm. Is generated. Then silicon nitride, oxide / nitride / oxide,
Alternatively, a tantalum pentoxide dielectric is aligned and deposited. This completes the capacitor with the deposited polysilicon top electrode.

Ino et al., Rugged Surface Polycrystalline Silicon Film, Deposition of Polycrystalline Silicon Film with Rough Surface and Application to Stacked Dynamic Random Access Memory Capacitor Electrode
Deposition and its Application in a Stacked Dynam
ic Random Access Memory Capacitor Electrode) "1
4, J. Vac. Sci. Tech., B 751 (1996) states that the layer thickness is in the range of 40 nm to 150 nm and the optimum thickness is 1
Disclosed is a capacitor (FIG. 14) with a bumpy polysilicon of 00 nm.

[0004]

According to the present invention, a thickness of 40 mm is provided.
HSG (hemispherical) where the surface area is at least doubled due to deposition of sub-nm, but with high density of crystal nucleation, enhancement of vapor phase grain shape, and addition of impurities in a single heat treatment step. Crystal grains (hemispherical grains)
A silicon (rough polysilicon) layer is obtained. The preferred embodiment of textured polysilicon creates a capacitor electrode with enhanced surface area (dynamic memory cell) and allows the deposition of the capacitor dielectric without the electrode touching the oxygen source.

The present invention has the advantage that highly integrated memory cells can be manufactured using processing steps that are compatible with standard manufacturing methods for silicon integrated circuits.

[0006]

BRIEF DESCRIPTION OF THE DRAWINGS The invention can be better understood with reference to the following drawings.

Overview In a preferred embodiment, the use of densely packed small grains of hemispherical grain (HSG) silicon (textured polysilicon) allows the capacitor to be maintained with a limited electrode thickness. The area of the electrode (electrode plate) is increased. In the manufacturing method of the preferred embodiment, HSG silicon is first prepared under conditions of crystal growth with small grains but with a large areal density, and then vapor phase enhancement of the grains and gas phase impurity doping of the HSG silicon. And then immediately create an initial capacitor dielectric without touching the oxygen source. The use of small grain HSG silicon limits the effective thickness of the capacitor electrodes, thereby reducing the spacing between adjacent and multiple capacitor electrodes. Preliminary grain shape enhancement is possible by adding gas-phase impurities, but the surface becomes more susceptible to undesired oxidation, and therefore, by performing the initial dielectric immediately, a highly uniform capacitor dielectric layer can be obtained. can get.

FIGS. 1 and 2 illustrate a vertical cylinder 104 of polysilicon, which has the shape of an elongated crown, and a polysilicon base 105 forming the lower electrode of the cell capacitor. HSG silicon 1
2A and 2B are a cross-sectional view and a plan view of a preferred embodiment of the DRAM cell 100 provided with O.2. The dielectric 106 is HSG
It is aligned with the surface of silicon 102 and the polysilicon portions 104-105 between the HSG silicon grains. Polysilicon 108 forms the top (common) capacitor electrode. However, other members such as TiN can be used instead of polysilicon. Pass transistor (gate 1 with source 112 and drain 114)
10) connects the bit line 120 to the lower capacitor electrode through the polysilicon stem 122. The bit line 120 is arranged parallel to the plane of FIG. 1 and only the offset in contact with the drain 114 is shown in FIG. Note that the spacing distance between cell 100 and cell 100 'is determined by the minimum spacing distance between HSG 102 and HSG 102'. This distance is the minimum thickness of the top electrode 108. For example, the thickness of the crown-shaped polysilicon 104 can be 85 nm,
And the HSG silicon 102 grains can be raised, and can be about 30-40 nm in height;
The oxidized silicon nitride (NO) dielectric 106 has a thickness of 6
nm, and the minimum thickness of the top electrode 108 between adjacent cells is about 100 nm. Therefore, if the height of the HSG silicon 102 crystal grains is
If 70 nm, the minimum thickness of the top electrode 108 is 20 n
m, and reliability decreases.

Manufacturing FIGS. 3-8 are cross-sectional front views of the memory cell 100 portion of the substrate illustrating the steps of manufacturing the DRAM described below.

(A) Shallow trench isolation and CMO
Begin with a silicon substrate (or silicon on an insulator substrate) having an S rim and a twin well for the memory array well. Performing a threshold adjustment impurity implant, which can be different for cell transistors and various peripheral transistors;
Then, a gate dielectric is formed. Depositing a tambusten silicide overlying the polysilicon gate member and the silicon dioxide layer, and then patterning these layers so that oxide is deposited on the top gate 110, the peripheral transistor gate, and the gate Create interconnects with levels. See FIG.

(B) Doping of the lightly doped drain is performed, and then a sidewall dielectric is created over the gate by deposition and anisotropic etching. By performing the impurity addition, the source 112 and the drain 114 including the peripheral source / drain are formed, and the level of the transistor is completed. The structure is covered with a planarized dielectric layer (eg, BPSG). See FIG.

(C) A hole (through hole) in the planarized dielectric reaching the source 112 is defined by photolithography and created by etching.
In-situ blanket deposition of doped polysilicon and etch back are performed to create a stem 122 in the hole. Next, a hole in the planarized dielectric down to the drain 114 is defined photolithographically and created by etching. A blanket deposition of in-situ doped polysilicon is performed, and then a cap of tungsten silicide is deposited and patterned to create a bit line 120 connected to the drain 114. . A flattened bit line dielectric is created. This bit line dielectric can be used to form etch stop sublayers (eg,
Oxide and nitride partial layers).
See FIG.

(D) depositing an in-situ doped polysilicon layer; This layer will ultimately be part of the horizontal base for the vertical polysilicon crown of cell 100. Thereafter, a hole is lithographically defined in the polysilicon over stem 122. In addition, the holes can be fitted with polysilicon sidewalls (with blanket deposition and anisotropic etching) to obtain rounded corners and small diameters. The planarized bitline dielectric is then etched down to the stem 122 using polysilicon as an etching mask.
See FIG.

(E) depositing an in-situ doped polysilicon layer; This layer will be connected to stem 122 and will eventually form the remainder of the horizontal base for the crown. Thereafter, the crown base is defined by the dielectric layer and lithography. The dielectric and polysilicon are etched to produce a dielectric covered crown base. See FIG.

(F) In-situ deposition of a polysilicon layer doped with impurities (phosphorus impurities). This makes contact with the exposed end of the polysilicon base 105. Anisotropic etching is performed on the polysilicon to remove horizontal portions of the polysilicon (above the top of the dielectric over the base and over the bitline dielectric between the bases). This creates a crown as a sidewall on the dielectric and the base end. A chlorine based plasma etch can be used. The dielectric is then removed, leaving a free standing crown with a horizontal base held over the stem. This removal stops at the etch stop partial layer. FIG. 8 shows a situation in which an etch stop layer is provided on the surface of the bit line dielectric. With the embedded etch stop layer, the bottom of the crown base can also be exposed, thereby increasing the electrode area.

(G) HSG silicon is grown on the exposed surfaces of the polysilicon crown and base, and unavoidably, on the exposed bit line dielectric.
The growth of HSG silicon on (poly) silicon is 2
Seems to be done in stages. The first stage is the stage of crystal nucleation, and the second stage is the stage where the generated crystal nuclei coalesce and grow into crystal grains. Thus, silane is placed in a deposition container containing silicon wafers.
Silane decomposition at 571 ° C. and a flow rate of 450 sccm generates HSG silicon crystal nuclei on the polysilicon crown and base, and a thickness of about 1.76 × 10 ¹¹ / cm ² per minute. A layer of crystal nuclei of 12 nm is formed. See FIG. 9, which is a TEM view of a crystal nucleus. Of course, the exact silane flow rate and temperature to produce this large nucleation density will vary depending on vessel size and pressure and total wafer area. In fact, FIG. 12 is a graph showing the crystal nucleation density when the state of the processing vessel and the layer thickness are variously changed. For example, a silane flow rate of about 230 sccm at 571 ° C. for 2 minutes results in a layer of crystal nuclei of about 17 nm thick and having a nucleation density of about 4.9 × 10 ¹⁰ / cm ² .

HS at a temperature of 571 ° C. and a silane flow rate of 450 sccm
Continuing the G silicon growth for an additional 2.5 minutes results in a grain layer with a maximum thickness of about 30 nm. FIG. 10 is a diagram of the crystal grains, and the scale of this diagram is the same as that of FIG. Of course, if this layer of grains continues to grow to a thickness such as 75 nm, grains of this density will move in the direction in which the grains coalesce into a solid layer of polysilicon. Will give rise to a layer of progress. This means that the area enhancement is reduced. Note that the theoretical area increase due to densely arranged hemispheres is independent of hemisphere height. Thus, the densely arranged hemispheres provide the same area enhancement, but form a very thin layer. In contrast, the conventional small nucleation density example has a few very large grains at the same 30 nm thickness, as shown in FIG. The scale of FIG. 11 is the same as FIGS. 9 and 10.

(H) To ensure separation of adjacent crowns, the crowns are masked by photolithography and the HSG silicon over the bitline dielectric is etched. Alternatively, an anisotropic silicon etch without a mask can be used. This reduces the crown height, but preserves surface irregularities. The crown and base are comprised of in-situ doped polysilicon and undoped HSG silicon on the surface. After the photoresist is removed, the wafer is cleaned to remove the native oxide. HSG without added impurities
Silicon is not as easily oxidized as the underlying doped polysilicon.

(I) By enhancing the HSG silicon grain shape and adding phosphorus impurities to the grains by first baking the wafer at 850 ° C. in a hydrogen (H ₂ ) atmosphere for 30-60 minutes. , Any remaining native oxide has been removed, and the underlying polysilicon 104/1
The silicon atoms move from 06 onto the crystal grains 102, and the crystal grains are raised relative to the polysilicon disposed below. The area enhancement (electrical measurements on the resulting capacitors) increases from a factor of about 2.2 for the original grains to a factor of about 2.7 for the raised grains. FIG. 13a showing before and after shape enhancement,
See FIG. 13b. Thereafter, the atmosphere is switched from the hydrogen atmosphere to the phosphine (PH ₃ ) atmosphere for one minute. The phosphine decomposes at the silicon surface and the phosphorus diffuses into the grains, resulting in a surface impurity concentration of phosphorus impurities of 2 × 10 ²⁰ / cm ³ or more.

(J) All the phosphorus on the free surface, which can occur in cracks between the grains, and the grains heavily doped in the previous stages, are located at positions which are very reactive to oxidation. It is. In fact, natural oxides grow rapidly on heavily doped silicon,
Typically, it grows to a thickness in the range of 1 nm to 3 nm.
Such oxides (dielectric constant 2.5-3.5) will degrade the effective dielectric constant of capacitors using 6 nm oxidized silicon nitride. (4.5 n with a dielectric constant of 6.8, coated with a 2 nm thermal oxide having a dielectric constant of 3.9
m nitride). In addition, the deposition of silicon nitride by silane and the surface reaction of ammonia have an incubation time for nucleation on oxides, but a minimum incubation time for nucleation on silicon. Have. Thus, the deposited nitride will be thinner on oxidized silicon surfaces than on clean silicon. This thinner nitride (eg, 2 nm to 4.5 nm instead of 4.5 nm) will be too thin to prevent oxidation of the underlying grains during oxidation of the nitride. As a result, immediately after the phosphine gas phase impurity addition of the grains, the interior of the deposition vessel is evacuated and the temperature is reduced.
The temperature is lowered to 740 ° C., and dichlorosilane and ammonia are introduced to deposit a 4.5 nm thick silicon nitride dielectric. Alternatively, the wafer can be transferred from the evacuated phosphine doping vessel to a silicon nitride deposition vessel. Then, about 2 nm
The nitride is oxidized in steam at 850 ° C. to form an oxide of and fill the pinholes in the nitride.
This completes the dielectric.

(K) Deposit in-situ doped polysilicon and pattern it to create the top capacitor electrode.

(L) Create an intermediate level dielectric and interconnect. This also connects the peripheral circuits in the DRAM.

HSG Growth When the HSG grains grow and the layer becomes thicker, the grains begin to coalesce. While grain growth increases the sloped grain sidewall area, coalescence of grains causes the sidewalls to disappear.
Therefore, as shown in FIG. 14, the total surface area has a maximum value. In fact, FIG. 14 shows that after a grain shape enhancement during a gas phase impurity addition with an area enhancement factor measured by electrical measurements on a capacitor using uneven polysilicon as the lower electrode, It is the graph which showed the area enhancement factor (ratio of the total surface area with unevenness to the original flat area). The HSG growth conditions for the capacitor of FIG. 14 are the same as the growth conditions of the small crystal nucleation density example shown in FIG. In fact, FIG. 11 shows the lateral expansion of the crystal grains caused by coalescence. The preferred embodiment of large crystal nucleation density is due to the large grain sidewall area due to low coalescence.
For small thickness layers (eg for 30 nm thickness)
It should have a larger area enhancement factor. FIG.
Compare the crystal grain having a small lateral dimension in FIG. 11 with the crystal grain in FIG. Possibly, rapid nucleation and grain growth from high silane flow rates will result in less coalescence and smaller grain size, resulting in a large area enhancement factor.

Modification Example In the case of thin (eg, 30 nm thick) textured polysilicon with grain enhancement during gas phase impurity addition and oxygen-free immediate dielectric formation, the characteristics of the large area enhancement factor The preferred embodiment can be modified in various ways while maintaining the above.

For example, processing conditions can be changed. To form a thin nitride barrier followed by the deposition of an oxide-based dielectric (such as Ta ₂ O ₅ ), a silicon nitride dielectric deposition is performed by rapid thermal nitridation (1000 ° C.).
Can be replaced with NH ₃ ).

In addition, the uneven polysilicon electrode capacitor has an EEPRO between the floating gate and the control gate.
Can be a coupling capacitor in M, or can be a capacitor for a regular linear circuit,
Or it could be another coupling capacitor.

With respect to the above description, the following items are further disclosed. (1) (a) a first electrode having a textured polysilicon surface having a thickness less than about 40 nm; and (b)
A capacitor comprising: a dielectric disposed on the surface; and (c) a second electrode disposed on the dielectric.

(2) (a) forming a first electrode having an uneven polysilicon surface; and (b) changing a crystal grain shape of the uneven polysilicon in a reduced-pressure atmosphere. And (c) adding an impurity to the uneven polysilicon in an atmosphere containing phosphorus.

(3) (a) forming a first electrode plate having an uneven polysilicon surface; and (b) adding impurities to the uneven polysilicon in an atmosphere containing phosphorus. And (c) forming a dielectric on the surface after the doping in step (b) and before exposing the surface to an oxygen-containing atmosphere. .

(4) Due to the uneven polysilicon electrode for the capacitor, a large surface area can be obtained by adding a thin layer having a large crystal nucleation density and adding a gas phase impurity. Vapor doping also enhances grain shape and oxygen-free dielectric formation.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a preferred embodiment of a memory cell.

FIG. 2 is a front view of a preferred embodiment of a memory cell.

FIG. 3 is a cross-sectional front view of the first stage of the first preferred embodiment of the manufacturing method.

FIG. 4 is a cross-sectional front view of the next stage of FIG. 3 of the first preferred embodiment of the manufacturing method;

FIG. 5 is a cross-sectional front view of the next stage of FIG. 4 of the first preferred embodiment of the manufacturing method;

FIG. 6 is a cross-sectional front view of the next stage of FIG. 5 of the first preferred embodiment of the manufacturing method;

FIG. 7 is a cross-sectional front view of the next stage of FIG. 6 of the first preferred embodiment of the manufacturing method;

FIG. 8 is a cross-sectional front view of the next stage of FIG. 7 of the first preferred embodiment of the manufacturing method;

FIG. 9 is a diagram showing crystal nucleation and crystal grains.

FIG. 10 is another diagram showing crystal nucleation and crystal grains.

FIG. 11 is yet another diagram showing crystal nucleation and crystal grains.

FIG. 12 is a graph showing crystal nucleation density.

13A and 13B are diagrams showing crystal grain protrusions, wherein a is a diagram before shape enhancement and b is a diagram after shape enhancement.

FIG. 14 is a graph showing area enhancement.

[Explanation of symbols]

 105 first electrode 106 dielectric 108 second electrode

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Rick L. Wise United States Post Oak Drive, Plano, Texas 604 (72) Inventor Catherine Violet, United States Dallas, Texas, Spring Grove Avenue 13745 (72) Inventor Adity Banersey United States Plano, Texas, Buckster Drive 748 (72) Inventor Paul A. Tiner United States 7604 Plano, Texas, Buckster Drive

Claims (2)

[Claims] 1. A first electrode having a textured polysilicon surface having a thickness of less than about 40 nm; (b) a dielectric disposed on said surface; A second electrode disposed on the dielectric. 2. A step of forming a first electrode having an uneven polysilicon surface; and a step of changing the shape of the uneven polysilicon crystal grains in a reduced-pressure atmosphere. And (c) adding impurities to the uneven polysilicon in an atmosphere containing phosphorus.