KR19980080710A - Capacitors and Memory Structures and Methods - Google Patents

Abstract

The rugged polysilicon electrode for capacitors has a high layer area increase rate while having a thin layer by high nucleation density and vapor phase doping which increase grain shape and increase anoxic dielectric formation.

Description

Capacitors and Memory Structures and Methods

TECHNICAL FIELD The present invention relates to electronic semiconductor devices, and more particularly, to a capacitor structure and a method of manufacturing the same.

As the demand for semiconductor memory increases and competitive pressures increase, high density integrated circuit dynamic random access memories (DRAM) based on memory cells consisting of one transistor and one capacitor are required. However, scaled-down capacitors with standard silicon oxide and nitride dielectrics have problems such as a reduction in the amount of charge stored in the cell. Therefore, DRAM manufacturers are studying new dielectrics to increase capacitor dielectric constants and new cell structures to increase capacitor area. For example, US Pat. No. 5,554,557 discloses a DRAM cell having a fence-shaped capacitor with a rugged polysilicon bottom electrode to increase the capacitor area. This patent discloses the deposition of rugged polysilicon by silane deposition at a pressure of about 200 mTorr at 560 ° C. to produce a layer of hemispherical grains (HSG) with a maximum thickness of 50-150 nm. It is. A dielectric of silicon nitride, oxide / nitride / oxide or tantalum pentoxide is then deposited conformally to complete the capacitor with the top electrode of the deposited polysilicon.

Rugged Surface Polycrystalline Silicon Film Deposition and its Application in a Stacked Dynamic Random Access Memory Capacitor Electrode, 14 J. Vac. Sci. Tech. B 751 (1996) discloses capacitors with rugged polysilicon in layer thicknesses ranging from 40 nm to 150 nm optimal at 100 nm thickness (FIG. 14).

The present invention relates to HSG silicon (rugged polysilicon) having a thickness of less than 40 nm, with high nucleation density deposition and increased surface area at least twice by doping in gas phase grain shape and doping in a single furnace operation. Provide a layer. The rugged polysilicon according to the preferred embodiment forms a capacitor electrode with an increased surface area (dynamic memory cell), and the capacitor dielectric is deposited without exposing the electrode to an oxygen source.

This has the advantage of providing a high packing density memory cell using a process that is compatible with standard silicon integrated circuit fabrication.

1A and 1B are a cross-sectional view and a plan view of a memory cell according to a preferred embodiment of the present invention.

2A-2F are cross-sectional elevation views of steps in accordance with a first preferred embodiment method of the present invention.

3A-3C illustrate nucleation and grains.

4 shows the nucleation density.

5A and 5B illustrate grain expansion.

6 is a diagram showing an area increase rate.

Explanation of symbols for the main parts of the drawings

100, 100 ': DRAM cell

102, 102 ': HSG Silicone

104, 104 ': Polysilicon Vertical Cylinder

105: polysilicon base

106: dielectric

108: polysilicon

110, 110 ': gate

112: source

114: drain

120: bit line

summary

According to a preferred embodiment of the present invention, by using high density small grains of hemispherical grain silicon (ruggent poly), the capacitor electrode (plate) area is increased while maintaining a limited electrode thickness. In the preferred embodiment method, HSG silicon is first formed under conditions of growing small grains to a high area density, and then the doped capacitor HG silicon is added to the oxygen source immediately after doping the grain with gas phase enhancement. Form without exposing. By using small grain HSG silicon, it is possible to limit the effective thickness of the capacitor electrode, which can further reduce the space between adjacent multiple capacitor electrodes. Vapor phase doping can increase the preliminary grain shape, but the surface is susceptible to unwanted oxidation, resulting in a more uniform capacitor dielectric layer by immediate initial dielectric formation.

1A and 1B illustrate a DRAM in accordance with a preferred embodiment having HSG silicon 102 on a polysilicon base 105 forming a lower electrode of a cell capacitor and a polysilicon vertical cylinder 104 (having a long crown shape). A cross-sectional view and a plan view of the cell 100 are illustrated. Dielectric 106 is formed to conform to polysilicon portions 104-105 between the surface of HSG silicon 102 and the HSG silicon grains. Other materials, such as TiN, may be used, but in this embodiment polysilicon 108 forms the top (common) capacitor electrode. A pass transistor (source 112 and drain 114 and gate 110) connects the bit line 120 through the polysilicon stem 122 to the lower capacitor electrode, the bit line being the plane of FIG. 1A. Only offsets disposed parallel to and forming a contact to the drain 114 are shown in FIG. 1A. The separation between cell 100 and adjacent cell 100 ′ is determined by the minimum spacing between HSG 102 and HSG 102 ′, which is the minimum thickness of top electrode 108. For example, crown polysilicon 104 is 85 nm thick, HSG silicon 102 grains are inflated to about 30-40 nm high, oxidized silicon nitride (NO) dielectric 106 is 6 nm thick, The minimum thickness of the top electrode 108 between adjacent cells is about 100 nm. Thereby, if the HSG silicon grain is 70 nm high, the minimum thickness of the top electrode 108 is reduced to 20 nm, resulting in poor reliability.

Produce

2A-2F illustrate cross-sectional elevation views of DRAM fabrication steps in the memory cell 100 portion of the substrate as follows.

(a) Start with a silicon substrate (or silicon on insulator substrate) with twin wells for CMOS peripherals and shallow trench isolation in addition to the memory array wells. Threshold adjustment implantation is performed (which may vary for cell transistors and various peripheral transistors) to form a gate dielectric. After depositing a tungsten silicide and silicon dioxide layer coated with a polysilicon gate material, the layers are patterned to form oxide covered gate 110 and peripheral transistor gates and gate level interconnects. See FIG. 2A.

(b) After lightly doped drain implantation is performed, sidewall dielectrics are formed on the gate by deposition and anisotropic etching. Dopants are introduced to form a source 112 and a drain 114 including surrounding sources / drains to complete the transistor level. This structure is applied with a planarized dielectric layer (such as BPSG). See FIG. 2B.

(c) Holes (vias) are formed by photolithography and etched downward in the planarized dielectric to the source 112. An in situ doped polysilicon is deposited and etched back to form a stem 122 in the hole. Next, holes (vias) are formed in the planarized dielectric downwards with respect to the drain 114 by photolithography and etched. After depositing the in-situ doped polysilicon and the tungsten silicide cap on the entire surface, the bit line 120 is formed to be connected to the drain 114 by patterning. A planarized bit line dielectric is formed that can include an etchstop auxiliary layer (eg, an auxiliary layer of oxide and nitride). See FIG. 2C.

(d) After depositing an in-situ doped polysilicon layer that will eventually become the horizontal base portion for the vertical polysilicon crown of the cell 100, holes are formed in the polysilicon on the stem 122 by photolithography. In addition, polysilicon sidewalls (anisotropically etched with front deposition) may be formed in the holes to round the corners and reduce the diameter. The planarized bit line dielectric is then etched down against the stem 122 using polysilicon as an etch mask. See FIG. 2D.

(e) deposits an in-situ doped polysilicon layer that is connected to the stem 122 and will eventually form a residue of the horizontal base for the crown. Thereafter, the dielectric layer and the crown base are formed by photolithography. The dielectric and polysilicon are etched to produce a crown base coated with the dielectric. See FIG. 2E.

(f) Phosphorus dopant (using phosphorus (P)) Polysilicon is deposited uniformly, thereby forming a contact to the exposed end of the polysilicon base 105. The polysilicon is anisotropically etched to remove the horizontal portion of the polysilicon (on top of the dielectric on the base and on the bitline dielectric between the bases). Thereby a crown is formed as a sidewall on the dielectric and the base end, and a chloride-based plasma etch can be used. Next, the dielectric is removed leaving a separate crown with a horizontal base supported on the stem, which can be stopped at the etch stop auxiliary layer. FIG. 2F illustrates a state where an etch stop portion is provided on the surface of the bit line dielectric, and the bottom portion of the crown base may be exposed by the embedded etch stop layer, thereby increasing the electrode area.

(g) HSG silicon is grown on the exposed surface of the polysilicon crown and base and the exposed bit line dielectric. HSG silicon growth on (poly) silicon occurs in two stages; A nuclear growth step that occurs while nucleating and coalescing into grain. Thus, through the deposition chamber containing the silicon wafer, HSG silicon was nucleated on the polysilicon crown and the base by silane decomposition at 571 ° C. at a silane flow rate of 450 sccm at about 1.76 × 10 ¹¹ / cm 2 per minute. A nucleation density of about 12 nm is formed at the nucleation density. See FIG. 3A, which is a TEM diagram illustrating the nucleus. Of course, the exact silane flow rate and temperature to generate this high nucleation density will depend on the deposition chamber structure, pressure and total wafer area. In practice, FIG. 4 illustrates nucleation density for various process chamber states and layer thicknesses. For example, a silane flow rate of about 230 sccm at 571 ° C. for 2 minutes yields a 17 nm thick nucleus with a nucleation density of about 4.9 × 10 ¹⁰ / cm 2.

HSG silicon growth was continued at 571 ° C. again at 450 sccm silane flow rate for 2.5 min to produce a grain layer with a maximum thickness of about 30 nm. 3B shows grain, which has the same size as FIG. 3A. Of course, if this grain layer continues to grow to a thickness such as 75 nm, the density at this time will create a layer with grains that coalesce towards the polysilicon of the solid layer, which means that it reduces area gain. Since the theoretical area increase by dense hemispheres is independent of hemisphere height, the dense small hemispheres form a thinner layer while providing the same area increase. In contrast, the above-described lower nucleation density example has almost no large particles 30 nm thick as illustrated in FIG. 3C, which has the same size as FIGS. 3A and 3B.

(h) Mask the crown by photolithography and etch the HSG silicon on the bitline dielectric to ensure separation of adjacent crowns. Alternatively, a non-masked anisotropic silicon etch can be used, which reduces the crown height while maintaining surface ruggedness. The crown and base consist of undoped HSG silicone and in situ doped polysilicon on the surface. The wafer is cleaned after the photoresist removal to remove the native oxide, and the undoped HSG silicon is not as easily oxidized as polysilicon doped with underlying phosphorus.

(i) First baking the wafer at 850 ° C. in a hydrogen (H ₂ ) atmosphere for 30 to 60 minutes to increase the HSG silicon grain shape, doping the grain with phosphorus, thereby removing the remaining natural oxides and Migration from the lower polysilicon 104/106 onto the grain 102 causes the grains to swell compared to the lower polysilicon. The area increase (electrical measurement on the final capacitor) increases from about 2.2 times the original grain to about 2.7 times the bloated grain. See FIGS. 5A and 5B, respectively, before and after shape enhancement. Subsequently, switching from hydrogen atmosphere to hydrogen phosphide (PH ₃ ) atmosphere for 1 minute, whereby hydrogen phosphide decomposes on the silicon surface and diffuses phosphorus into grains to obtain a surface doping concentration of phosphorus greater than 2 × 10 ²⁰ / cm 3.

(j) Free surface phosphorus, which may occur in the gaps between the grains, and heavily doped grains from the preceding step, provide a highly reactive oxidation site. Indeed, natural oxides typically grow rapidly on densely doped silicon in thicknesses ranging from 1 to 3 nm, and these oxides (dielectric constants of 2.5 to 3.5) are effective for capacitors using 6 nm oxidized silicon nitride. The dielectric constant is degraded (4.5 nm nitride with dielectric constant 6.8 is applied with 2 nm thermal oxide with dielectric constant 3.9). In addition, deposition of the silicon nitride dielectric by silane and ammonia surface reactions has a latencies for nucleation on oxides, which is minimal in the case of nucleation on silicon, so that the deposited nitrides on pure silicon Thinner on the surface oxidized silicon. Such thinner nitrides (eg 2 to 2.5 nm instead of 4.5 nm) may be too thin to prevent oxidation of the underlying grains upon oxidation of the nitride. Therefore, immediately after hydrogen phosphide vapor phase doping of the grains, the deposition chamber is evacuated, the temperature is lowered to 740 ° C, flowed in dichlorosilane and ammonia, and the silicon nitride dielectric is deposited to a thickness of 4.5 nm. Alternatively, the wafer may be transferred from a hydrogen phosphide doping chamber to a silicon nitride deposition chamber under vacuum. The nitride is then oxidized in steam at 850 ° C. to add to the plug pin holes in the nitride to form an oxide of 2 nm to complete the dielectric.

(k) In situ doped polysilicon is deposited and patterned to form the upper capacitor electrode.

(l) Form interlevel dielectrics and interconnects, which also connect peripheral circuits to the DRAM.

HSG growth

As the HSG grain grows and the layer thickens, the grain begins to coalesce. Grain growth increases the inclined grain sidewall area while grain coalescence removes the sidewall, so the total surface area is maximized as illustrated in FIG. 6. In fact, FIG. 6 shows the area growth rate (ratio of total rugged surface area to original flat area) after grain shape increase during gas phase doping, which is a capacitor using rugged polysilicon as the bottom electrode. It is measured by electrical measurements on the phase. HSG growth conditions for the capacitor of FIG. 6 were the same as the low nucleation density example described above illustrated in FIG. 3C. Indeed, FIG. 3C shows the lateral stretching of grain resulting from coalescence. Using a high nucleation density according to a preferred embodiment, the amount of grain sidewall area will be greater due to lower coalescence, so that even if the layer thickness is small (eg 30 nm thick) it will have a large area growth rate. This can be confirmed by comparing the laterally dense grain of FIG. 3B with the grain of FIG. 3C. Increasing the silane flow rate to generate more rapid nucleation and grain growth can reduce coalescence, resulting in more dense grain, and consequently increase the area growth rate.

Variant

Preferred embodiments according to the present invention include thin (eg, 30 nm thick) rugged polysilicon in which grains are increased and vapor-free dielectrics are formed immediately during vapor phase doping, while maintaining a characteristic of high area growth. It can be modified in a way.

For example, processing conditions can be varied and a thin nitride barrier, followed by an oxide-based dielectric (such as Ta ₂ O ₅ ) deposition, replaces silicon nitride dielectric deposition with rapid thermal nitriding (NH ₃ at 1,000 ° C.). Can be formed.

In addition, the rugged polysilicon electrode capacitor may be a coupling capacitor of the EEPROM between the floating and control gates, or may be a general linear circuit or other capacitor for coupling.

According to the present invention, it is possible to provide the advantage of providing a high packing density memory cell using a process compatible with standard silicon integrated circuit fabrication.

Claims (3)

In the capacitor, (a) a first electrode comprising a rugged polysilicon surface having a thickness of less than about 40 nm, (b) a dielectric on the surface, and (c) a second electrode on the dielectric Capacitor comprising a. In the capacitor manufacturing method, (a) forming a first electrode having a rugged polysilicon surface, (b) changing the grain shape of the rugged polysilicon in a reducing atmosphere, and (c) doping the rugged polysilicon in a phosphorus containing atmosphere Capacitor manufacturing method comprising a. In the capacitor manufacturing method, (a) forming a first plate having a rugged polysilicon surface, (b) doping the rugged polysilicon in a phosphorus containing atmosphere, and (c) after the doping of step (b), forming a dielectric on the surface before exposing the surface to an oxygen containing atmosphere; Capacitor manufacturing method comprising a.