JPH11284153A - Nonvolatile semiconductor memory cell and method for writing data in nonvolatile semiconductor memory cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory cell whose column circuit is not required to comprise a high breakdown voltage transistor and in which it is ensured that the electric potential at the channel forming region is controlled when data is written into a memory element. SOLUTION: A nonvolatile memory cell has a memory cell which can be rewritten electrically, a word line and a bit line 21. The nonvolatile memory cell is also provided with a charging means for charging the bit line 21 through a base 11 when data is written into a memory element, a discharge control means Ts for controlling the discharge of the bit line 21 in accordance with whether data can be written into the memory element or not, and a conduction control means D for controlling conduction/nonconduction between the bit line 21 and a source/drain region 12 constituting the memory element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory cell having a floating gate and a control gate and comprising an electrically rewritable memory element, and a data writing method in the non-volatile semiconductor memory cell.

[0002]

2. Description of the Related Art One type of nonvolatile semiconductor memory cell known as an EEPROM is a highly integrated NAN.
D string type nonvolatile semiconductor memory cells (hereinafter, NA
ND strings). Each memory element constituting the NAND string is provided with a base (more specifically,
(in a p-type semiconductor substrate or a p-type well), and a source / drain region, a channel formation region,
It has a floating gate (also called a floating gate or a charge storage electrode) and a control gate (also called a control gate or a control electrode). And
In a NAND string, a plurality of memory elements are connected in series by sharing one source / drain area of a memory element with the other source / drain area of an adjacent memory element. A memory element at one end of the NAND string is connected to a bit line via a first selection transistor, and a memory element at the other end of the NAND string is connected to a common source line via a second selection transistor. Have been. Note that multiple NAs
The ND strings are arranged in the column direction, and the control gates are connected to word lines arranged in the row direction.

An outline of a data write operation to a memory element in a conventional NAND string will be described below.

In a NAND string, data is:
Writing is performed in order from the memory element located farthest from the bit line. In the data write operation, a high potential V _PP (for example, about 20 volts) is applied to a control gate of a memory element to which data is to be written (hereinafter, for convenience, referred to as a selected memory element). An intermediate potential V _PPm (for example, about 10 volts) is applied to a control gate of a memory element other than such a memory element (hereinafter, for convenience, referred to as an unselected memory element). On the other hand, for example, 0 volt is applied to the bit line. Then, the first selection transistor is turned on, and the second selection transistor is turned on.
Is turned off, the potential of the bit line is transferred to the source / drain regions of the memory element. Then, in the selected memory element, electrons are injected from the channel formation region to the floating gate based on a potential difference between the control electrode and the channel formation region. As a result, the threshold voltage of the selected memory element shifts from the initial negative to the positive direction, and data is written to the selected memory element. On the other hand, in a non-selected memory element, a large potential difference does not occur between the control electrode and the channel formation region, and injection of electrons from the channel formation region to the floating gate does not occur. As a result, the threshold voltage of the selected memory element does not change from the initial value, and the original data is held in the non-selected memory element.

[0005] Word lines are shared with other NAND strings. Therefore, another NAND string connected to the word line connected to the control gate of the selected memory element (hereinafter, such a NAND string is referred to as another NA string)
The high potential V _PP is also applied to a control gate of a memory element (hereinafter, such a memory element is referred to as another selected memory element) in the ND string. If data should not be written to such another selected memory element, an intermediate potential V _m (for example, about 10 volts) is applied to the bit line connected to another NAND string. As a result, in the other selected memory elements, a large potential difference does not occur between the control electrode and the channel formation region,
No electrons are injected from the channel formation region to the floating gate. Therefore, no data is written to the other selected memory elements, and the original data is retained.

Alternatively, in another NAND string, the first and second selection transistors are turned off, the NAND string is disconnected from the bit line (that is, put in a floating state), and the word line is connected via the channel coupling capacitance. There is also known a method of increasing a potential in a channel formation region by using a high potential V _PP applied to the _substrate . Note that such a method is also called a self-boost method.
As a result, in the other selected memory elements, a large potential difference does not occur between the control electrode and the channel formation region,
No data is written to the other selected memory elements.

[0007]

An intermediate potential V is applied to the bit line.
In the conventional method of applying a _m, is provided for each bit line, it is necessary to supply an intermediate voltage V _m to be applied to the bit line by a column circuit consisting of a sense amplifier or the like, in order that, the column circuit Must use a transistor with a high breakdown voltage. However, providing such a high breakdown voltage transistor requires a large area, and it is difficult to reduce the area of the nonvolatile semiconductor memory cell.

On the other hand, in the self-boost method, the ratio between the potential of the word line and the potential of the channel formation region depends on the channel coupling capacitance determined by the memory element structure and the N
It depends on the threshold voltage of another memory element forming the AND string. Therefore, there is a problem in that it is difficult to control the potential in the channel formation region, and the disturb resistance is likely to deteriorate.

Therefore, an object of the present invention is to eliminate the necessity of forming a column circuit with a transistor having a high breakdown voltage, to reduce the circuit area, and to further reduce the memory element structure and
For example, a nonvolatile semiconductor memory cell capable of reliably controlling a potential in a channel formation region when writing data to a memory element without depending on a threshold voltage of another memory element included in a NAND string, and such a nonvolatile semiconductor memory cell In a data writing method.

[0010]

According to the present invention, there is provided a nonvolatile semiconductor memory cell according to the present invention, comprising: (a) a source / drain region, a channel formation region, a floating gate, and a control gate. A nonvolatile semiconductor memory cell having an electrically rewritable memory element, (b) a word line connected to the control gate, and (c) a bit line connected to one of the source / drain regions. (D) charging means for charging the bit line via the base when writing data to the memory element; and (e) charging the bit line according to whether data can be written to the memory element. Discharge control means for controlling the discharge of the generated charges, and (f) conduction control for controlling conduction / non-conduction between the bit line and one of the source / drain regions Stage, characterized in that it comprises.

In order to achieve the above object, a method for writing data in a nonvolatile semiconductor memory cell according to the present invention comprises:
(A) an electrically rewritable memory element formed on a substrate and having a source / drain region, a channel formation region, a floating gate, and a control gate; (b) a word line connected to the control gate; A) a bit line connected to one of the source / drain regions, (d) charging means for charging the bit line via the base when writing data to the memory element, and (e) data transfer to the memory element. Discharge control means for controlling the discharge of the electric charge charged in the bit line according to whether or not writing is possible; and (f) for controlling the conduction / non-conduction between the bit line and one of the source / drain regions A data writing method in a nonvolatile semiconductor memory cell, comprising:
(A) At the time of writing data to a memory element, the bit line and the memory element are made non-conductive based on the operation of the conduction control means and the discharge control means, and the charge means charges the bit line via the base with the charge means. (B) Then, when writing data to the memory element based on the operations of the conduction control means and the discharge control means, the electric charge charged in the bit line is discharged, and then the bit line and the memory element are electrically connected. Then, when a predetermined potential is applied to the source / drain region via the bit line, and the data is not written to the memory element, the charge charged in the bit line is not discharged. The element is made conductive, and a potential based on the potential of the bit line due to the charge is applied to the source / drain region. (C) Then, a predetermined write potential is applied to the word line And wherein the Rukoto.

In the nonvolatile semiconductor memory cell of the present invention or the method of writing data in the nonvolatile semiconductor memory cell (hereinafter, these may be collectively simply referred to as the present invention), the charging means increases the pressure of the substrate. A booster circuit, a diode formed in the surface region of the base, one end of which is connected to the bit line, the discharge control means comprises a switching transistor provided on the bit line, and the conduction control means comprises one source / drain A configuration including a selection transistor provided between the region and the bit line can be employed. In this case, the booster circuit also serves as a circuit for erasing data stored in the memory element by boosting the base, and the circuit is connected to the bit line via the base when writing data to the memory element. A configuration including a switching unit for switching between a potential to be applied to the base to charge the electric charge and a potential to be applied to the base when erasing data from the memory element,
This is preferable in terms of simplifying the circuit configuration.

In the present invention, charging of the bit line is performed based on a capacitor formed by the bit line, the word line, and an insulating layer formed between the bit line and the word line. Can or
An electrode is formed above the bit line with a second insulating layer interposed therebetween, and charge of the bit line is performed by the bit line, the electrode,
And a configuration performed based on a capacitor formed by the second insulating layer.

The substrate in the present invention may be a p-type semiconductor substrate or a p-type well.
The p-type well may be formed in an n-type semiconductor substrate, or may be formed in an n-type well formed in a p-type semiconductor substrate. Further, all of the nonvolatile semiconductor memory cells may be formed in one p-type well, or a plurality of nonvolatile semiconductor memory cells may be formed in a plurality of p-type wells.

As a structure of the nonvolatile semiconductor memory cell in the present invention, a DINOR type, an AND type, or a NAND type nonvolatile semiconductor memory cell which is a kind of EEPROM can be cited. In the case of a NAND type nonvolatile semiconductor memory cell, a NAND string in which a plurality of memory elements are connected in series is formed, and one source / drain region of the memory element at one end of the NAND string is connected to a bit line via the conduction control means. It is connected to the. In the case of a NAND-type nonvolatile semiconductor memory cell, data is written and erased by injecting electrons into the floating gate and extracting electrons from the floating gate, and the data writing operation and the erasing operation are performed by Fowler-Nordheim (Fowler-Nordheim). -Nordheim)-It is performed based on the tunnel phenomenon. Note that the data erasing operation means changing the threshold voltages of a plurality of memory elements to a predetermined state at once, and the data writing operation changes the threshold voltage of the selected memory element to another predetermined state. Means that.

In the present invention, at the time of writing data to the memory element, the bit line is charged with electric charge via the base, and if necessary, a potential based on the potential of the bit line due to the charge is supplied to the source / drain region. , It is not necessary to use a transistor with a high withstand voltage in the column circuit, and the potential in the channel formation region can be reliably controlled without depending on the memory element structure or the like.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the invention (hereinafter abbreviated as embodiments).

(Embodiment 1) FIG. 1 shows a schematic partial cross-sectional view of a nonvolatile semiconductor memory cell of the present invention according to Embodiment 1, and FIG. 2 shows a principle equivalent circuit diagram. This nonvolatile semiconductor memory cell includes a plurality of memory elements (M ₀ to M ₀ ).
M ₇ ) is composed of NAND strings connected in series. Note that a plurality of NAND strings are arranged in the column direction (perpendicular to the paper surface). Each memory element (M _{0 to} M ₇ ) is formed in a base (more specifically, in a p-type well 11 formed in an n-type well provided in a p-type silicon semiconductor substrate 10). A source / drain region 12, a channel forming region 13, a floating gate 14,
And a control gate 15. Note that a plurality of memory elements (M _{0 to} M ₇ ) are connected in series by sharing one source / drain area of the memory element with the other source / drain area of the adjacent memory element. The memory element M _{7 at} one end of the NAND string is connected to the bit line 21 via the first selection transistor DSG, and the memory element M _{0 at} the other end of the NAND string is connected to the second selection transistor SSG. The common source line 24 is connected to the common source line 24. Further, the control gate 15
Are connected to word lines 20 arranged in the row direction. Note that, specifically, the control gate 15 and the word line 20 are common. The control gate 15 is covered with an insulating layer 16 made of, for example, SiO ₂ , and a bit line 21 is provided on the insulating layer 16. The plurality of word lines 20 and the plurality of bit lines 21 intersect in a grid via the insulating layer 16. Note that the first selection transistor DSG and the second selection transistor SSG are each a normal MOS FET.
It is composed of Floating gate 14 and control gate 1
5 may be composed of, for example, a polysilicon layer containing impurities. The bit line 21 may be made of a wiring material such as aluminum or aluminum alloy.

In the nonvolatile semiconductor memory cell of the first embodiment, when writing data to the memory element, the bit line 21 is further connected to the base via the p-type well 11.
Charging means for charging electric charges to the memory elements M _{0 to} M ₇
Discharge control means for controlling the discharge of the electric charge charged in the bit line 21 in accordance with whether data can be written to the bit line 21, and conducting / non-conducting between the bit line 21 and one of the source / drain regions. Conduction control means for controlling is provided. Note that the conduction control means includes a first selection transistor DSG. Further, the discharge control means includes a switching transistor T _S provided on the bit line 21. Further, the charging means includes a booster circuit for boosting the p-type well 11 serving as the base, and a diode D formed on the surface region of the p-type well 11 serving as the base and having one end connected to the bit line 21. I have. Diode D is, specifically, n ⁺ -type impurity region 23 formed in the surface region of p-type well 11 located at the bottom of contact portion 22 for connecting the bit line and first select transistor DSG. , P-type well 11
It is composed of an n-junction diode. Note that the n ⁺ -type impurity region 23 corresponds to one source / drain region of the first select transistor DSG.

The bit line 21 is connected to the column circuit 31 via the switching transistor T _S , the word line 20 is connected to the row circuit 30 and the source line 24
Are connected to the source circuit 32. Also, the base 11
(Further, the other end of the diode D) is connected to a well circuit 33 corresponding to a booster circuit constituting a charging unit. The well circuit 33 also serves as a circuit for erasing data stored in the memory element by boosting the p-type well 11 serving as a base. This circuit is used for writing data to the memory element. 11 to charge the bit line 21 through the p-type well 11
And a switching means for switching between a potential to be applied to the p-type well 11 and a potential to be applied to the p-type well 11 when erasing data from the memory element.

In FIG. 2, the symbol “C _a ” means the capacitance of the capacitor C. The details of the capacitor C will be described later.

Hereinafter, the equivalent circuit diagram shown in FIG.
The write operation (program operation) and (verify) read operation of the nonvolatile semiconductor memory cell according to the first embodiment will be described below with reference to the operation timing charts shown in FIGS. FIG. 3 shows an operation timing chart in a NAND string including a memory element to which data is to be written, and FIG. 4 shows another NAND connected to a word line connected to a control gate of the memory element to which data is to be written. FIG. 4 shows an operation timing chart in a string.
The meanings of the symbols used in FIGS. 2, 3 and 4 are as shown in Table 1 below.

[0023]

Table 1 φ _WELL : Control pulse applied to the anode (p-type well 11) of diode D φ _DSG : Control pulse applied to first select transistor DSG φ _SSG : Applied to second select transistor SSG Control pulse φ _{CG_A} : control pulse applied to the control gate of the unselected memory element φ _{CG_B} : control pulse applied to the control gate of the selected memory element φ _TS : control pulse V _W applied to the switching transistor T _S : A potential applied to the p-type well 11 V _pass : a gate voltage applied to the first selection transistor DSG, or a potential V _pgm applied to a control gate of an unselected memory element V _pgm : a selected memory element and another selected memory potential V _d is applied to the control gate of the element: when writing data, generic V _cc of potential output from the column circuit: during data write, Potential V _prog is output from the column circuit when the memory device not write data: data write, the potential V _b is output from the column circuit when data is written into the memory device: the bit at the time of data writing to the memory device Line potential V _r : Generic term of potential applied during (verify) read setup V _ref : Potential output from column circuit during (verify) read setup

First, when writing data to the memory element, the bit line and the memory element are turned off based on the operations of the conduction control means and the discharge control means. That is, at the time of program setup, the first selection transistor DSG corresponding to the conduction control unit and the switching transistor T _S corresponding to the discharge control unit are turned off, and the bit line 21 and the memory elements (M _{0 to} M ₇ ) are set. Are turned off, and the bit line 21 is brought into a floating state. Note that the second selection transistor SSG is also turned off.

Then, at time t ₀ , the potential of the control pulse φ _WELL from the well circuit 33 constituting the charging means is changed from the reference potential (for example, 0 volt) to the potential V _W to change the potential of the p-type well 11 to V. _W. Operation of the well circuit 33 is continued until time t _2. p-type well 1
1 is connected to the bit line 21 via the diode D. The bit line 21 is in a floating state. Therefore, assuming that the forward conduction voltage of the diode D is V _ON (for example, about 0.7 volt), if (V _W −V _ON )> 0, the diode D conducts. As a result, the charge on the bit line 21 from the well circuit 33 via the p-type well is a substrate is charged, the potential V _b of the bit line 21 is maintained until the (V _W -V _ON), and the time t _2.

Data set is performed at time t ₁ at the time of program setup. That is, the potential V _d output from the column circuit, when not write data to the memory device to the potential V _cc, when data is written into the memory device is a potential V _prog (e.g. 0 volts).

At time t ₂ at the time of program setup, the potential of the control pulse φ _WELL from the well circuit 33 is returned to the reference potential (for example, 0 volt). As a result, the diode D is turned off. The lowered potential of the bit line 21, when the capacitance coupled to the bit line 21 other than a capacitor C having a capacitance C _a and the C _b, the potential V _p of the bit line 21 is as follows. Here, it is desirable for V _p, for example, about 10 volts, the structure and configuration of a nonvolatile semiconductor memory cell may be designed to potential V _W to be applied. _{V p = (V W -V ON} ) C a / (C a + C b)

Next, when writing data to the memory element based on the operations of the conduction control means and the discharge control means, the electric charge charged in the bit line is discharged. That is,
As shown in FIG. 3, time t at the time of program setup
_{At 3} , the control pulse φ is applied to the switching transistor T _S.
TS is applied to turn on the switching transistor T _S. As a result, electric charges charged in bit line 21 is discharged, the potential V _b of the bit line 21 is equal to V _d. That is, it becomes V _prog (for example, 0 volt).

On the other hand, when data is not to be written to the memory element, the charge stored in the bit line 21 is not discharged. That is, as shown in FIG. 4, the switching transistor T _S is kept off. Thus, the potential V _b of the bit line 21 is held at V _p.

Next, at the time of programming, at time t ₄ , the control pulse φ _{DSG is} supplied to the first selection transistor _DSG.
Is applied. As a result, the bit line 21 and the memory elements (M _{0 to} M ₇ ) conduct. When writing data to the memory element, the potential of the bit line 21 is V _prog , so a predetermined potential (V _prog ) is applied to the source / drain region 12 via the bit line 21. . On the other hand, when data is not written to the memory element, the potential of the bit line 21 is V _p, and therefore, the potential V _b based on the potential V _b (= V _p ) of the bit line 21 due to the charge. _inh is applied to source / drain region 12.
Since the capacitance of the capacitor C is sufficiently larger than the capacitance coupled to the channel formation region of the memory element, the potential V
_inh is substantially equal to V _p.

Then, a control pulse (φ
_{CG_A} or _{φCG_B} ). That is, the word line 20
To the predetermined write potential (V _pass or V _pgm )
And Incidentally, the V _pass for example about 10 volts, may be set to V _pgm example about 20 volts. In the NAND string including the selected memory element, the potential difference between the control gate 15 of the selected memory element and the channel forming region 13 is approximately (V _pgm −V _prog ) (for example, about 20 volts), and From the gate to the floating gate 14. As a result, the threshold voltage of the selected memory element shifts from the initial negative to the positive direction, and data is written to the selected memory element. The potential difference between the control gate 15 of the unselected memory element and the channel formation region 13 is approximately (V _pass -V _prog ) (for example, about 10
Volts), and injection of electrons from the channel formation region 13 to the floating gate 14 does not occur. As a result, the threshold voltage of the non-selected memory element is maintained at the original value.

On the other hand, in another NAND string,
The potential difference between the control gate 15 of the other selected memory element and the channel forming region 13 is approximately (V _pgm -V _p ) (for example, about 10 volts), and the unselected memory element in another NAND string. The potential difference between the control gate 15 and the channel formation region 13 is approximately (V _pass −
V _p ) (eg, about 0 volts). As a result, injection of electrons from the channel formation region 13 to the floating gate 14 does not occur. As a result, the threshold voltages of all the memory elements of the other NAND strings are maintained at the original values.

At the end of the program (time t ₅ ), the first selection transistor DSG and each of the memory elements (M _{0 to} M ₇ ) are turned off.

[0034] (verify) the read setup, reset the potential V _b of the bit line 21 V _prog (e.g., 0 volts), then at time t _6, the column circuit 3
The output potential V _d from 1 and V _cc, to charge all the bit lines 21 to the (V _cc -V _th). Here, V _th is the threshold voltage of the memory element. Then, at time t ₇ is the start of the (verification) lead, the first selection transistor DSG and second selection transistors SSG is turned on, (verify) to the memory device connected to the word line to perform a read V _ref is applied, and a word line connected to a memory element that does not perform (verify) read is applied with V _{ref.
Apply r} . (Verify) The memory element to be read is turned on or off depending on the relationship between the threshold voltage _Vth and the potential _Vref applied to the word line 20. Then, in the case of the ON state, the charge charged in the bit line 21 is discharged through the memory element, and the bit line 2 is discharged.
1 drops. On the other hand, in the off state, the charge charged in the bit line 21 is not discharged via the memory element, and the potential of the bit line 21 is maintained. Therefore, the input potential V _d to the column circuit 31 is a value that reflects the potential of the bit line 21 corresponding to the ON / OFF state of the memory element to perform (verify) lead. By detecting this value in the column circuit 31, it is possible to detect the data holding state of the memory element to be subjected to (verify) read.

By performing a data write operation (program operation) and a (verify) read operation of the nonvolatile semiconductor memory cell based on the above procedure, the threshold value of the memory element to which data is to be written is set to a desired value (V _ref ).
Can be controlled so that the threshold value of the memory element to which data is not written does not change.

In the first embodiment, a schematic partial cross-sectional view is shown in FIG. 1, and an equivalent circuit diagram is shown in FIG. 5, in which an insulating layer 16 is formed between a bit line and a word line. cage, the bit line 21, the capacitor C ₀ -C ₇ from the portion of the word line 20 insulating layer 16 and is sandwiched between the bit lines 21 and word lines 30, are formed. Charging of the charge to the bit line 21 is made based on these capacitors C ₀ -C _7. The capacitance C _a of the above-described capacitor C is equal to the sum of the capacitances of the capacitor composed of one bit line 21, a plurality of word lines 20, and the insulating layer 16. When charging the bit line 21 via the base by the charging means, the potential of the word line 20 may be set to a reference potential (for example, 0 volt). By changing the reference potential, the potential V _inh applied to the source / drain region 12 is changed.
Can be set to a desired potential.

FIG. 6 shows a circuit diagram of an example of a booster circuit provided with switching means. The booster circuit may be, for example, a known booster circuit including an N-stage including a capacitor and a transfer transistor, two consecutive complementary clocks input thereto, and a limiter circuit. The switching means comprises resistors R ₀ , R _P , R _E , switching transistors T _P , T _E , and an operational amplifier, and controls the cycle of the input clock according to the output of the operational amplifier. When erasing data from a memory element,
Enter the signal phi _E to the switching transistor T _E, and turning on the switching transistor T _E. On the other hand, when charging the bit line through the base when writing data to the memory element, the switching transistor T
_A signal φ _P is input to _P to turn on the switching transistor TP. Thereby, the output V of the booster circuit
_OUT switches between a potential V _W to be applied to the base to charge the bit line through the base when writing data to the memory element and a potential to be applied to the base when erasing data from the memory element. Can be

(Embodiment 2) Embodiment 2 is a modification of the nonvolatile semiconductor memory cell of the present invention described in Embodiment 1. The nonvolatile semiconductor memory cell of the second embodiment is different from the nonvolatile semiconductor memory cell of the first embodiment in that a schematic partial cross-sectional view is shown in FIG. 7, and an equivalent circuit diagram is shown in FIG. , For example, above the bit line 21.
The point is that the electrode 25 is formed via the second insulating layer 17 made of iO ₂ . The electrode 25 is disposed in parallel with the bit line 21 and is made of, for example, a metal wiring material. The charge of the bit line 21 is performed based on the capacitor C formed by the bit line 21, the electrode 25, and the second insulating layer 17. A reference potential of, for example, 0 volt may be applied to the electrode 25. Alternatively, by changing the according reference potential, the potential V _{in h} applied to the source / drain regions 12
Can be set to a desired potential.

Depending on the configuration of the nonvolatile semiconductor memory cell, not only the capacitor C is formed by the bit line 21, the electrode 25, and the second insulating layer 17, but also the bit line 21, the word line 20, and the bit Line 21 and word line 30
From the portion of the insulating layer 16 sandwiched between the capacitors C _{0 to} C ₇
May be formed.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these embodiments. The structure of the nonvolatile semiconductor memory cell described in the embodiment of the invention or the value of the potential to be applied is an example, and can be changed as appropriate. In the embodiment of the present invention, the diode D is connected to the n ⁺ -type impurity formed in the surface region of the p-type well 11 located at the bottom of the contact portion 22 for connecting the bit line and the first select transistor DSG. The region 23 and the p-type well 11
Although constituted by an n-junction diode, it is not limited to such an embodiment. For example, the diode D is connected to the contact 2
In the base (p-type semiconductor substrate or p-type well) located at a position other than the bottom part of the second part 2,
It may be formed independently, or may be formed in a p-type semiconductor substrate or p-well region different from the base on which the memory element is formed. Further, the diode D is not limited to a pn junction diode. The diode D can also be formed from a Schottky diode formed by providing, for example, a silicide layer in the surface region of the p-type well 11. Alternatively, when forming the bit line 21, a barrier layer or a glue layer made of, for example, titanium silicide or TiN is usually formed, and such a barrier layer or a glue layer is also formed on the surface of the p-type well 11. Thereby, a part of the bit line 21 (more specifically,
A conductive region common to the barrier layer and a part of the glue layer) may be formed in the surface region of the p-type well 11.

[0041]

According to the present invention, it is not necessary to constitute a column circuit with a high breakdown voltage transistor. Therefore, the circuit area can be reduced. In addition, the potential in the channel formation region can be reliably controlled when writing data to the memory element without depending on the memory element structure or the threshold voltage of another memory element included in the NAND string, for example. It is possible to obtain a nonvolatile semiconductor memory cell having durability.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a nonvolatile semiconductor memory cell of the present invention according to Embodiment 1 of the present invention.

FIG. 2 is a theoretical equivalent circuit diagram of a nonvolatile semiconductor memory cell of the present invention.

FIG. 3 is a diagram showing operation timing of a nonvolatile semiconductor memory cell of the present invention.

FIG. 4 is a diagram showing operation timings of the nonvolatile semiconductor memory cell of the present invention.

FIG. 5 is an equivalent circuit diagram of the nonvolatile semiconductor memory cell according to the first embodiment of the present invention;

FIG. 6 is a circuit diagram illustrating an example of a booster circuit including a switching unit.

FIG. 7 is a schematic partial cross-sectional view of a nonvolatile semiconductor memory cell according to the second embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of the nonvolatile semiconductor memory cell according to the second embodiment of the present invention.

[Explanation of symbols]

M ₀ ~M ₇ ... memory device, 10 ... p-type semiconductor substrate, 11 ... p-type well, 12 ... source / drain region, 13 ... channel forming region, 14 ... floating Gate, 15: control gate, 16: insulating layer, 1
7 ... second insulating layer, 20 ... word line, 21 ...
.Bit line, 22 contact part, 23 n ⁺
Type impurity region, 24 ... source line, 25 ... electrode,
30 ... row circuit, 31 ... column circuit, 32 ...
· Source circuit, 33 ··· Well circuit, DSG ··· First selection transistor, SSG ··· Second selection transistor, T _S ··· Switch transistor, D ···
Diode, C, C ₀ ~C ₇ ··· capacitor

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (12)

[Claims] 1. An electrically rewritable memory element formed on a substrate and having a source / drain region, a channel formation region, a floating gate, and a control gate. (B) connected to the control gate. A nonvolatile semiconductor memory cell having a word line and (c) a bit line connected to one of the source / drain regions, and (d) when writing data to a memory element, (E) discharging means for controlling the discharge of the charge charged on the bit line according to whether data can be written to the memory element, and (f) bit line; A non-volatile semiconductor memory cell, comprising: conduction control means for controlling conduction / non-conduction between one source / drain region. 2. The charging means comprises a booster circuit for boosting the base, a diode formed in a surface region of the base and one end of which is connected to a bit line, and the discharge control means includes a switch provided on the bit line. 2. The nonvolatile semiconductor memory cell according to claim 1, wherein the conduction control means comprises a selection transistor provided between one of the source / drain regions and the bit line. 3. The booster circuit also serves as a circuit for erasing data stored in a memory element by boosting a base, and the circuit is configured to perform bit writing via the base when writing data to the memory element. 3. The semiconductor device according to claim 2, further comprising a switching unit configured to switch between a potential to be applied to the substrate for charging the line and a potential to be applied to the substrate when erasing data from the memory element. The nonvolatile semiconductor memory cell according to claim 1. 4. The method according to claim 1, wherein charging of the bit line is performed based on a capacitor formed by a bit line, a word line, and an insulating layer formed between the bit line and the word line. Item 2. The nonvolatile semiconductor memory cell according to item 1. 5. An electrode is formed above the bit line with a second insulating layer interposed therebetween.
2. The method according to claim 1, wherein the step is performed based on a capacitor formed by a bit line, an electrode, and a second insulating layer.
3. The nonvolatile semiconductor memory cell according to 1. 6. A NAN in which a plurality of memory elements are connected in series.
2. The nonvolatile semiconductor device according to claim 1, wherein a D string is formed, and one source / drain region of a memory element at one end of the NAND string is connected to a bit line via the conduction control means. Memory cells. 7. An electrically rewritable memory element formed on a substrate and having a source / drain region, a channel formation region, a floating gate, and a control gate. (B) connected to the control gate. A word line; (c) a bit line connected to one of the source / drain regions; (d) charging means for charging the bit line via the base when data is written to the memory element; (e) a memory Discharge control means for controlling the discharge of the electric charge charged in the bit line according to whether data can be written to the element, and (f) conduction / non-connection between the bit line and one of the source / drain regions A method of writing data in a nonvolatile semiconductor memory cell having conduction control means for controlling conduction, wherein: (A) when writing data to a memory element, Charging the bit line via the base by the charging means in a state where the bit line and the memory element are made non-conductive based on the operation of the means and the discharge control means; and (B) subsequently, the conduction control means and the discharge control means When data is written to the memory element based on the operation of the bit line, after the charge charged in the bit line is discharged, the bit line and the memory element are made conductive, and the source / source is connected via the bit line.
When a predetermined potential is applied to the drain region and the data is not written to the memory element, the bit line and the memory element are made conductive while the electric charge charged to the bit line is not discharged, and the electric charge is charged. (C) applying a predetermined write potential to the word line after that, and applying a predetermined write potential to the word line. 8. The charging means comprises a booster circuit for boosting the base, a diode formed in a surface region of the base and one end of which is connected to a bit line, and the discharge control means includes a switch provided on the bit line. 8. The data writing method according to claim 7, wherein the conduction control means comprises a selection transistor provided between one of the source / drain regions and the bit line. . 9. The booster circuit also serves as a circuit for erasing data stored in the memory element by boosting the base, and the circuit is used to write data to the memory element via the base when writing data to the memory element. 9. A device according to claim 8, further comprising switching means for switching between a potential to be applied to the substrate to charge the line and a potential to be applied to the substrate when erasing data from the memory element. A data writing method in the nonvolatile semiconductor memory cell described in the above. 10. The non-volatile semiconductor memory cell further includes an insulating layer formed between the word line and the bit line, and charging of the bit line is performed by the bit line, the word line, and the bit line and the word. 8. The method according to claim 7, wherein the method is performed based on a capacitor formed by the insulating layer formed between the line and the line. 11. The non-volatile semiconductor memory cell further includes a second insulating layer formed on the bit line, and an electrode formed on the second insulating layer. The method according to claim 7, wherein the method is performed based on a capacitor formed by the bit line, the electrode, and the second insulating layer. 12. An NA in which a plurality of memory elements are connected in series.
The method according to claim 7, wherein an ND string is formed, and a memory element at one end of the NAND string is connected to a bit line via the conduction control means.