JPH11282405A - Interlace display method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display the images of excellent image quality without degrading a vertical resolution even in the case of displaying the images based on the video signals of a low resolution in a display device capable of independently displaying plural screens. SOLUTION: In a second field period, read is performed from an upper storage area in the order of '2-1', '2-0', '2-0' and '2-1' and the read is performed from a lower storage area in the order of '2-3', '2-2', '2-2' and '2-3' parallelly to it. After a vertical, exchange operation is executed between the first '2-1' from the upper storage area and the first '2-3' from the lower storage area, '2-3', '2-0', '2-0' and '2-1' are written to the row numbers 0-3 (display rows 0-3) of an upper screen by scanning lines L0-L7 and '2-1', '2-2', '2-2' and '2-3' are written to the row numbers 0-3 (display rows 4-7) of a lower screen. On the upper screen of the row number 0, not '2-3' but information for indicating black is set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an interlace display method in a non-interlace display device such as a plasma display panel (PDP) device.

[0002]

2. Description of the Related Art There is a PDP device as a non-interlaced display device capable of displaying at a high resolution such as XGA (1024 × 768 (width × length)). In a recent PDP device, as shown in FIG. 6, there is a configuration in which a plasma display panel is independently driven and displayed on an upper screen 1A and a lower screen 1B. In the configuration shown in FIG. 6, the upper screen 1A
Are represented by scanning lines 0 to (2n-1). However, n ≧ 1. Lower screen 1B is 2n- (4n-1)
The scanning lines 0 to (2n-1) are displayed by the upper driving circuit (not shown in FIG. 6).
The (4n-1) scan lines are independently driven by a lower drive circuit (not shown in FIG. 6).

On the other hand, a high-resolution PDP device sometimes displays an interlaced video signal with a low resolution.

As shown in FIG. 7, the interlaced video signal includes a first field composed of even-numbered scanning lines L0, L2, L4, and L6 and an odd-numbered scanning line L1, L3, L5, L7.
This is a method of composing a screen of one frame with the second field consisting of:

When displaying such an interlaced video signal, a high-resolution PDP device uses a scanning line L (2).
i) and L (2i + 1) can be displayed simultaneously, that is, image information for two fields can be displayed simultaneously (note that i
= 0 to 3. ).

[0006]

However, in the above-described display, a moving image such as a fast-moving television displays a blurred image for each scanning line. There was a problem that it was hard to see.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. In a display device capable of independently displaying a plurality of screens, even when an image based on a low-resolution video signal is displayed, the vertical resolution is reduced. An object of the present invention is to provide an interlaced display method in a display device capable of displaying an image of good quality without deterioration.

[0008]

According to a first aspect of the present invention, there is provided an interlaced display method capable of displaying a first row to a fourth nth row (n is a natural number) constituted by an upper screen and a lower screen. A method of displaying an interlaced input image on the display screen using a display device having a display screen, wherein the upper screen is a first line to a second line of the display screen.
The n-th row is displayed based on the image information stored in the upper storage area, and the lower screen is the (2n) th of the display screen.
+1) The display of the rows from the (n) th row to the (4n) th row is performed based on the image information stored in the lower storage area, and the input video signal is a first to a (2n) th row each indicating one row of image information. (A) The first to n-th row display video signals are stored in the first to n-th row areas of the upper storage area, and the (n + 1) to 2n-th row display signals are displayed. Storing the video signal in the first to n-th rows of the lower storage area; and (b) in the first field period, for the j-th row (j = 1 to n) of the upper storage area. Is output twice and written sequentially to the (2j-1) th and 2jth rows of the upper screen, and in parallel to the jth row of the lower storage area. When the stored row display video signal is 2
Output every time, the (2j-1) th line and the 2jth line of the lower screen
(C) performing a display operation of the upper screen and the lower screen after the step (b) in the first field period; and (d) in the second field period, A row display video signal stored in the n-th row of the lower storage area is output and written to the first row of the upper screen, and then the k-th row (k = 1 to n-1) of the upper storage area is written. The stored row display video signal is output twice and sequentially written in the 2kth row and the (2k + 1) th row of the upper screen, and then the row display video signal stored in the nth row of the upper storage area And outputs the row display video signal stored in the nth row of the upper storage area, and writes the row display video signal in the first row of the lower screen. At the k-th row of the lower storage area (k = 1 to n-1) The 2k rows of the bottom of the screen and outputs the stored row display image signal by twice and the (2k +
1) sequentially writing data to rows and then outputting a row display video signal stored in the nth row of the lower storage area and writing it to the 2nth row of the lower screen; and (e) the second field period. Performing a display operation of the upper screen and the lower screen after the step (d), wherein in the step (b) and the step (d),
The information corresponding to the display on the first line of the upper screen is set to a display disabled value (black).

According to a second aspect of the present invention, there is provided an interlace display method, comprising: a display device having a display screen capable of displaying a first to a fourth (n is a natural number) lines constituted by an upper screen and a lower screen. A method of displaying an interlaced input image on the display screen by using the first screen and the second n-th row of the display screen based on the image information stored in the upper storage area. And the lower screen is the (2n + 1) th line to the 4nth line of the display screen.
The row display of the row is performed based on the image information stored in the lower storage area, and the input video signal includes first to second n row display video signals each indicating one row of image information,
(a) The first to n-th row display video signals are stored in the first to n-th rows of the lower storage area, and the (n + 1) to 2n-th row display video signals are stored in the lower storage area. From the first line of the area
(B) during the first field period, storing the data in the j-th row (j =
1 to n) are simultaneously written to the (2j-1) th row and the 2jth row of the upper screen, and in parallel with this, stored in the jth row of the lower storage area. Simultaneously writing the row display video signal into the (2j-1) th and 2jth rows of the lower screen; and (c) in the first field period, after the step (b), the upper screen and the lower screen. Performing a screen display operation;
(d) in a second field period, output a row display video signal stored in the nth row of the upper storage area and write it in the first row of the upper screen;
The row display video signals stored in the rows (k = 1 to n-1) are output and written simultaneously to the 2kth and (2k + 1) th rows of the upper screen, and then the nth row of the upper storage area is written. And outputs the row display video signal stored in the second screen of the upper screen.
Write to the n-th row, and in parallel, output the row display video signal stored in the n-th row of the upper storage area and write it to the first row of the lower screen.
The row display video signals stored in the rows (k = 1 to n-1) are simultaneously written in the 2kth and (2k + 1) th rows of the lower screen, and then stored in the nth row of the lower storage area. Outputting the displayed row display video signal to the 2nth row of the lower screen, and (e) performing the display operation of the upper screen and the lower screen after the step (d) in the second field period. And in step (b) and step (d), the information corresponding to the display of the first line of the upper screen is set to an undisplayable value (black).

[0010]

<First Embodiment> FIG. 1 is a block diagram showing a main configuration of a PDP device used for an interlace display method in a PDP device according to a first embodiment of the present invention.

The input video signal SV has a vertical resolution of 2n, and each row number having video information of one row is 0.
To (2n-1) can be regarded as signals that are continuously input.

The upper storage area 11 stores 0 to (n-1) row display video signals of the input video signal SV. The lower storage area 12 stores n to (2n-1) of the input video signal SV.
Is stored.

The above-described upper storage area 11 and lower storage area 12 may be arranged in the same memory, or may be arranged and configured using separate memories.

A switch SW2 is provided between the upper storage area 11 and the lower storage area 12 and one input of the AND gate G1, and a switch is provided between the upper storage area 11 and the lower storage area 12 and the lower write driver 3. SW3 is provided.

The switch SW2 outputs the signal "0" /
The upper storage area 11 / lower storage area 12 is connected to one input of the AND gate G1 based on "1". Switch SW
3 connects the lower storage area 12 / upper storage area 11 to the lower write driver 3 based on "0" / "1" of the switching signal SB.

The upper write driver 2 sequentially fetches image information in units of display rows obtained from the output of the AND gate G 1 in synchronization with the control clock SCLK, and fetches the fetched image information above the row number designated by the upper drive circuit 4. Write to screen 1A.

Similarly, the lower write driver 3 sequentially captures image information in units of display rows obtained via the switch SW3 in synchronization with the control clock SCLK, and instructs the captured image information to the lower drive circuit 5. Write to the lower screen 1B of the line number to be executed.

The control circuit 13 outputs the switching signal SB in synchronization with the synchronizing signal SYNC at a timing described later in detail, and determines whether the output of the AND gate G1 is valid / invalid by "1" / "of the display control signal SCP. 0 ", and outputs the drive system control signal SCP to the upper drive circuit 4 and the draft drive circuit 5 to control the operation of the upper drive circuit 4 and the draft drive circuit 5.

The control circuit 13 also controls the upper storage area 11
In addition to controlling the write and read operations of the lower storage area 12, the control clock SCLK is supplied to the upper write driver 2 and the lower write driver 3.

The upper drive circuit 4 selectively activates a scan pulse provided corresponding to each row of the upper screen 1A based on the control clock SCLK and writes the scan pulse to the upper screen 1A.

The lower drive circuit 5 selectively activates a scanning pulse provided corresponding to each row of the lower screen 1B based on the control clock SCLK, and writes the activated scanning pulse on the lower screen 1B.

FIG. 2 shows a PD according to the first embodiment of the present invention.
FIG. 4 is a timing chart showing a method of displaying an interlaced video signal in the P device. FIG. 2 shows a read operation from the upper storage area 11 and the lower storage area 12, and exemplifies the case of 4-bit gradation.

As shown in FIG. 2, the readout period TR is set for each gradation from the upper storage area 11 and the lower storage area 12 by the control circuit 13 in synchronization with the synchronization signal SYNC, and subsequently, light emission is performed for each gradation. (Display) Period T
D0, TD1, TD2, and TD3 exist. In the readout period TR, the first field readout period is T1 and the second field readout period is T2.

In the first field readout period T1, 0, 0, 1, 1, 2, 2, ..., (n-1), (n-
1) The row display video signals are read out in order, and in parallel with this, the video signals n, n, (n + 1), (n + 1),.
The row display video signals are read out in the order of 1) and (2n-1).
Therefore, video signals are read from the upper storage area 11 and the lower storage area 12 in units of 2n display rows.

However, since the display control signal SCP is “0”, the readout period Δt of the video information for the first display row unit in the first field readout period T1 is equal to the upper screen 1A.
Are forcibly set to black (all gradations are "0"), which is a color that cannot be displayed.

During the first field readout period T1, the switching signal SB is "0" and constant, so that all row display video signals read out from the upper storage area 11 via the AND gate G1 are sent to the upper write driver 2. All the row display video signals that are output and read from the lower storage area 12 are output to the lower write driver 3.

Upper storage area 11 and lower storage area 12
In parallel with the read operation from the scan lines L0 to L (2n) based on the control signal from the control circuit 13.
-1), the upper storage area 1 is activated.
The image information of each display row read from the row 1 is written in row numbers 0 to (2n-1) of the upper screen 1A of the PDP 1.

Similarly, based on a control signal from the control circuit 13, the lower drive circuit 4 changes the scanning lines L (2n) to L (4n).
n-1), the video information read out from the lower storage area 12 in units of display rows is displayed on the PDP 1.
Is written to the row numbers 0 to 2n of the lower screen 1B.

For example, when n = 2, as shown in FIG. 3, from the upper storage area 11 side, "1-0", "1-0", "1-1", "1-1" 1
-1 "and read from the lower write area 12 side as" 1-2 "," 1 "as lower PDP write data.
-2 "," 1-3 ", and" 1-3 "in that order, and" 1--1 "is added to row numbers 0 to 3 (display rows 0 to 3) of the upper screen 1A.
0, "1-0", "1-1", "1-1" are written, and "1-2", "1-" are added to row numbers 0 to 3 (display rows 4 to 7) of the lower screen 1B. 2 "," 1-3 ", and" 1-3 "are written.

In the light emission period, the upper screen 1A
Then, the display operation of the lower screen 1B is performed. At this time, since the line display video signal of “1-0” written to the display line 0 is forcibly set to the information indicating black, it is displayed as black on the upper screen 1A and substantially displayed. Not in a state.

In the readout period T2 of the second field,
(N-1), 0, 0, 1, 1,..., (N-2), (n
-2) and (n-1) are read out in order, and in parallel with this, the input signals (2n-1), n, n, (n +) of the input signal of the second field from the lower storage area 12 are read.
1), (n + 1), ..., (2n-2), (2n-
2) The row display video signal is read out in the order of (2n-1).

At this time, the row display video signals of (n-1) and (2n-1) of the second field are read once at the beginning and at the end, and the other row display video signals are successively read twice each. Is read. Therefore, image information is read out from the upper storage area 11 and the lower storage area 12 in units of 2n display rows.

Then, the second field readout period T2
In the readout period Δt for one display row unit of the first row display video signal, the switching signal SB is set to “1” and the (n−1) row display video signal read from the upper storage area 11 is written to the lower write driver. 3 and the lower storage area 1
An upper / lower exchange operation of outputting the (2n-1) row display video signal read from the second write driver 2 to the upper write driver 2 is performed.

At the same time, since the display control signal SCP is “0”, the readout period Δt of the video information for the first display row unit in the second field readout period T2 is equal to the AND gate G.
The (2n-1) row display video signal output to one input of the first is forcibly set to information indicating black and AND
Output from the gate G1.

Thereafter, since the switching signal SB is again "0" and the display control signal SCP is "1" and stabilized, all the row display video signals read from the upper storage area 11 via the AND gate G1 are all written to the upper write driver. Output to 2,
All the row display video signals read from the lower storage area 12 are output to the lower write driver 3.

Upper storage area 11 and lower storage area 12
In parallel with the read operation, the upper drive circuit 4 scans the scanning lines L0 to L (2n−) based on the control signal from the control circuit 13.
By being activated in the order of 1), the data is written to the display rows 0 to (2n-1) of the upper screen 1A of the PDP 1.

Similarly, based on a control signal from the control circuit 13, the lower drive circuit 5 causes the scanning lines L (2n) to L (4n)
By being activated in the order of -1), the data is written to the display rows 2n to (4n-1) of the lower screen 1B of the PDP 1.

For example, when n = 2, the upper storage area 11
From the side, “2-1”, “2-0”, “2-0”, “2-
1 ”and“ 2 ”from the lower storage area 12 side.
-3 "," 2-2 "," 2-2 "," 2-3 ", and the first" 2-1 "from the upper storage area 11 and the first" 2-1 "from the lower storage area 12. Since the vertical exchange operation as described above is performed between “2-3”, the upper screen 1A
The line numbers 0 to 3 (display lines 0 to 3) have "2-3" and "2
−0 ”,“ 2-0 ”, and“ 2-1 ”are written, and“ 2--0 ”is displayed in row numbers 0 to 3 (display rows 4 to 7) of the lower screen 1B.
1 "," 2-2 "," 2-2 "," 2-3 "are written.

In the light emission period, the upper screen 1A
Then, the display operation of the lower screen 1B is performed. At this time, since the image information of “2-3” written in the display row 0 is forcibly set to the information indicating black, the upper screen 1
In A, it is displayed as black, and is in a state of not being displayed substantially.

Table 1 shows a generalized PDP write operation of the first and second fields in the interlace operation of the first embodiment. Table 1 shows the order of operation during normal non-interlace for comparison and reference.

[0041]

[Table 1]

As described above, according to the display method of the first embodiment, even when a video signal having a low vertical resolution is input, the vertical resolution is not degraded, and a sense of incongruity can be obtained even for a fast moving image. A missing display image can be displayed on the PDP 1. In addition, an appropriate image can be displayed even at the boundary between the upper screen 1A and the lower screen 1B.

Also, the PDP is controlled by the display control signal SCP.
Since the display of the display row 0 of 1 is controlled to be always black, the image quality of the image displayed by the vertical exchange operation does not deteriorate.

As a result, good image quality display can be realized even when the PDP 1 is driven independently by the upper screen 1A and the lower screen 1B.

<Embodiment 2> FIG. 5 is a timing chart showing a method of writing to PDP 1 in an interlaced display method according to Embodiment 2 of the present invention.
The write timing order to P is shown. The configuration of the PDP device used in the second embodiment is the same as that of the first embodiment shown in FIG. 1, and the write and read timings of the upper storage area 11 and the lower storage area 12 are the same as in the first embodiment. As shown. FIG. 5 shows the timing of writing to the upper screen 1A and the lower screen 1B when n = 2.

The method of displaying an interlaced video signal according to the second embodiment is as follows. In the first field readout period T1, the row display video is displayed in the order of 0, 1, 2,... The signals are read out, and in parallel with this, n, (n + 1), (n + 2),
.., (2n−1) are read out in the order of the row display video signal. At this time, the row display video signal is read only once. Therefore, the upper storage area 11 and the lower storage area 1
The row display video signal is read out every 2 to n scan line units.

At this time, since the switching signal SB is "0" and constant, all the row display video signals read from the upper storage area 11 are output to the upper write driver 2, and the row display video signals read from the lower storage area 12 are read. All video signals are output to the lower write driver 3.

However, since the display control signal SCP is "L" in the readout period .DELTA.t of the image information for the first display row unit in the first field readout period T1, the image information of the uppermost scanning line of the upper screen 1A is The information is forcibly set to indicate black.

In parallel with the read operation from the upper storage area 11 and the lower storage area 12, as shown in Table 1, based on the control signal from the control circuit 13, the upper drive circuit 4
= 0 to (n-1) in order of two scanning lines L (2i) and L (2i).
By simultaneously activating (2i + 1), the image information of each display row read from the upper storage area 11 via the AND gate G1 is written to the row numbers 0 to (2n-1) of the upper screen 1A of the PDP 1. It is.

Similarly, as shown in Table 1, based on the control signal from the control circuit 13, the lower drive circuit 5
To (2n-1) in order of two scanning lines L (2i) and L (2i).
By simultaneously activating (2i + 1), the image information of each scanning line read from the lower storage area 12 becomes P
The data is written to row numbers 0 to (2n-1) (display rows 2n to (4n-1)) of the lower screen 1B of DP1.

Specifically, as shown in FIG. 5, during the first field read period T1, "1-0" and "1-1" are read from the upper storage area 11 in this order, and the lower storage area 12 is read. From the side, "1-2", "1-3" are read in this order, and "1-0", "1-0", "1-0" are displayed in row numbers 0-3 (display rows 0-3) of the upper screen 1A. 1-1 "and" 1-1 "are written, and row numbers 0 to 3 (display rows 4 to
7), “1-2”, “1-2”, “1-3”, “1-
3 "are written in this order.

In the light emission period, the upper screen 1A
Then, the display operation of the lower screen 1B is performed. At this time, since the image information “1-0” written in the display row 0 is forcibly set to the information indicating black, the upper screen 1
In A, it is displayed as black, and is in a state of not being displayed substantially.

In the second field readout period T2, (n−1), 0, 1,...
, (N-1), and read out the row display video signals in the order of (n-1).
1), n, (n + 1),..., (2n-1) are read out in this order. At this time, the row display video signals of (n-1) and (2n-1) are read once each at the beginning and end, and each other is read only once.

Therefore, (n + 1) times of image information for each display row are read from the upper storage area 11 and the lower storage area 12, respectively.

Then, the second field readout period T2
In the readout period Δt of the image information for the first display row unit, the switching signal SB is set to “1” and the upper storage area 1
1 is output to the lower write driver 3 and the (2n-1) row display video signal read from the lower storage area 12 is written to the upper side via the AND gate G1. The upper and lower exchange operation of outputting to the driver 2 is performed.

At the same time, the second field readout period T2
During the readout period Δt of the image information for the first display row unit, the display control signal SCP is “0”, so the AND gate G1
The (2n-1) row display video signal output to one input is forcibly set to "0" (black) and output from the AND gate G1.

Thereafter, since the switching signal SB is again "0" and the display control signal SCP is "1" and stabilized, all the image information read from the upper storage area 11 is output to the upper write driver 2 and the lower storage area. All of the image information read from 12 is output to the lower write driver 3.

Upper storage area 11 and lower storage area 12
In parallel with the read operation from, the upper drive circuit 4 first activates the scanning line L0 based on the control signal from the control circuit 13, and thereafter, the two lines in the order of i = 1 to (n-1) By simultaneously activating the scanning lines L (2i-1) and L (2i) and activating the last scanning line L (2n-1), the row display video signal is changed to the row number of the upper screen 1A of the PDP1. It is written to 0 (2n-1).

Similarly, based on the control signal from the control circuit 13, the lower drive circuit 5 first activates the scanning line L (2n), and thereafter, i = (n + 1) to (2n-1). Simultaneously activates the two scanning lines L (2i-1) and L (2i), and activates the last scanning line L (4n-1), so that the row display video signal changes to the lower screen of the PDP1. 1B row numbers 0 to (2n-1) (display rows 2n to (4n
-1)) is written.

More specifically, as shown in FIG. 5, "2-1", "2-0", "2-1" from the upper storage area 11 side.
, And from the lower storage area 12 side, “2-
3 "," 2-2 ", and" 2-3 ", and the first" 2-1 "from the upper storage area 11 and the lower storage area 1
Since the upper / lower exchange operation is performed in the same manner as described above between the first and second “2-3” from “2” to “2-3”, writing to the PDP 1 is performed as shown in the upper PDP write data and the lower PDP write data in FIG. Line number 0 of upper screen 1A
2 to 3 (display rows 0 to 3), “2-3”, “2-0”, “2
−0 ”and“ 2-1 ”are written, and“ 2-1 ”,“ 2-2 ”, and“ 2-2 ”are displayed in row numbers 0 to 3 (display rows 4 to 7) of the lower screen 1B.
Data is written in the order of “2-2” and “2-3”.

In the light emission period, the upper screen 1A
Then, the display operation of the lower screen 1B is performed. At this time, since the image information of “2-3” written in the display row 0 is forcibly set to the information indicating black, the upper screen 1
In A, it is displayed as black, and is in a state of not being displayed substantially.

As described above, the method of displaying an interlaced video signal according to the second embodiment is based on the second field readout period T.
2, since only the (n−1) and (2n−1) row display video signals from the upper storage area 11 and the lower storage area 12 are read once, the first field readout period T1 and the second field readout period Any of T2 can be shortened as compared with the first embodiment.

As a result, the period during which writing and display are not performed can be set long, so that a pseudo contour of a moving image can be suppressed.

Since the interlaced display method according to the second embodiment has all the features of the first embodiment, it is needless to say that all the effects described in the first embodiment can be achieved.

<Others> In the first and second embodiments, the display line 0 of the PDP 1 is forcibly displayed in black and the interlace display is performed. Row (4n-1) may also be configured to forcibly display black.

[0066]

As described above, in the display method according to the first aspect of the present invention, most of the scanning lines are displayed on the display screen by shifting two consecutive line display video signals by one line in the vertical direction. Since it is displayed, the vertical resolution does not deteriorate much.

Further, an appropriate image can be displayed even at the boundary between the divided upper screen and lower screen. Further, the first row of the display screen is equivalent to a state in which the first row is not always displayed, so that good image quality can be maintained without displaying an unnatural image on the display screen.

In the display method according to the second aspect of the present invention, since both the first field readout period and the second field readout period can be shortened, the period during which neither writing nor display is performed can be set longer. ,
It is possible to make the pseudo contour of the moving image difficult to appear.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a PDP device used in an interlaced display method according to Embodiments 1 and 2 of the present invention.

FIG. 2 is a timing chart showing a part of an interlace operation according to the first and second embodiments.

FIG. 3 is a timing chart showing a specific example of an interlace operation according to the first embodiment;

FIG. 4 is an explanatory diagram showing effects of the first embodiment.

FIG. 5 is a timing chart showing a specific example of an interlace operation according to the second embodiment.

FIG. 6 is an explanatory diagram showing a configuration of a PDP in which a screen is divided into two.

FIG. 7 is an explanatory diagram showing the concept of an interlaced video signal.

[Explanation of symbols]

1 PDP, 2 upper write driver, 3 lower write driver, 4 upper drive circuit, 5 lower drive circuit, 11 upper memory, 12 lower memory, 13 control circuit, G1
AND gate, SW1 to SW3 switches.

Claims (2)

[Claims] 1. An interlaced input image is displayed on a display screen using a display device having a display screen capable of displaying first to fourth n-th rows (n is a natural number) constituted by an upper screen and a lower screen. The upper screen performs line display of the first to second n-th lines of the display screen based on image information stored in an upper storage area, and the lower screen displays the first screen of the display screen. (2n + 1) -th to (4n) -th rows are displayed based on the image information stored in the lower storage area, and the input video signal is a first to a 2n-th row each indicating one row of image information. (A) storing the first to n-th row display video signals in the first to n-th rows of the upper storage area, and selecting the (n + 1) to 2n-th rows Display video signals for the first row of the lower storage area
(B) outputting the row display video signals stored in the j-th row (j = 1 to n) of the upper storage area twice in the first field period; And the (2j-1) -th row and the second
The row display video signal stored in the j-th row of the lower storage area is output twice, and the (2j-1) -th row and the 2j-th row of the lower screen are output in parallel. And (c) in the first field period,
(b) performing a display operation of the upper screen and the lower screen after (b) outputting a row display video signal stored in the nth row of the lower storage area during a second field period; Write to the first line of the upper screen, and then write the k-th of the upper storage area
The row display video signals stored for the rows (k = 1 to n-1) are output twice, and the 2nd row and the (2k +
1) writing sequentially to the row, and then outputting a row display video signal stored in the nth row of the upper storage area and writing it to the 2nth row of the upper screen; Output the row display video signal stored in the nth row and write it in the first row of the lower screen, and then the kth row (k = 1 to n) of the lower storage area
The row display video signal stored in -1) is output twice, and is sequentially written in the 2kth row and the (2k + 1) th row of the lower screen, and subsequently stored in the nth row of the lower storage area. Outputting a row display video signal and writing the row display video signal in a second n-th row of the lower screen; and (e) in the second field period,
(d) performing a display operation of the upper screen and the lower screen after the (d), in the step (b) and the step (d), the information corresponding to the display of the first line of the upper screen An interlaced display method characterized by setting a non-displayable value (black). 2. An interlaced input image is displayed on a display screen using a display device having a display screen capable of displaying first to fourth n-th rows (n is a natural number) constituted by an upper screen and a lower screen. The upper screen performs line display of the first to second n-th lines of the display screen based on image information stored in an upper storage area, and the lower screen displays the first screen of the display screen. (2n + 1) -th to (4n) -th rows are displayed based on the image information stored in the lower storage area, and the input video signal is a first to a 2n-th row each indicating one row of image information. (A) storing the first to n-th row display video signals in the first to n-th rows of the lower storage area, and setting the (n + 1) to 2n-th rows Display video signals for the first row of the lower storage area
(B) storing the row display video signals stored in the j-th row (j = 1 to n) of the upper storage area in the first field period during the first field period; At the same time, the row display video signals stored in the j-th row of the lower storage area are written into the (2j-1) -th row and the 2j-th row at the same time. And writing simultaneously to the 2j-th row; and (c) in the first field period,
(b) performing the display operation of the upper screen and the lower screen after (b), and (d) outputting a row display video signal stored in the nth row of the upper storage area during a second field period. Write to the first line of the upper screen, and then write the k-th of the upper storage area
The row display video signals stored in the rows (k = 1 to n-1) are output and written simultaneously to the 2kth and (2k + 1) th rows of the upper screen, and then the nth row of the upper storage area is written. And outputs the row display video signal stored in the second screen of the upper screen.
Write to the n-th row, and in parallel with this, output the row display video signal stored in the n-th row of the upper storage area and write it to the first row of the lower screen, and then write the k-th row of the lower storage area. Lines (k = 1 to n
-1) The row display video signal stored in the lower screen is simultaneously written to the 2kth row and the (2k + 1) th row of the lower screen, and then the row display video signal stored in the nth row of the lower storage area is output. (E) writing in the second n-th row of the lower screen;
(d) performing a display operation of the upper screen and the lower screen after the (d), in the step (b) and the step (d), information corresponding to the display of the first line of the upper screen An interlaced display method characterized by setting a non-displayable value (black).