JPH1127600A - Multiscreen display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To the multiscreen display device in which a read/write overtake line is unremarkably displayed so as to be inconspicuous in the multiscreen display for plural input dynamic image signals whose synchronization signals have phases and periods which are slightly different from each other. SOLUTION: This display device is provided with a vertical read timing pulse means, that generates a vertical read timing pulse signal whose period differs from the period of a vertical synchronization signal of an input dynamic image signal by an integral multiple or one divided by the integer. Furthermore, an image data storage reproduction section 7 is made up of a synchronizing separator section 2, that separates and outputs a vertical synchronization signal and a horizontal synchronization signal from the received dynamic image signal, a timing pulse generating section 3 that generates a memory write pulse which is phase-locked with the vertical synchronization signal and the horizontal synchronization signal, a memory write control section 4 that converts the input analog dynamic image signal into digital image data and applies write control of the digital image data to a designated area of a memory 5, the memory 5 that stores the digital image data, and a memory read control section 6 that applies the read control of the digital image data stored in the memory 5 by a read pulse the period of which differs from that of the memory white pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PDP (Plazma Displa).
y Panel) and other matrix driven video devices.
The present invention relates to multi-screen display control for displaying a plurality of moving images on one screen.

[0002]

2. Description of the Related Art As shown in FIG. 2, in a conventional multi-screen display device, input moving image signals 1a, 1a from a plurality of moving image signal sources are provided.
, 1n are written and stored as digital image data in a plurality of memories 5 by the memory cell and the control unit 4 for each input moving image signal. The stored image data is read out by the memory read control unit 6 and input to the synthesizing circuit 10. A plurality of input image data is synthesized by a synthesizing circuit 10 into a multi-screen display image signal as shown in FIG. The matrix type display unit 14 is driven by a synchronization signal phase-locked to the input moving image signal, and outputs and displays a multi-screen.

An image data storage / reproduction unit 7a for writing and reading image data includes a synchronization separation unit 2 for separating and outputting a vertical and horizontal synchronizing signal from an input moving image signal, and the memory synchronized with a vertical and horizontal synchronizing signal. A timing pulse generator 3 for generating a pulse for writing, a memory write controller 4 having means for converting an input analog moving image signal into digital image data and writing and controlling the digital image data in a designated section of the memory 8; It is controlled by a memory 8 for storing digital image data and a memory read control 6 for reading out the digital image data stored in the memory 8 with a read pulse synchronized with a memory write pulse. In general, the read pulse is phase-synchronized with any one of a plurality of input video signals slightly different from the synchronization phase and period. Therefore, in the read image of another input moving image signal, a read / write reversal phenomenon (a so-called overtaking line) occurs as shown in FIG. This overtaking location has a slightly different synchronization phase and synchronization cycle for each input moving image signal, so that a fixed discontinuous portion is displayed and output on a part of each screen, which is more noticeable. A point occurs. On the other hand, in order to prevent the occurrence of the overtaking line, it is necessary to perform external synchronization phase control for each input moving image signal, but this is not economical in a device that performs a large number of multi-screen displays.

[0004]

SUMMARY OF THE INVENTION In view of these problems, the present invention relates to a multi-screen display of a plurality of input video signals having slightly different synchronization phases and synchronization periods.
It is an object of the present invention to propose a display device that displays a passing line of a light in an inconspicuous manner.

[0005]

In a multi-screen display device having an image data storage / reproduction unit for reading and outputting a plurality of digital image data and a synthesizing circuit for synthesizing and outputting the digital image data, an input moving image signal is provided. Is provided with a vertical read timing pulse means having a cycle different from an integral multiple or a fraction of an integer of the vertical cycle. A synchronization separation unit configured to separate and output a vertical and horizontal synchronization signal from the input moving image signal; a timing pulse generation unit configured to generate a pulse in memory writing phase-synchronized with the vertical and horizontal synchronization signal; Means for converting an input analog moving image signal into digital image data, a memory write control unit for controlling writing of the digital image data in a designated section of the memory, a memory for storing the digital image data, and a digital image data stored in the memory. It is composed of a memory write pulse and a memory read control that performs read control with a read pulse having a different cycle. Further, the vertical read timing pulse means is a timing pulse generator (R) for generating a memory read control sampling clock, a horizontal pulse and a vertical pulse synchronized with a pulse signal from the vertical timing generator. Further, the vertical timing generating means
The internal oscillator oscillates at an arbitrary frequency, and the cycle of the internal oscillator is such that the overtaking lines for writing and reading on the display output screen are fixed.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory read control sampling clock, horizontal pulse and vertical pulse are signals having a period different from the vertical period of an input moving image signal by an integral multiple or a fraction of an integral number, and the writing of a display output screen is performed. The period is set such that the read overtaking line is a fixed display. Further, the vertical timing generating means is selected by m / n of the vertical synchronizing signal period of an arbitrary input moving image signal or an internal oscillator, so that the overtaking lines for writing and reading of the display output screen are fixed. I do.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (a) is a block diagram of a main part of an embodiment according to the present invention, (b) is a block diagram of a selection circuit of a vertical timing generating means, and FIG. 3 is a multi-screen display example according to the prior art and the present invention. . In FIG. 1, reference numerals 1a, 1b, and 1n denote a plurality of input video signals, 2 denotes a synchronization separation unit that separates and outputs vertical and horizontal synchronization signals from the input video signal, and 3 denotes a memory write phase-synchronized with the vertical and horizontal synchronization signals. It is a timing pulse generator for generating a pulse. Reference numeral 4 denotes a memory write control unit which has means for converting an input analog moving image signal into digital image data and controls writing of the digital image data in a designated section of the memory; 5, a memory for storing digital image data; Read control unit 7a, 7b, 7 for reading out the read digital image data with a read pulse having a cycle different from that of the memory write pulse
Reference numeral n denotes an image data storage / reproduction unit that stores, reads, and reproduces a plurality of digital image data. Reference numeral 8 denotes a sampling clock for memory read control synchronized with a pulse signal from the vertical timing generator, a timing pulse generator (R) for generating horizontal and vertical pulses, or an integral multiple or an integer of the vertical period of the input moving image signal. A sampling pulse for memory read control having a different cycle, a timing pulse generating (R) section for generating horizontal and vertical pulses, 9 an internal oscillator, 10 a synthesizing circuit for synthesizing and outputting a plurality of digital image data, Reference numeral 12 denotes a synchronization separation unit, 13 denotes one of the input moving image signals, and S1 denotes a switch.
Reference numeral 14 denotes a matrix type display unit such as a PDP.

The embodiment is composed of the above elements, and the detailed operation will be described below along the signal flow. The plurality of input moving image signals 1a, 1b,... 1n are input to the corresponding image data storage / reproduction units 7a, 7b,. The following description focuses on 7a. Input video signal 1
a is separated and output into a vertical synchronizing signal and a horizontal synchronizing signal by the synchronizing separation unit 2. A sampling pulse CL for writing which is phase-synchronized with the input moving image signal 1a by a timing pulse generator 3 including a PLL (Phase Lock Loop) circuit, a VCO (Voltage Controlled Oscilater) and a frequency divider.
K, a horizontal pulse H, and a vertical pulse V are generated.

The memory write control unit 4 has an A / D
(Analog / digital converter) and a memory control unit. The input moving image signal 1a is converted into digital image data by A / D driven by the writing sampling clock CLK, and is converted into digital image data.
Thus, the data is continuously and cyclically written and stored in the memory 5. This means that when one field or one frame of memory is full, new image data is written while discarding old image data sequentially from the beginning of the memory. Means that discontinuous image data is generated in the section.

The timing pulse generator (R) 8 generates a sampling clock CLKr, a horizontal pulse Hr, a vertical pulse Vr, and the like for controlling the memory read controller 6 and supplies them to the memory read controller 6.
The image data stored in the memory 5 is read by the memory read control unit 6, input to the synthesizing circuit 10, and synthesized and output as a multi-screen signal. Readout vertical pulse V
Since r and the writing vertical pulse V have different periods and phases, the image data read from the memory 5 becomes the discontinuous image data, and the overtaking line as shown in FIG. Generate. Read vertical pulse Vr
And the period of the vertical pulse V for writing is the same or close,
The displayed overtaking line is displayed at a fixed position on the screen or in a state of slowly moving, which is very obstructive to the viewer.

In order to alleviate this phenomenon, the overtaking line is not displayed at a certain place, and the display position is moved at a speed that is not obstructive. The first means is provided with an internal oscillator 9 and oscillates a reference signal having a period 10% earlier or later than the period of the write vertical pulse V, and generates a timing pulse (R).
Supply to section 8. The timing pulse generator (R) 8 generates a read vertical pulse Vr synchronized with the reference signal and supplies the read vertical pulse Vr to the memory read controller 6. The second means is provided with a sync separation section 12 for separating a vertical sync signal of one input video signal 13 and supplying the separated vertical sync signal to a timing pulse generation (R) section 8. The timing pulse generator (R) 8 used in the second means is composed of a PLL, a VOC, and a frequency divider.
The frequency division ratio of the frequency divider is set so that the reading vertical pulse Vr and the writing vertical pulse V can be synchronized at a rate of once every ten times by the PLL. Therefore, the cycle of the read vertical pulse Vr is different from the cycle of the write vertical pulse V by 10%. In the third means, as shown in FIG. 1 (b), a switch S1 is additionally installed, and the first means and the second means can be selectively used.

[0011]

The present invention is embodied in the form described above and has the following effects. The memory read control sampling clock, horizontal pulse and vertical pulse
A signal having a period different from the vertical period of the input moving image signal by an integer multiple or a fraction of an integer, or the vertical timing generating means is set to m / m of the vertical synchronizing signal period of an arbitrary input moving image signal.
n (m and n are arbitrary integers, m / n is not an integral multiple or a fraction of an integer) or a means for selecting an internal oscillator, if the overtaking line portion of writing and reading of the display output screen is a fixed display. By doing so, the display of the unsightly passing line portion can be made inconspicuous.

[Brief description of the drawings]

FIG. 1A is a block diagram of a main part of a multi-screen display device according to an embodiment of the present invention, and FIG. 1B is a block diagram of a selection circuit of a vertical timing generator.

FIG. 2 is a block diagram of a main part of a conventional multi-screen display device.

3A is an example of a multi-screen display according to the related art and the present invention, and FIG. 3B is an example of an overtaking line display.

[Explanation of symbols]

 1a, 1b, 1n Input moving image signal 2, 12, Sync separation unit 3, Timing pulse generation unit 4, Memory write control unit 5, Memory 6, Memory read control unit 7a, 7b, 7n Image data storage / reproduction unit 8 Timing pulse generation (R) unit 9 Internal oscillator 10 Synthesis circuit S1 Switch

Claims (6)

[Claims] 1. A matrix type display unit capable of displaying horizontal and vertical drive signals of an arbitrary period, and input video signals from a plurality of video signal sources are stored as digital image data in a plurality of memories for each of the input video signals. An image data storage / reproducing unit that stores and reads and outputs the plurality of digital image data; and a combining circuit that combines the digital image data and outputs a multi-screen signal. Digital image data is read out and output from the memory by a vertical read timing pulse generating means having a period different from the vertical synchronization period by an integral multiple or a fraction of an integer, and a passing line for writing and reading on the display output screen is fixedly displayed. A multi-screen display device, characterized in that it does not become unusual. 2. The image data storage / reproduction section separates and outputs a vertical and horizontal synchronizing signal from an input moving image signal, and generates a pulse in the memory writing phase-synchronized with the vertical and horizontal synchronizing signal. A timing pulse generator, a memory write controller having means for converting the analog input moving image signal into digital image data, and writing and controlling the digital image data in a specified section of a memory described later, and storing the digital image data Memory and
2. The multi-screen display device according to claim 1, further comprising a memory read control unit that controls reading of the digital image data stored in the memory with a read pulse having a cycle different from that of the memory write pulse. 3. The vertical read timing pulse means is a timing pulse generator (R) for generating the memory read control sampling clock, horizontal pulse and vertical pulse synchronized with a pulse signal from the vertical timing generator. The multi-screen display device according to claim 1, wherein: 4. The vertical timing generating means is an internal oscillator that oscillates at an arbitrary frequency, and the signal period of the internal oscillator is determined by the overwriting line for writing and reading on the display output screen. 2. The multi-screen display device according to claim 1, wherein the period is set as follows. 5. A synchronizing separation section is additionally provided at a stage preceding the timing pulse generating section (R), and the timing pulse generating section (R) is provided with m / n (m / n) of a vertical synchronizing signal cycle of the arbitrary input moving image signal. (m and n are arbitrary integers, and m / n is not an integral multiple or 1 / integer). The memory read control timing pulse is generated, and the overwriting lines for writing and reading of the display output screen are fixed. 2. The multi-screen display device according to claim 1, wherein the display has a cycle similar to that of the display. 6. A switch for selecting a plurality of vertical timing generators at a stage preceding said timing pulse generator (R).
The internal oscillator and a synchronization separation unit that separates and outputs a vertical synchronization signal of the arbitrary input video signal are additionally installed, and the timing pulse generation unit (R) selects and inputs the plurality of vertical timing generation units. Generating the memory read control timing pulse of m / n of the vertical synchronizing signal period of the arbitrary input moving image signal, so that the overwriting line portion of writing and reading of the display output screen becomes a fixed display. 2. The multi-screen display device according to claim 1, wherein the period is a period.