JPH11274730A - Manufacture of multilayer printed wiring board - Google Patents

Manufacture of multilayer printed wiring board

Info

Publication number
JPH11274730A
JPH11274730A JP7939298A JP7939298A JPH11274730A JP H11274730 A JPH11274730 A JP H11274730A JP 7939298 A JP7939298 A JP 7939298A JP 7939298 A JP7939298 A JP 7939298A JP H11274730 A JPH11274730 A JP H11274730A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
hole
resin
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7939298A
Other languages
Japanese (ja)
Other versions
JP3012590B2 (en
Inventor
Yasuji Furui
靖二 古井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Toppan Circuit Solutions Toyama Inc
Original Assignee
NEC Toppan Circuit Solutions Toyama Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Toppan Circuit Solutions Toyama Inc filed Critical NEC Toppan Circuit Solutions Toyama Inc
Priority to JP7939298A priority Critical patent/JP3012590B2/en
Publication of JPH11274730A publication Critical patent/JPH11274730A/en
Application granted granted Critical
Publication of JP3012590B2 publication Critical patent/JP3012590B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a high density multilayer printed wiring board which has a via hole on a conduction through hole (hereinafter called IVH) formed in a laminate which will serve as a core. SOLUTION: An IVH 3 of a laminate 1 which is formed with a first plating layer 4 and has the conduction through hole (IVH 3) is filled with resin filler 5. After that, the resin filler 5 is etched by a desired depth to form a recessed resin etched section 6. In this recessed resin etched section 6, a via hole concentrical with the IVH 3 and connected to the IVH 3 is formed on the IVH 3 by forming a conductor layer by filling the recessed section 6 with plating or conductive paste and then building up photosensitive resin and plating on the layer 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は多層印刷配線板の製
造方法に関し、特にビルドアップ法による多層印刷配線
板の製造方法に関する。
The present invention relates to a method of manufacturing a multilayer printed wiring board, and more particularly to a method of manufacturing a multilayer printed wiring board by a build-up method.

【0002】[0002]

【従来の技術】ビルドアップ法を用いた多層印刷配線板
の製造方法においては表裏の導通を得るためにコアとな
る積層板に導通スルーホール(以下、IVHという)を
設け、このIVHに樹脂を充填するのが一般的である。
該IVHと上層の回路との導通を得るためには、IVH
の樹脂上には導体回路が無いため、該当のIVHのラン
ドを延長するか、IVHと上層の接続ランドを導体回路
でつなぐ方法が採用されている。
2. Description of the Related Art In a method of manufacturing a multilayer printed wiring board using a build-up method, conductive through holes (hereinafter, referred to as IVH) are provided in a laminated board serving as a core in order to obtain front-to-back conduction, and resin is applied to the IVH. It is common to fill.
In order to obtain conduction between the IVH and the circuit in the upper layer, the IVH
Since there is no conductive circuit on the resin, there is adopted a method of extending the corresponding land of the IVH or connecting the IVH and the upper connection land with a conductive circuit.

【0003】これらの方法では回路の高密度化に制限が
あるために、IVH上に導体回路を形成する方法が特開
平5―82945号公報や特開平6―275959号公
報に開示されている。以下に、これらの方法について図
4、図5を参照して説明する。まず、図4(a)に示す
ように銅箔2を張り付けた積層板1に貫通孔3aをドリ
ル加工やパンチング加工等により形成する。次に図4
(b)に示すようにこの積層板1の表面および貫通孔3
aをめっき処理する。積層板1および貫通孔には第1の
めっき層4が形成される。めっき処理され導通化された
貫通孔をIVH3と呼ぶ。
[0003] In these methods, since there is a limit in increasing the density of the circuit, a method of forming a conductor circuit on an IVH is disclosed in Japanese Patent Application Laid-Open Nos. 5-82945 and 6-275959. Hereinafter, these methods will be described with reference to FIGS. First, as shown in FIG. 4A, a through hole 3a is formed in a laminated plate 1 on which a copper foil 2 is adhered by drilling, punching, or the like. Next, FIG.
As shown in (b), the surface of the laminate 1 and the through holes 3
a is plated. A first plating layer 4 is formed in the laminate 1 and the through holes. The plated through hole that is rendered conductive is referred to as IVH3.

【0004】次に図4(c)に示すようにIVH3内に
穴埋め樹脂5を充填してIVH3を穴埋めした後、図4
(d)に示すように再度めっき処理を行い、穴埋め樹脂
5の表面並びにIVH第1のめっき層4表面に第2のめ
っき層7を形成する。
[0004] Next, as shown in FIG. 4 (c), after filling the filling resin 5 into the IVH 3 and filling the IVH 3, FIG.
As shown in (d), the plating process is performed again to form the second plating layer 7 on the surface of the filling resin 5 and the surface of the IVH first plating layer 4.

【0005】次いで、図4(e)に示すように公知のド
ライフィフィルム法や電着レジスト法等により積層板表
面の第1のめっき層4,7と銅箔2をエッチングして内
層導体回路9とIVH3上に導体ランド10を有する内
層印刷配線板11が得られる。
Next, as shown in FIG. 4 (e), the first plating layers 4 and 7 and the copper foil 2 on the surface of the laminated board are etched by a known dry film method or an electrodeposition resist method or the like to form an inner conductor circuit. 9 and the inner printed wiring board 11 having the conductor land 10 on the IVH 3 are obtained.

【0006】その後、図5(f)に示すように公知のビ
ルドアップ法により、感光性絶縁樹脂12を内層印刷配
線板11の表面に塗布した後、フォト法又はレーザー法
等によりビアホール13を形成する。その際IVH3上
には導体ランド10があるためにIVH3の同軸上にビ
アホール13を形成することができる(図5(g))。
Thereafter, as shown in FIG. 5F, a photosensitive insulating resin 12 is applied to the surface of the inner printed wiring board 11 by a known build-up method, and then a via hole 13 is formed by a photo method or a laser method. I do. At this time, since the conductor land 10 is present on the IVH 3, the via hole 13 can be formed coaxially with the IVH 3 (FIG. 5G).

【0007】次に、感光性絶縁樹脂12の表面にめっき
処理を施し、第2のめっき層14を形成し、回路形成を
行うことで多層印刷配線板15が製造される(図5
(i))。
Next, a plating process is performed on the surface of the photosensitive insulating resin 12, a second plating layer 14 is formed, and a circuit is formed to manufacture a multilayer printed wiring board 15 (FIG. 5).
(I)).

【0008】[0008]

【発明が解決しようとする課題】しかしながらこのよう
にして得られた多層印刷配線板15は以下のような問題
点を有している。
However, the multilayer printed wiring board 15 thus obtained has the following problems.

【0009】まず第一に、この多層印刷配線板15は、
特に内層回路の微細線化が難しいことである。その理由
はIVH3上に導体ランド10を設けるためめっき処理
を2回実施していることから、導体厚の厚みは、銅箔2
の厚み(通常12〜18μm)、第1のめっき層4の厚み
(約20μm)と第2のめっき層7の厚み(20μm)を合
計した50μm以上の厚さとなり、エッチング時間の増
加に伴い、内層導体回路9並びに導体ランド10の側面
のサイドエッチング量が増え、回路形成の解像度が悪く
なり、微細回路を形成することが難しくなるからであ
る。
First, this multilayer printed wiring board 15
In particular, it is difficult to make the inner layer circuit finer. The reason is that the plating process is performed twice in order to provide the conductor land 10 on the IVH 3.
Thickness (normally 12 to 18 μm), thickness of the first plating layer 4
(Approximately 20 μm) and the thickness of the second plating layer 7 (20 μm), the total thickness is 50 μm or more. As the etching time increases, the amount of side etching on the side surfaces of the inner conductor circuit 9 and the conductor land 10 increases. This is because the resolution of circuit formation deteriorates and it becomes difficult to form a fine circuit.

【0010】微細回路形成を考えた場合、2回目の第2
のめっき層7を薄くつけるか、特開平5―175653
号公報に開示されているように、めっき後エッチング処
理を行い、導体層の薄化することが考えられるが、この
場合はIVH3上の導体層も同様に薄くなるために同軸
に形成するビアホール13とIVH3の接続信頼性が低
下する問題点があった。
Considering the formation of a fine circuit, the second
The plating layer 7 is thinly applied.
As disclosed in Japanese Patent Application Laid-Open Publication No. H11-107, it is conceivable to perform an etching process after plating to reduce the thickness of the conductor layer. In this case, since the conductor layer on the IVH 3 is similarly thinned, a via hole 13 formed coaxially is used. And the connection reliability of the IVH3 is reduced.

【0011】本発明は上記の問題点を解決し、IVHの
同軸上にビアホールを形成出来るとともに、微細回路形
成も可能となる高密度な多層印刷配線板の製造方法を提
供することにある。
An object of the present invention is to provide a method for manufacturing a high-density multilayer printed wiring board which can solve the above problems and can form a via hole coaxially with an IVH and can also form a fine circuit.

【0012】[0012]

【課題を解決するための手段】本発明の多層印刷配線板
の製造方法は、両面に銅箔を有する積層板に貫通孔を形
成する工程と、前記貫通孔を含む前記積層板表面に第1
のめっき層を形成する工程と、前記第1のめっき層を形
成した前記貫通孔(以下、IVHという)に穴埋め樹脂
を充填する工程と、前記IVH中の前記穴埋め樹脂を所
望の深さエッチングし前記IVHに凹部を形成する工程
と、前記凹部に導電体層を形成する工程と、前記第1の
めっき層をエッチングし前記積層板表面に内層導体回路
と前記IVH表面に導体ランドを有する内層印刷配線板
を形成する工程と、前記内層印刷配線板表面に絶縁樹脂
を被覆する工程と、前記IVH上の前記絶縁樹脂に前記
IVHの前記凹部の前記導電体層が露出するようにビア
ホールを形成する工程と、前記ビアホールを含む前記絶
縁樹脂の表面に第2のめっき層を形成する工程とを含む
ことを特徴とする。
According to the present invention, there is provided a method for manufacturing a multilayer printed wiring board, comprising the steps of: forming a through hole in a laminate having copper foil on both sides;
Forming a plating layer, filling the through-hole (hereinafter, referred to as IVH) with the first plating layer with a filling resin, and etching the filling resin in the IVH to a desired depth. A step of forming a recess in the IVH, a step of forming a conductor layer in the recess, and etching the first plating layer to form an inner layer conductor circuit on the surface of the laminate and a conductor land on the surface of the IVH. A step of forming a wiring board, a step of coating the surface of the inner printed wiring board with an insulating resin, and forming a via hole in the insulating resin on the IVH so that the conductor layer in the concave portion of the IVH is exposed. And a step of forming a second plating layer on a surface of the insulating resin including the via hole.

【0013】本発明における前記IVHの前記凹部への
前記導電体層の形成方法としては、前記凹部形成後、前
記凹部を充填するように前記第1のめっき層表面にめっ
き膜を形成し、このめっき膜を前記第1のめっき層が露
出するように機械研磨や化学的にエッチングする方法
や、前記凹部に導電性ペーストを選択的に充填する方法
を採用することができる。
In the present invention, the method of forming the conductive layer in the concave portion of the IVH may include forming a plated film on the surface of the first plating layer so as to fill the concave portion after forming the concave portion. A method of mechanically polishing or chemically etching the plating film so that the first plating layer is exposed, or a method of selectively filling the recess with a conductive paste can be adopted.

【0014】本発明においては、内層印刷配線板の内層
導体回路形成時のエッチングする銅の厚さを薄くするこ
とができるために内層印刷配線板の内層導体回路の細線
化ができ、またIVH内部の穴埋め樹脂上の導電体層の
厚さも厚くできるために、IVHとビアホールとの接続
信頼性も高く保持できる効果を得ることができる。
In the present invention, the thickness of the copper to be etched when forming the inner conductor circuit of the inner printed wiring board can be reduced, so that the inner conductor circuit of the inner printed wiring board can be made thinner, and the IVH internal circuit can be formed. Since the thickness of the conductor layer on the filling resin can be increased, the effect of maintaining high connection reliability between the IVH and the via hole can be obtained.

【0015】[0015]

【発明の実施の形態】次に、本発明の多層印刷配線板の
製造方法の実施の形態について図面を参照して説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for manufacturing a multilayer printed wiring board according to the present invention will be described with reference to the drawings.

【0016】図1は、本発明の第1の実施の形態の多層
印刷配線板の製造方法の工程を説明するための基板要部
の拡大断面図である。図2は図1に続く多層印刷配線板
の製造方法の工程を説明するための基板要部の拡大断面
図である。また、図3は図2に続く多層印刷配線板の製
造方法の工程を説明するための基板要部の拡大断面図で
ある。
FIG. 1 is an enlarged sectional view of a main part of a substrate for describing steps of a method for manufacturing a multilayer printed wiring board according to a first embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of a main part of a substrate for describing steps of a method for manufacturing a multilayer printed wiring board following FIG. FIG. 3 is an enlarged cross-sectional view of a main part of a substrate for describing steps of a method for manufacturing a multilayer printed wiring board following FIG.

【0017】図1を参照すると、まず図1(a)で両面
に銅箔2を張り付けた積層板1に貫通孔3aをドリル加
工やパンチング加工等により形成する。次いで、積層板
1の貫通孔3aと表面に第1のめっき層4を形成する。
貫通孔3aは導電化されIVH3となる(図1
(b))。
Referring to FIG. 1, first, a through-hole 3a is formed by drilling, punching, or the like in a laminated plate 1 having copper foils 2 adhered to both sides in FIG. 1 (a). Next, the first plating layer 4 is formed on the through holes 3 a and the surface of the laminate 1.
The through-hole 3a is made conductive and becomes IVH3 (FIG. 1).
(B)).

【0018】上記の第1の第1のめっき層4は、無電解
銅めっきの厚付け法や無電解銅めっきと電気銅めっきの
併用法により形成される。その際のめっき厚はIVH3
の導通の信頼性を確保するために20μm程度の厚みが
必要である。
The first first plating layer 4 is formed by a method of thickening electroless copper plating or a combination of electroless copper plating and electrolytic copper plating. The plating thickness at that time is IVH3
Is required to have a thickness of about 20 μm in order to ensure the reliability of conduction.

【0019】次に図1(c)のようにIVH3内に穴埋
め樹脂5を充填し、穴埋めを実施する。この樹脂として
は例えば、山栄化学株式会社製のPHP−900 IR
−1熱硬化型エポキシ樹脂等を使用することができ、ス
クリーン印刷法により、穴埋め樹脂5をIVH3に充填
後、温度約140℃で、30分間のベーキングを行い、
穴埋め樹脂5を熱硬化させた後、IVH3の表面を平滑
化するために、機械的研磨等により積層板1を表面研磨
する。研磨方法としては、ベルトサンダー研磨機等を用
いればよく、表面平滑度の高い研磨剤例えば三共理化学
(株)製レジンクロスベルトRAXB AA#600を
用いることにより、第1のめっき層4とIVH3の穴埋
め樹脂5の表面の平滑性を実現する事ができた。穴埋め
樹脂5としては、熱硬化型エポキシ樹脂の他に紫外線硬
化型のエポキシ樹脂等も使用でき、また、これらの穴埋
め樹脂5にはめっきの密着性を向上させるためにパラジ
ウム金属を添加してもよい。
Next, as shown in FIG. 1C, the filling resin 5 is filled in the IVH 3 and filling is performed. Examples of the resin include PHP-900 IR manufactured by Yamaei Chemical Co., Ltd.
-1 A thermosetting epoxy resin or the like can be used. After filling the filling resin 5 into the IVH 3 by a screen printing method, baking is performed at a temperature of about 140 ° C. for 30 minutes,
After thermosetting the filling resin 5, the surface of the laminate 1 is polished by mechanical polishing or the like in order to smooth the surface of the IVH3. As a polishing method, a belt sander polishing machine or the like may be used. By using a polishing agent having a high surface smoothness, for example, a resin cross belt RAXB AA # 600 manufactured by Sankyo Rikagaku Co., Ltd., the first plating layer 4 and the IVH3 can be polished. The smoothness of the surface of the filling resin 5 could be realized. As the filling resin 5, an ultraviolet-curing epoxy resin or the like can be used in addition to the thermosetting epoxy resin, and palladium metal may be added to these filling resins 5 in order to improve the adhesion of plating. Good.

【0020】次に図1(d)のようにIVH3に充填し
た穴埋め樹脂5の表層を10μmから20μmの深さで
樹脂エッチングし、穴埋め樹脂5上に樹脂エッチング部
分(以下、凹部6という)を形成する。この際の凹部6
の深さが10μmより少なくなった場合は、凹部6の導
電体層層7とビアホールとの接続信頼性が低下する問題
点が生じる。また、この凹部6の深さが20μmより多
くなった場合は、めっきでこの凹部を充填するための処
理時間の増加等が生ずる。従って、この樹脂エッチング
の深さのコントロールは上記範囲内に収まるように管理
することが肝要である。
Next, as shown in FIG. 1D, the surface layer of the filling resin 5 filled in the IVH 3 is resin-etched to a depth of 10 μm to 20 μm, and a resin-etched portion (hereinafter referred to as a concave portion 6) is formed on the filling resin 5. Form. Recess 6 at this time
If the depth is smaller than 10 μm, there arises a problem that the connection reliability between the conductive layer 7 of the recess 6 and the via hole is reduced. If the depth of the concave portion 6 is larger than 20 μm, the processing time for filling the concave portion with plating increases. Therefore, it is important to control the depth of the resin etching so as to fall within the above range.

【0021】上記の樹脂のエッチング方法としてはアル
カリ性過マンガン酸塩水溶液によるエッチング方法を使
用した。まず、アルカリ性水溶液(アルカリ規定度0.
7〜0.8N、温度70〜80℃)で樹脂の膨潤処理を
行い、続いてアルカリ過マンガン酸塩水溶液(規定度
1.0〜1.2N、過マンガン酸塩濃度43〜55g/
l、浴温75℃±2℃)で約10分間、樹脂をエッチン
グする。その後、硫酸(規定度0.3〜0.4N、温度
40〜50℃)で中和し、穴埋め樹脂5のエッチングを
完了する。なお、穴埋め樹脂3のエッチング方法とし
て、アルカリ性過マンガン酸水溶液による化学処理方法
の他にCF4/O2,O2 ,Arのプラズマガスによるプ
ラズマエッチング方法やエキシマレーザー,YAGレー
ザー,CO2レーザー等によるレーザー加工処理方法を
使用することもできる。
An etching method using an alkaline aqueous solution of permanganate was used as the method for etching the resin. First, an alkaline aqueous solution (alkaline normality of 0. 1).
The resin is subjected to a swelling treatment at 7 to 0.8 N at a temperature of 70 to 80 ° C., followed by an aqueous alkali permanganate solution (normality: 1.0 to 1.2 N, permanganate concentration: 43 to 55 g /
1, at a bath temperature of 75 ° C. ± 2 ° C.) for about 10 minutes. Thereafter, the mixture is neutralized with sulfuric acid (normality: 0.3 to 0.4 N, temperature: 40 to 50 ° C.), and the etching of the filling resin 5 is completed. As a method for etching the filling resin 3, a plasma etching method using a plasma gas of CF 4 / O 2 , O 2 , Ar, an excimer laser, a YAG laser, a CO 2 laser, etc., in addition to a chemical treatment method using an alkaline permanganate aqueous solution. Can be used.

【0022】次に図1(e)に示すように電気銅めっき
(IVH表面めっきという)により、第1のめっき層4
の表面並びに凹部6に導電体層7を形成する。その際の
導電体層7の厚みは穴埋め樹脂5の凹部6を埋め込む程
度の厚みが必要であり、最低でも20μmの厚みが必要
となる。
Next, as shown in FIG. 1E, the first plating layer 4 is formed by electrolytic copper plating (referred to as IVH surface plating).
The conductor layer 7 is formed on the surface of the substrate and the recess 6. At this time, the thickness of the conductor layer 7 needs to be large enough to bury the concave portion 6 of the filling resin 5, and needs to be at least 20 μm.

【0023】次いで図2(f)に示すように2回めっき
を実施したことにより厚くなった表層の導電体層7を機
械研磨もしくは化学研磨によって薄化する。ここではベ
ルトサンダー等の機械研磨の方法、例えば三共理化学
(株)製レジンクロスベルトRAXB AA#400を
用いることにより、表層の導体層を約20μm研磨し
た。この研磨により表層の導体層は銅箔2及び第1のめ
っき層4のみの厚みに加工でき、凹部6の導電体層(凹
部導電体層8という)の高さが表層の第1のめっき層4
の高さと同等になった積層板1が得られる。
Next, as shown in FIG. 2 (f), the surface of the conductor layer 7 which is thickened by plating twice is thinned by mechanical polishing or chemical polishing. Here, the surface conductor layer was polished by about 20 μm by using a mechanical polishing method such as a belt sander, for example, using a resin cross belt RAXB AA # 400 manufactured by Sankyo Rikagaku Co., Ltd. By this polishing, the surface conductor layer can be processed to a thickness of only the copper foil 2 and the first plating layer 4, and the height of the conductor layer in the recess 6 (referred to as the recess conductor layer 8) is equal to the surface of the first plating layer. 4
Is obtained.

【0024】このようにして得られた積層板1を公知の
回路形成方法で回路を加工する。その回路形成方法とし
てはエッチング工程を含むものであれば特に限定される
ものではない。例えば、表層の導体層にドライフィルム
フォトエッチングレジストをラミネートもしくは電着型
フォトエッチングレジストを電着塗装を施した後、エッ
チングレジストを露光・現像した後、塩化第2銅、また
は塩化第2鉄等のエッチング液で浸漬、またはスプレー
方法でエッチングすることにより、図2(g)に示すよ
うに内層内層導体回路9、並びにIVH3上に導体ラン
ド10を有する内層内層印刷配線板11が形成される。
The laminate 1 thus obtained is processed into a circuit by a known circuit forming method. The circuit forming method is not particularly limited as long as it includes an etching step. For example, after laminating a dry film photo-etching resist or electrodepositing an electrodeposition type photo-etching resist on the surface conductor layer, exposing and developing the etching resist, cupric chloride or ferric chloride etc. 2 (g), the inner-layer inner-layer conductor circuit 9 and the inner-layer inner-layer printed wiring board 11 having the conductor land 10 on the IVH 3 are formed as shown in FIG. 2 (g).

【0025】その後、内層導体回路9表面並びに導体ラ
ンド10表面に黒化処理を実施し、酸化銅を形成した。
これは次に塗布する感光性樹脂と導体回路等との密着性
を向上させるために、内層導体回路9および導体ランド
10の表面を粗面化する目的で実施される。
Thereafter, the surface of the inner layer conductor circuit 9 and the surface of the conductor land 10 were subjected to blackening treatment to form copper oxide.
This is performed for the purpose of roughening the surfaces of the inner layer conductor circuit 9 and the conductor land 10 in order to improve the adhesion between the photosensitive resin to be applied next and the conductor circuit or the like.

【0026】次に図2(h)に示すように内層印刷配線
板11上に感光性の絶縁樹脂12(例えば、エポキシ樹
脂)をカーテンコーター、ロールコーターまたはスクリ
ーン印刷等の方法で塗布する。例えば、カーテンコータ
ーにより、感光性の絶縁樹脂12を約60μm厚に塗布
し、温度90℃で約1時間の指触乾燥を実施した後、I
VH3と絶縁樹脂12上の導体層(外層導体回路等)と
を接続するためのビアホールをフォトリソグラフィーで
形成する。即ち、マスクフィルムを用いて密着露光後、
1重量%濃度の炭酸ナトリウム水溶液等の現像液により
光重合していない絶縁樹脂12(ビアホール形成部分)
を現像除去し、温度130℃で約90分間のポストベー
キングまたは紫外線キュア(例えば露光量600mJ/c
2の紫外線照射等)を行い、図2(i)に示すようにビ
アホール13を形成した。
Next, as shown in FIG. 2H, a photosensitive insulating resin 12 (for example, epoxy resin) is applied on the inner printed wiring board 11 by a method such as a curtain coater, a roll coater, or screen printing. For example, the photosensitive insulating resin 12 is applied to a thickness of about 60 μm by a curtain coater, and the touch drying is performed at a temperature of 90 ° C. for about 1 hour.
Via holes for connecting the VH 3 and a conductor layer (such as an outer conductor circuit) on the insulating resin 12 are formed by photolithography. That is, after contact exposure using a mask film,
Insulating resin 12 that is not photopolymerized by a developing solution such as a 1% by weight aqueous solution of sodium carbonate (a portion where a via hole is formed).
Is removed by post-baking or ultraviolet curing at a temperature of 130 ° C. for about 90 minutes (for example, an exposure amount of 600 mJ / c).
UV irradiation of m 2 , etc.) to form a via hole 13 as shown in FIG.

【0027】次に絶縁樹脂12の表面に形成する導体層
の密着度を向上させる目的で絶縁樹脂12の表面をアル
カリ過マンガン酸塩水溶液等で粗面化し、絶縁樹脂12
の表面に深さ0.1〜1μmの微細な凸凹を形成する。
Next, the surface of the insulating resin 12 is roughened with an alkali permanganate aqueous solution or the like to improve the adhesion of the conductor layer formed on the surface of the insulating resin 12.
Are formed with a depth of 0.1 to 1 [mu] m on the surface.

【0028】その後、図3(j)に示すようにめっき浴
に浸漬し、無電解銅めっき等のめっき処理を施すことに
より約20μm程度の厚さの第2のめっき層14を形成
する。その後、公知の回路形成方法により外層導体回路
15を形成し、図3(k)に示すようにIVH3上にビ
アホール13が形成された多層印刷配線板16を得た。
Thereafter, as shown in FIG. 3J, the second plating layer 14 having a thickness of about 20 μm is formed by dipping in a plating bath and performing plating such as electroless copper plating. Thereafter, an outer layer conductor circuit 15 was formed by a known circuit forming method, and a multilayer printed wiring board 16 having via holes 13 formed on the IVH 3 as shown in FIG. 3K was obtained.

【0029】上記の第1の実施の形態では、ビアホール
13をフォトリソグラフィー的に形成したが、エキシマ
レーザー,YAGレーザー,CO2 レーザー等のレーザ
ー光を照射してもビアホールを形成することができる。
この場合には絶縁樹脂12としては熱硬化性の絶縁樹脂
を使用してもよい。
In the first embodiment, the via hole 13 is formed by photolithography. However, the via hole can be formed by irradiating a laser beam such as an excimer laser, a YAG laser, or a CO 2 laser.
In this case, a thermosetting insulating resin may be used as the insulating resin 12.

【0030】次に、本発明の第2の実施の形態の多層印
刷配線板の製造方法について説明する。本発明の実施の
形態の多層印刷配線板の製造方法では、上記の第1の実
施の形態におけるIVH3の穴埋め樹脂5のエッチング
後、IVH3の凹部に導電性ペーストを充填後、エッチ
ングにより内層導体回路と導体ランドを形成する方法
で、第1の実施の形態におけるIVH表面めっきと表面
研磨処理を省くことができる。導電ペーストはIVHの
深さ20μm程度の凹部に形成すればよいので、導電ペ
ーストが充填しやすく、表面が平滑なIVHが得られ
る。前記導電性ペーストとしては銀や銅のペーストが使
用できるが、導電ペーストにパラジウム金属を添加する
ことによって凹部に充填した導電ペーストと銅めっき
(無電解銅めっき)の密着性増加によるIVHとビアホ
ールの接続信頼性を向上する効果が得られる。
Next, a method for manufacturing a multilayer printed wiring board according to a second embodiment of the present invention will be described. In the method for manufacturing a multilayer printed wiring board according to the embodiment of the present invention, after the filling resin 5 of the IVH 3 in the first embodiment is etched, the concave portion of the IVH 3 is filled with a conductive paste, and then the inner layer conductor circuit is etched. With the method of forming the conductive lands, the IVH surface plating and the surface polishing treatment in the first embodiment can be omitted. Since the conductive paste may be formed in a recess having a depth of about 20 μm of the IVH, the conductive paste can be easily filled and an IVH having a smooth surface can be obtained. As the conductive paste, a silver or copper paste can be used. However, the addition of palladium metal to the conductive paste increases the adhesion between the conductive paste filled in the recesses and the copper plating (electroless copper plating) to increase the IVH and via hole. The effect of improving connection reliability is obtained.

【0031】[0031]

【発明の効果】本発明の多層印刷配線の製造方法におけ
る第1の効果はIVH同軸上のビアの形成が可能となり
配線の自由度が向上することである。その理由はIVH
に充填した穴埋め樹脂上に導体層を形成しているためで
ある。本発明の第2の効果は微細回路を形成する際の回
路形成精度が向上し細線化がはかれることである。その
理由は充填した穴埋め樹脂を一定の深さまでエッチング
後、この凹部に銅めっきや導電性ペーストで導電層を充
填平滑化してエッチングする銅の厚さを薄化できるため
である。
A first effect of the method for manufacturing a multilayer printed wiring according to the present invention is that a via on the IVH coaxial can be formed, and the degree of freedom of wiring is improved. The reason is IVH
This is because the conductor layer is formed on the filling resin filled into the substrate. A second effect of the present invention is that the circuit formation accuracy when forming a fine circuit is improved and the line is thinned. The reason for this is that after etching the filled filling resin to a certain depth, the recess can be filled with a conductive layer with copper plating or a conductive paste to smoothen the thickness of the etched copper.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態の多層印刷配線板の
製造方法の工程を説明するための基板要部の拡大断面図
である。
FIG. 1 is an enlarged cross-sectional view of a main part of a substrate for describing steps of a method for manufacturing a multilayer printed wiring board according to a first embodiment of the present invention.

【図2】図1に続く多層印刷配線板の製造方法の工程を
説明するための基板要部の拡大断面図である。
FIG. 2 is an enlarged cross-sectional view of a main part of a substrate, for illustrating steps of a method of manufacturing the multilayer printed wiring board following FIG. 1;

【図3】図2に続く多層印刷配線板の製造方法の工程を
説明するための基板要部の拡大断面図である。
FIG. 3 is an enlarged cross-sectional view of a main part of the substrate, for illustrating steps of a method of manufacturing the multilayer printed wiring board following FIG. 2;

【図4】従来の多層印刷配線板の製造方法の工程を説明
するための基板要部の拡大断面図である。
FIG. 4 is an enlarged cross-sectional view of a main part of a substrate for describing steps of a conventional method for manufacturing a multilayer printed wiring board.

【図5】図4に続く従来の多層印刷配線板の製造方法の
工程を説明するための基板要部の拡大断面図である。
FIG. 5 is an enlarged cross-sectional view of a main part of the substrate, for explaining steps of a conventional method for manufacturing a multilayer printed wiring board following FIG. 4;

【符号の説明】[Explanation of symbols]

1 積層板 2 銅箔 3 IVH 3a 貫通孔 4 第1のめっき層 5 穴埋め樹脂 6 凹部 7 導電体層 8 凹部導電体層 9 内層導体回路 10 導体ランド 11 内層印刷配線板 12 絶縁樹脂 13 ビアホール 14 第2のめっき層 15 外層導体回路 16 多層印刷配線板 REFERENCE SIGNS LIST 1 laminated board 2 copper foil 3 IVH 3a through hole 4 first plating layer 5 filling resin 6 recess 7 conductive layer 8 concave conductive layer 9 inner conductor circuit 10 conductor land 11 inner printed wiring board 12 insulating resin 13 via hole 14th 2 plating layer 15 outer layer conductor circuit 16 multilayer printed wiring board

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 両面に銅箔を有する積層板に貫通孔を形
成する工程と、前記貫通孔を含む前記積層板表面に第1
のめっき層を形成する工程と、前記第1のめっき層を形
成した前記貫通孔に穴埋め樹脂を充填する工程と、前記
貫通孔中の前記穴埋め樹脂を所望の深さエッチングし前
記貫通孔に凹部を形成する工程と、前記凹部に導電体層
を形成する工程と、前記第1のめっき層をエッチングし
前記積層板表面に内層導体回路と前記貫通孔表面に導体
ランドを有する内層印刷配線板を形成する工程と、前記
内層印刷配線板表面に絶縁樹脂を被覆する工程と、前記
内層印刷配線板の前記貫通孔上の前記絶縁樹脂に該貫通
孔の前記凹部の前記導電体層が露出するようにビアホー
ルを形成する工程と、前記ビアホールを含む前記絶縁樹
脂の表面に第2のめっき層を形成する工程とを含むこと
を特徴とする多層印刷配線板の製造方法。
1. A step of forming a through hole in a laminate having copper foils on both sides, and a first step in a surface of the laminate including the through hole.
Forming a plating layer, filling the through hole with the first plating layer with a filling resin, and etching the filling resin in the through hole to a desired depth to form a recess in the through hole. Forming a conductor layer in the recess, etching the first plating layer to form an inner printed circuit board having an inner conductor circuit on the surface of the laminate and a conductor land on the surface of the through hole. Forming, coating the surface of the inner printed wiring board with an insulating resin, and exposing the conductive layer in the recess of the through hole to the insulating resin on the through hole of the inner printed wiring board. Forming a second plated layer on the surface of the insulating resin including the via hole.
【請求項2】 前記貫通孔中の前記穴埋め樹脂の前記エ
ッチングする方法として、アルカリ性過マンガン酸によ
る化学的処理法,プラズマエッチング方法またはレーザ
ーエッチング方法を使用した請求項1記載の多層印刷配
線板の製造方法。
2. The multilayer printed wiring board according to claim 1, wherein the method of etching the filling resin in the through-holes is a chemical treatment method using alkaline permanganate, a plasma etching method or a laser etching method. Production method.
【請求項3】 前記貫通孔の前記凹部の前記導電体層
を、前記凹部を充填するようにめっき膜を前記積層板表
面に形成し、次いで前記第1のめっき層が露出するまで
前記積層板表面を機械研磨あるいは化学研磨することに
より形成した請求項1または2記載の多層印刷配線板の
製造方法。
3. A plating film is formed on the surface of the laminated plate so as to fill the conductive layer in the concave portion of the through hole with the concave portion, and then the laminated plate is exposed until the first plated layer is exposed. 3. The method according to claim 1, wherein the surface is formed by mechanical polishing or chemical polishing.
【請求項4】 前記貫通孔の前記凹部の前記導電体層
を、前記凹部に導電性ペーストを充填することにより形
成した請求項1または2記載の多層印刷配線板の製造方
法。
4. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein the conductive layer in the concave portion of the through hole is formed by filling the concave portion with a conductive paste.
【請求項5】 前記導電性ペーストとして、銀とパラジ
ウムの金属あるいは銅とパラジウム金属を含む導電ペー
ストを使用した請求項1,2または4記載の多層印刷配
線板の製造方法。
5. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein a conductive paste containing silver and palladium metal or copper and palladium metal is used as said conductive paste.
【請求項6】 前記内層印刷配線板表面に形成する絶縁
樹脂として感光性または熱硬化性の絶縁樹脂を使用した
請求項1乃至請求項5のいずれかに記載の多層印刷配線
板の製造方法。
6. The method for manufacturing a multilayer printed wiring board according to claim 1, wherein a photosensitive or thermosetting insulating resin is used as the insulating resin formed on the surface of the inner printed wiring board.
【請求項7】 前記穴埋め樹脂としてパラジウム金属を
添加した熱硬化型または紫外線硬化型エポキシ樹脂を使
用した請求項1乃至請求項6のいずれかに記載の多層印
刷配線板の製造方法。
7. The method for producing a multilayer printed wiring board according to claim 1, wherein a thermosetting or ultraviolet curing epoxy resin to which palladium metal is added is used as the filling resin.
JP7939298A 1998-03-26 1998-03-26 Method for manufacturing multilayer printed wiring board Expired - Fee Related JP3012590B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7939298A JP3012590B2 (en) 1998-03-26 1998-03-26 Method for manufacturing multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7939298A JP3012590B2 (en) 1998-03-26 1998-03-26 Method for manufacturing multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPH11274730A true JPH11274730A (en) 1999-10-08
JP3012590B2 JP3012590B2 (en) 2000-02-21

Family

ID=13688602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7939298A Expired - Fee Related JP3012590B2 (en) 1998-03-26 1998-03-26 Method for manufacturing multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP3012590B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291956A (en) * 2000-04-05 2001-10-19 Ngk Spark Plug Co Ltd Multilayered printed wiring board and producing method therefor
US7540082B2 (en) 2003-08-28 2009-06-02 International Business Machines Corporation Method for manufacturing printed wiring board
KR101015688B1 (en) * 2008-11-13 2011-02-22 삼성전기주식회사 Apparatus for manufacturing printed circuit board and method for manufacturing printed circuit board using the same
JP2011049447A (en) * 2009-08-28 2011-03-10 Kyocer Slc Technologies Corp Wiring board and method for manufacturing the same
US8129625B2 (en) 2003-04-07 2012-03-06 Ibiden Co., Ltd. Multilayer printed wiring board
CN105530768A (en) * 2014-09-28 2016-04-27 深南电路有限公司 Circuit board manufacturing method and circuit board
US9433096B2 (en) 2011-10-12 2016-08-30 Shinko Electric Industries Co., Ltd. Wiring board, semiconductor device and method for manufacturing wiring board

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101396704B1 (en) * 2012-12-20 2014-05-16 삼성전기주식회사 Circuit board and method for manufacturing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001291956A (en) * 2000-04-05 2001-10-19 Ngk Spark Plug Co Ltd Multilayered printed wiring board and producing method therefor
US8129625B2 (en) 2003-04-07 2012-03-06 Ibiden Co., Ltd. Multilayer printed wiring board
US7540082B2 (en) 2003-08-28 2009-06-02 International Business Machines Corporation Method for manufacturing printed wiring board
KR101015688B1 (en) * 2008-11-13 2011-02-22 삼성전기주식회사 Apparatus for manufacturing printed circuit board and method for manufacturing printed circuit board using the same
JP2011049447A (en) * 2009-08-28 2011-03-10 Kyocer Slc Technologies Corp Wiring board and method for manufacturing the same
US9433096B2 (en) 2011-10-12 2016-08-30 Shinko Electric Industries Co., Ltd. Wiring board, semiconductor device and method for manufacturing wiring board
CN105530768A (en) * 2014-09-28 2016-04-27 深南电路有限公司 Circuit board manufacturing method and circuit board

Also Published As

Publication number Publication date
JP3012590B2 (en) 2000-02-21

Similar Documents

Publication Publication Date Title
JP4405993B2 (en) Method for manufacturing high-density printed circuit board
JP2009260204A (en) Printed circuit board and method of manufacturing the same
JP3012590B2 (en) Method for manufacturing multilayer printed wiring board
JP2003133727A (en) Method for manufacturing resin padding substrate and manufacturing method for multi-layer printed wiring board using the substrate
JP4066848B2 (en) Manufacturing method of multilayer printed wiring board
WO2017094470A1 (en) Multilayer printed wiring board and method for manufacturing same
JP2022030289A (en) Wiring board and method for manufacturing wiring board
JPH1187865A (en) Printed circuit board and its manufacture
JP2001094252A (en) Method for manufacturing of multilayer semiconductor board
KR20040061410A (en) PCB with the plated through holes filled with copper with copper and the fabricating method thereof
JPH10215072A (en) Manufacture of multilayer printed wiring board
JP2003124632A (en) Multilayer printed wiring board and its manufacturing method
JP2000091750A (en) Method for forming through hole, multilayered printed wiring board and manufacture thereof and through hole forming substrate
JP3143408B2 (en) Manufacturing method of printed wiring board
JP4045120B2 (en) Multilayer printed wiring board and manufacturing method thereof
JP2001291956A (en) Multilayered printed wiring board and producing method therefor
JP6598694B2 (en) Thick copper circuit board and manufacturing method thereof
JP2001267724A (en) Printed board and its manufacturing method
JP4059386B2 (en) Multilayer printed wiring board and manufacturing method thereof
JP2984625B2 (en) Multilayer printed wiring board manufacturing method
JPH077264A (en) Manufacture of printed wiring board
JPH08204339A (en) Manufacture of printed wiring board
JP3713726B2 (en) Multilayer printed wiring board
JPH1187924A (en) Multilayered printed circuit board with non-penetrating via hole
JP4051923B2 (en) Manufacturing method of build-up multilayer printed wiring board

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19991116

LAPS Cancellation because of no payment of annual fees