JPH11274409A - Semiconductor device, its manufacture and its etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously form a source opening part and an element separation opening part by wet-etching by a method wherein, in a capacitor, a lower electrode formed at a first height level on a substrate is further extended to a second height level, and a dielectric film and an upper electrode are formed in this order on the lower electrode. SOLUTION: A recess part 21A is formed on a substrate 21, and a lower electrode layer and a SiN film are respectively formed so as to cover the recess part 21A, and an upper electrode 25 is formed in a part covering the recess part 21a out of the SiN film. Next, a capacitor C comprising a SiO2 pattern 22A, a lower electrode 23A and a SiN capacitor dielectric film 24A is formed on the substrate 21. A lower electrode pattern 23A of the capacitor C is formed so as to extend to the outside of the recess part 21A, namely onto a main face of the substrate 21. A thickness of the lower electrode layer, the SiN film and the upper electrode 25 is set so that an upper main face of the upper electrode 25 is set to the substantially same height as an upper main face of a part extending to the outside of the recess 21A out of the lower electrode pattern 23A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to a compound semiconductor device and a method of manufacturing the same. A compound semiconductor device operates at a higher speed than a normal Si semiconductor device because a compound semiconductor having a small effective mass of electrons is used for an active portion. Therefore, a so-called MMIC (Monolithic Mic) that operates in a microwave band such as a mobile phone and a satellite communication.
rowave IntegratedCircuit).

In such an MMIC, Ga, Al, I
It is necessary to monolithically form a capacitor on an integrated circuit including a group III-V compound semiconductor epitaxial layer composed of a group III element such as n and a group V element such as As and P, and to maximize the operation speed as much as possible. In order to achieve this, an electron beam drawing technique is used. In order to further increase the operating speed, the thickness of the compound semiconductor substrate has been reduced as much as possible in the conventional MMIC, and the source electrode is directly connected to the ground electrode formed on the back surface of the substrate through the via hole formed in the semiconductor substrate. The configuration of grounding is adopted. In the MMIC using the via hole technology, after a large number of integrated circuit devices are integrally formed on the semiconductor substrate, they are divided into individual integrated circuit devices by etching.

[0003]

2. Description of the Related Art FIGS. 12A to 14G show a process of manufacturing a conventional MMIC including a capacitor. FIG.
Referring to (A), an SiO ₂ film 12 is formed as a protective film on a semi-insulating substrate 11 made of a compound semiconductor such as GaAs, and the protective film 1 is formed in the step of FIG.
A lower electrode layer 13 having an Au / Ti structure is deposited on the substrate 2 by sputtering. However, the semi-insulating substrate 11 may further include a buffer layer or an electron transit layer made of undoped GaAs. Semiconductor device in MMIC is HE
In the case of MT, an n-type AlGaAs layer may be further included.

Next, in the step of FIG. 12C, a dielectric film 14 made of SiN or the like is deposited on the lower electrode layer 13 by sputtering or CVD.
In step 3 (D), an upper electrode pattern 15 having an Au / Ti structure is formed on the dielectric film 14 by sputtering and a lift-off method. Further, FIG.
In the step (E), the dielectric film 14 is patterned,
Further, the lower electrode layer 13 is patterned to form a lower electrode pattern.
Is formed.

Next, in the step of FIG.
An active element such as a HEMT including a gate electrode 16 and source / drain electrodes 17A and 17B adjacent to the capacitor C is formed thereon by using, for example, an electron beam drawing technique. Further, in the step of FIG. An interlayer insulating film 18 of SiO ₂ or the like is formed so as to cover the structure of FIG. Further, the capacitor C is provided in the interlayer insulating film 18.
A contact hole 18A exposing the upper electrode 15 and a contact hole 18B exposing the lower electrode 13 are formed, and the wiring pattern 1 is formed on the interlayer insulating film 18.
9A and 19B are formed such that the wiring pattern 19A contacts the upper electrode 15 via the contact hole 18A and the wiring pattern 19B contacts the lower electrode 13 via the contact hole 18B. I do.

[0006]

FIG. 15 is an enlarged view of a portion near the capacitor C in the MMIC thus formed. Referring to FIG. 15, the interlayer insulating film 18
The depth of the contact hole 18B formed therein and exposing the lower electrode 13 is inevitably greater than the depth of the contact hole 18B exposing the upper electrode 15, and as a result, the length of the wiring pattern 19B filling the contact hole 18B L ₂ , that is, inductance is in contact hole 1
Inevitably it becomes larger than the inductance corresponding to the length L ₁ of the wiring pattern 19A to fill the 8A (L ₁ <
L _2). In general, it is difficult to sufficiently consider such a change in the inductance of the wiring pattern due to the depth of the contact hole in the integrated circuit design using CAD. Therefore, the problem occurs only after checking the operation of the prototyped MMIC. Is often recognized. In such a case, it is necessary to redesign the integrated circuit. However, such redesigning not only increases the manufacturing cost of the MMIC but also shifts the timing of introducing the MMIC to the market.

Accordingly, it is a general object of the present invention to provide a new and useful semiconductor device which solves the above-mentioned problems, and a method of manufacturing the same. More specific objects of the present invention are:
It is an object of the present invention to provide a semiconductor device having a configuration in which an inductance of a wiring pattern connected to a capacitor is substantially equal to an inductance of a wiring pattern connected to a lower electrode and a wiring pattern connected to an upper electrode.

Another object of the present invention is to provide a semiconductor device having a configuration in which the depth of a contact hole is substantially equal between a wiring pattern connected to the lower electrode and a wiring pattern connected to the upper electrode. In doing so, it is an object of the present invention to provide a technique for forming a concave portion by wet etching in a semiconductor substrate including a plurality of compound semiconductor layers having different compositions.

Another object of the present invention is to form a semiconductor device on a semiconductor substrate including a plurality of compound semiconductor layers having different compositions by an electron beam lithography technique, and to further form a semiconductor device in the substrate corresponding to a source region. A method of manufacturing a semiconductor device in which a source opening reaching the back surface of a substrate is formed, and an element isolation opening is formed at the same time so as to reach the back surface of the substrate. It is to provide a forming technique.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device comprising a substrate and a capacitor formed on the substrate. A lower electrode formed at a first height level on the substrate, a dielectric film formed on the lower electrode, and an upper electrode formed on the dielectric film;
The lower electrode has a second height above the first height level.
The lower electrode is formed in a concave portion formed on the substrate surface by a semiconductor device characterized by extending to a height level of, or as described in claim 2, 2. The semiconductor device according to claim 1, wherein the semiconductor device extends to the outside of the recess along the defining side wall surface, and is located at the second level outside the recess. 3.
The semiconductor device according to claim 1 or 2, wherein the upper electrode is located at a level substantially the same as the second level. As described in the above, further comprising an interlayer insulating film on the substrate so as to cover the capacitor, wherein the interlayer insulating film has a first contact hole exposing the upper electrode and a lower electrode of the second level. An exposed second contact hole is formed, and a first conductor pattern that contacts the upper electrode via the first contact hole on the interlayer insulating film; and a second contact hole is formed on the interlayer insulating film. 4. The semiconductor device according to claim 1, wherein a second conductive pattern that contacts the lower electrode is formed through the semiconductor device. 5. The method according to claim 1, wherein a protrusion having the second height level is formed on the substrate, and the lower electrode extends to the protrusion. Or a method of manufacturing a semiconductor device comprising a substrate and a capacitor formed on the substrate, as described in claim 6,
Forming a concave portion on the substrate surface by etching, forming a lower electrode of the capacitor on the concave portion so as to extend out of the concave portion, and forming a dielectric film of the capacitor on the lower electrode. 8. A method of manufacturing a semiconductor device according to claim 7, further comprising the steps of: forming, and forming an upper electrode of the capacitor corresponding to the recess on the dielectric film. To
Forming an interlayer insulating film on the substrate so as to fill the capacitor; and forming a first opening exposing the upper electrode and exposing the lower electrode outside the recess in the interlayer insulating film. A step of forming a second opening and a second step of forming the second substrate. The method according to claim 6, wherein the substrate is substantially free from P. 1, a III-V compound semiconductor layer, and a first compound semiconductor layer formed on the first compound semiconductor layer;
A second III-V compound semiconductor layer containing P, and a third III-V compound semiconductor layer formed on the second III-V compound semiconductor layer and containing substantially no P The step of forming the concave portion, including laminating, is performed by the third I
Etching the II-V compound semiconductor layer with a first etchant until the second III-V compound semiconductor layer is exposed;
Etching the group V compound semiconductor layer with an etchant having a second composition different until the first group III-V compound semiconductor layer is exposed;
A step of etching the group-V compound semiconductor layer with a third etchant having a different composition from the second etchant; and a step of etching the second group III-V compound semiconductor layer. The step of etching the second III-V compound semiconductor layer according to the method of manufacturing a semiconductor device according to claim 6 or 7, or the step of etching the second III-V compound semiconductor layer is performed by using the second etchant. 9. The method according to claim 8, wherein
11. The method for manufacturing a semiconductor device according to claim 10, or
9. The method according to claim 8, wherein the step of etching the second III-V compound semiconductor layer is performed by a fourth etchant having a composition different from that of the second etchant. The first and third group III-V compound semiconductor layers are formed of GaAs by the method of manufacturing a semiconductor device according to the present invention or as set forth in claim 11.
Wherein the second III-V compound semiconductor layer comprises I
nGaP, the first and third etchants are a mixture of HF, H ₂ O ₂ and H ₂ O, and the _second and third etchants are
13. The method of manufacturing a semiconductor device according to claim 9, wherein said etchant contains a chlorine-based compound, or as described in claim 12, the first and third IIs.
The IV group compound semiconductor layer is made of GaAs, and
III-V compound semiconductor layer of InGaP
Wherein the first and third etchants consists of a mixture of HF and H ₂ O ₂ and H ₂ O, the manufacturing method of the fourth etchant semiconductor device according to claim 10, characterized in that it comprises a chlorine-based compound Or a first III-V compound semiconductor layer and a second, III-V compound having a different composition formed on the first compound semiconductor layer, as described in claim 13. A semiconductor layer;
A third III-V compound semiconductor layer formed on
In the method for etching a semiconductor laminated structure including lamination with a III-V compound semiconductor layer having a composition different from that of the second III-V compound semiconductor layer, the third II
The group IV compound semiconductor layer is formed by the first etchant.
Forming a first opening in the third group III-V compound semiconductor layer by etching until the second group III-V compound semiconductor layer is exposed; and forming the second opening in the third group III-V compound semiconductor layer.
Etching the III-V compound semiconductor layer with a second etchant having a composition different from that of the first etchant until the first III-V compound semiconductor layer is exposed; Forming a second opening corresponding to the first opening in the III-V compound semiconductor layer; and forming the first III-V compound semiconductor layer with respect to the second etchant. Etching with a third etchant having a different composition, the first II
Forming a third opening corresponding to the first opening in the group IV compound semiconductor layer;
After the step of etching the II-V compound semiconductor layer, the step of etching the second III-V compound semiconductor layer projecting between the first opening and the third opening. 15. The second group III-V projecting between the first opening and the third opening by an etching method comprising: or as described in claim 14, 16. The method according to claim 13, wherein the step of etching the compound semiconductor layer is performed using the second etchant. Etching the second III-V compound semiconductor layer projecting between the second etchant and the third opening in the fourth etchant having a composition different from that of the second etchant. 14. The method according to claim 13, wherein the first and third group III-V compound semiconductor layers contain P by using an etching method. And the second III-V compound semiconductor layer contains P. The method according to claim 13, wherein the first and third group-III compound semiconductor layers contain P. The III-V compound semiconductor layer is made of GaAs, and the second III-V compound semiconductor layer is made of InG.
aP, and the first and third etchants are H
Becomes a mixture of F and H ₂ O ₂ and H ₂ O, the second etchant by etching method according to claim 14, wherein the chlorine-containing compound or claim 18,
As described in the above, the first and third III-V compound semiconductor layers are made of GaAs, and the second III-V compound semiconductor layer is made of GaAs.
The -V group compound semiconductor layer is made of InGaP;
20. The etching method according to claim 19, wherein the third etchant comprises a mixture of HF, H ₂ O ₂ and H ₂ O, and the fourth etchant contains a chlorine-based compound. As described in the above, the chlorine-based compound is HCl, or an aqueous solution containing HCl and phosphoric acid, or HCl and phosphoric acid and hydrogen peroxide,
Alternatively, Cl ₂ , SiCl ₄ or BCl ₃ and N ₂
And a mixture of CHF ₃ , CF ₄ and SF ₆ by the etching method according to any one of claims 13 to 17, or as described in claim 20. In the method of manufacturing a semiconductor device on a compound semiconductor substrate, a conductor pattern is formed on a first surface of the compound semiconductor substrate along an element isolation region.
Forming the conductive pattern so as to define an element region on the first surface; and forming a groove corresponding to the element isolation region on a second opposed surface of the compound semiconductor substrate. Forming a groove by etching so that the groove reaches the first surface and exposing the conductor pattern; and removing the exposed conductor pattern. 21. The method according to claim 20, further comprising the step of forming an electrode pattern on the element region substantially simultaneously with the step of forming the conductor pattern. According to a method for manufacturing a semiconductor device, or as described in claim 22, further, simultaneously with the step of forming the groove, on the second surface of the compound semiconductor substrate, An opening is formed so as to expose the electrode pattern, the opening is formed to penetrate from the second surface to the first surface, and a back electrode is formed on the compound semiconductor substrate so as to fill the opening. 22. The method as claimed in claim 20, wherein the second surface is formed on the second surface.
24. The method of manufacturing a semiconductor device according to claim 23.
And forming an active element on the first surface of the compound semiconductor substrate by using an electron beam drawing technique after the step of forming the conductor pattern and before the etching step. 21. The method according to claim 20, wherein
25. The method of manufacturing a semiconductor device according to claim 24.
As described in the above, the compound semiconductor substrate includes a first III-V compound semiconductor layer substantially free of P, and a second III-V compound semiconductor layer formed on the first compound semiconductor layer and including P. -V group compound semiconductor layer and the second III-V
Forming a groove on the third group III-V compound semiconductor layer formed on the group III compound semiconductor layer, the third group III-V compound semiconductor layer containing substantially no P; The layer is applied to the second II by a first etchant.
Etching the group III-V compound semiconductor layer until the group III-V compound semiconductor layer is exposed, and exposing the exposed group III-V compound semiconductor layer to the first group III-V compound semiconductor by a different etchant of a second composition. Etching until the layer is exposed; etching the first group III-V compound semiconductor layer with an etchant having a different composition from the third and second etchants; Etching the group III-V compound semiconductor layer, wherein the method of manufacturing a semiconductor device according to any one of claims 20 to 24,
Or, as described in claim 25, the second III
27. The method of manufacturing a semiconductor device according to claim 24, wherein the step of etching the -V group compound semiconductor layer is performed by the second etchant, or as described in claim 26, 25. The method of manufacturing a semiconductor device according to claim 24, wherein the step of etching the second III-V compound semiconductor layer is performed by a fourth etchant having a different composition from the second etchant. ,Solve. According to the first aspect of the present invention, a relative recess is formed on the substrate, and the lower portion of the capacitor forming a part of the MMIC is a relative recess. The lower electrode is formed so as to extend to the outside of the concave portion, and a dielectric film and an upper electrode are sequentially formed on the lower electrode in the concave portion, so that the height of the upper electrode and the outside of the concave portion are reduced. Can be configured such that the heights of the lower electrodes are substantially equal. For this reason, the depth of the contact hole when the conductor pattern is contacted to the lower electrode through the contact hole outside the concave portion is the same as the depth when the conductor pattern is contacted to the upper electrode through the contact hole. Thus, the problem that the inductance of the conductor pattern deviates from the design value depending on the depth of the contact hole is solved.

According to the second feature of the present invention, a recess or a through hole is formed by etching in a stacked semiconductor structure including at least the first to third compound semiconductor layers. In this case, when the first and third compound semiconductor layers containing no P are etched with a normal HF-based etchant and only the second compound semiconductor layer containing P is etched with a chlorine-based etchant,
The problem that the second compound semiconductor layer forms an overhang in the concave portion or the through hole is solved by etching again using the chlorine-based etchant after the concave portion or the through hole is formed. Problems such as disconnection of the conductor pattern formed in the recess or through hole due to such overhang are avoided.

Further, according to the present invention, an active element is formed on a compound semiconductor substrate by an electron beam lithography technique, and the compound semiconductor substrate is divided into individual chips by etching. In addition, by forming a conductor pattern on the compound semiconductor substrate along the element isolation region, the problem of charge-up of the substrate due to electron beam irradiation and the problem of pattern deformation accompanying the problem are solved. Further, by etching the substrate corresponding to the element isolation region from the back surface side and removing the conductor pattern exposed as a result of the etching, a very fine high-speed semiconductor device can be obtained.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIGS.
(C), FIGS. 2 (D) to (E) and FIGS. 3 (F) to (H)
3 shows a manufacturing process of the semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1A, a recess 21A is formed on a semi-insulating GaAs substrate 21 including an AlGaAs layer (not shown) by wet etching using an etchant composed of a mixture of HF, H ₂ O ₂ and H ₂ O. 1 (A), and SiO _{2 is formed} on the structure of FIG. 1 (A) in the process of FIG. 1 (B).
A film 22 is formed by a CVD method so as to cover the recess 21A, and a lower electrode layer 23 having an Au / Ti structure is formed on the structure of FIG. It is formed so as to cover the recess 21A. Further, in the step of FIG. 2D, Si is added on the structure of FIG.
An N film 24 is formed by sputtering or a CVD method so as to cover the recess 21A.
In the step of (E), the SiN film 24 in the structure of FIG.
The upper electrode 25 is formed in the portion covering the recess 21A. In the step of FIG. 1A, the composition of the etchant is
Generally, the etching rate when applied to a GaAs layer or an AlGaAs layer is set to be about 100 nm / min.

Next, in the step of FIG. 3F, the SiO ₂ film 22, the lower electrode layer 23 and the SiN film 24 are patterned to form a capacitor comprising the SiO ₂ pattern 22A, the lower electrode 23A and the SiN capacitor dielectric film 24A. C is formed on the substrate 21. Further, the next FIG.
In the step, the gate electrode 26 and the source / drain electrodes 27A,
An active element such as a HEMT or MESFET having 27B is formed. In the step of FIG. 3F, the lower electrode pattern 23A of the capacitor C is
It is formed so as to extend outside A, that is, on the main surface of the substrate 21. In the lower electrode layer 23, the SiN film 24 and the upper electrode 25, the upper main surface of the upper electrode 25 is formed by the concave portion 21A of the lower electrode pattern 23A.
The thickness is set so as to be substantially the same height as the upper main surface of the portion extending to the outside.

The structure shown in FIG. 3G is then covered with an interlayer insulating film 28 made of a SiO ₂ film or the like in the step shown in FIG.
Further, a contact hole 2 exposing the upper electrode 25 and the lower electrode pattern 23A in the interlayer insulating film 28.
8A and 28B are formed respectively. However, the contact hole 28B is formed in the lower electrode pattern 23A.
A portion located outside the concave portion 21A is exposed. Further, in the step of FIG. 3G, wiring patterns 29A and 29B are formed on the interlayer insulating film 28 so as to contact the upper electrode 25 and the lower electrode pattern 23A via the contact holes 28A and 28B, respectively. .

FIG. 4 schematically shows a part of the capacitor C shown in FIG. However, in FIG. 4, SiO ₂ pattern 22
A is not shown. Referring to FIG. 4, in the capacitor C according to the present embodiment, the upper surface of the upper electrode 25 is at substantially the same level as the upper surface of the lower electrode pattern 23A outside the recess 21A, and as a result, the depth of the contact hole 28A is reduced. is L ₃ depth of the contact hole 28B L ₄
Are substantially equal. Therefore, the inductance of the wiring pattern 29A filling the contact hole 28A is substantially equal to the inductance of the wiring pattern 29B filling the contact hole 28B. Therefore, the optimum semiconductor device designed by CAD and the actual device can be used. Differences in operating characteristics due to differences in contact hole depth, especially between contact holes, are minimized.

In the configuration shown in FIG. 4, the lower electrode pattern 23A extends outside the recess 21A.
Although the inductance is increased by that amount, the area of the lower electrode pattern 23A is smaller than that of the contact hole 28A or 2A.
It is much larger than the cross-sectional area of 8B, and therefore has a lower current density. Therefore, the concave portion 2 of the lower electrode pattern 23A is formed.
The increase in inductance due to the extension outside 1A is negligible. [Second Embodiment] By the way, when the concave portion 21A is formed on the compound semiconductor substrate 21 by etching in the process of FIG.
Since the semiconductor layer has a laminated structure of compound semiconductor layers having different compositions, it is necessary to perform such etching while switching the etchant in accordance with the composition of the compound semiconductor layer. In particular, in recent high-speed semiconductor devices, InGa
There is a tendency to use a compound semiconductor layer containing P as a group V element, such as P, InP or GaP, but such a compound semiconductor layer containing P is an effective etchant for a compound semiconductor layer containing no P such as GaAs or AlGaAs. If used, the etching rate will be significantly reduced.

FIGS. 5A to 5D show such InGaP
1 is obtained by etching a stacked compound semiconductor structure including
A conventional process for forming a recess corresponding to the recess 21A of FIG.
Show the process. Referring to FIG. 5A, the GaAs substrate 31
An InGaP layer 32 is formed thereon, and the InG
Another GaAs layer 33 is formed on the aP layer 32.
You. In the step of FIG. 5B, on the GaAs layer 33,
Is formed with a resist film 34 having an opening 34A.
Using the resist film 34 as a mask, HF and H_TwoO_TwoAnd H _Two
Wet etch using an etchant consisting of a mixture of O
The opening 33A is formed in the GaAs layer 33 by the
Formed so that the InGaP layer 32 thereunder is exposed.
I do.

Next, in the step of FIG. 5C, the GaAs having the resist film 34 and the opening 33A formed therein is formed.
Using the s layer 33 as a mask, Cl ₂ , SiCl ₄ and BCl
And Cl compound selected from any of the _3, and N _2, C
A dry etching method using an etchant gas comprising a mixture of an F compound selected from HF ₃ , CF ₄ and SF ₆ , or HCl, HCl and phosphoric acid, or HCl, phosphoric acid and hydrogen peroxide are used. The InGaP layer 32 is etched by a wet etching method containing Cl such as an aqueous solution containing GaAs.
An opening 32A exposing the substrate 31 is formed. that time,
When the wet etching method is applied, GaAs is used.
The GaAs layer 33 remains without being etched because the etching rate of the GaAs layer 33 is extremely low.

Next, in the step of FIG.
The wet etching process is performed again using the etchant used when etching the aAs layer 33, and the Ga
A recess 31A is formed in the As substrate 31. In the etching step of FIG. 5D, the InGaP layer 32 is not substantially etched, but the GaAs layer 33 is etched. As a result, the opening 33A is enlarged, so that the InGaP layer 32 is located in the recess. An overhang projecting from one side is formed. When such an overhang is formed at the stage of FIG. 1A, FIG.
The lower electrode pattern 23A extending to the outside of the recess along the side wall surface of the recess 21A shown in FIG.
Such overhangs may fall off during the manufacturing process of the semiconductor device and form impurity particles. Further, when such an overhang exists, the conductor film deposited thereunder is difficult to remove when patterning is performed, and there is a risk of causing a short circuit.

FIGS. 6A to 6C and FIGS.
(E) shows a method of forming a concave portion in a compound semiconductor substrate according to a second embodiment of the present invention, which solves the above-mentioned problem.
However, the parts described above are given the same reference numerals,
Description is omitted. Referring to the drawings, FIGS.
The steps up to (D) are substantially the same as the steps up to FIG. 5 (A) to FIG. 5 (D).
Although a structure in which the InGaP layer 32 corresponding to (D) forms an overhang is obtained, in this embodiment, FIG.
In the step (E), the overhang due to the InGaP layer 32 is removed by performing a wet etching step used in the step of FIG.

By using the steps shown in FIGS. 6A to 7E, the recess 21A shown in FIG. 1A can be overhanged even if the compound semiconductor substrate 21 contains an InGaP layer. Can be formed on the substrate 21 without forming. 6 (A) to FIG.
The step (E) is effective not only when forming a concave portion on a compound semiconductor substrate but also when forming a through-hole described below as a third embodiment. [Third Embodiment] FIGS. 8 (A) to 8 (E) and FIGS. 9 (F) to 9 (F)
(H) and FIGS. 10 (I) to (K) show the steps of manufacturing the compound semiconductor device according to the third embodiment of the present invention.

Referring to FIG. 8A, semi-insulating GaAs
An etching mask 42 such as a resist pattern is formed on the surface of the s substrate 41, and the surface of the GaAs substrate 41 is etched by a wet etching method using an etchant composed of a mixture of HF, H ₂ O ₂ and H ₂ O. Then, a concave portion 41A is formed in a portion where the source or drain electrode is formed. Further, as a result of the wet etching, a concave portion 41B is further formed on a portion of the substrate 41 corresponding to the scribe line.

In particular, when the substrate 41 is made of P such as InGaP,
When a semiconductor layer containing a group 4 element is included, the recess 4
1A is formed by the steps described above with reference to FIGS. 6A to 7D so that the recess 41A cuts the P-containing semiconductor layer. Next, in the step of FIG.
A source or drain electrode 43 is formed on the surface of the substrate 41 by lift-off corresponding to A, and a conductor pattern 43A is formed corresponding to the recess 41B, that is, along a scribe line on the semiconductor substrate. Further, in the step of FIG. 8C, a thickness of 1000 to 50 is formed on the surface side of the structure of FIG.
A gate electrode 44 of 0 nm is formed by lift-off. The electrode 43 and the conductor pattern 43A have a thickness of 1
N to a thickness of 50 to 5 nm on an Au film of 00 to 500 nm
an i-film is deposited, and a thickness of 100 to 1
A Au / Ni /
It has an AuGe structure. By the step of FIG. 8C, a semiconductor device is formed on the front surface side of the substrate 41.

In this embodiment, the semi-insulating GaAs
Since the conductive pattern 43A is formed along the scribe line on the surface of the substrate 41,
Even if the electron beam is irradiated thereon, the electric charge is dissipated along the conductor pattern 43A, and there is no problem that the GaAs substrate 41 is charged up or a pattern drawn by the charge up is deformed.

Next, in the step of FIG. 8D, a wiring pattern 45 is formed on the source or drain electrode 43, and the substrate is turned upside down in the step of FIG. The surface side on which the semiconductor device is formed is coated with a protective film 46 such as a resist film or wax.
And lapping and polishing the back surface of the substrate 41 to reduce the thickness of the substrate 41 to a range of 20 to 100 μm. In this embodiment, FIG.
In the step (F), the resist pattern (not shown) formed on the back surface of the substrate 41 is used as a mask to form the H
An opening 41C for exposing the electrode 43 and an opening 41D for exposing the conductive pattern 43A by a wet etching method using an F-based etchant or a well-known etchant made of a mixture of nitric acid, ammonia and hydrogen peroxide. Is formed so as to extend from the back side of the GaAs substrate 41 to the front side. The GaAs
Even when the s substrate 41 includes a compound semiconductor layer containing P such as InGaP as described in the previous embodiment, the recess 41A or 41B is first formed in the recess 41A or 41B in the step of FIG.
In the case where the openings 41C and 41D are formed below the compound semiconductor layer including
It can be performed by a wet etching process of aAs.

Next, in the step of FIG.
A thin conductor film 47, for example, an Au film having a thickness of 50 to 500 nm is uniformly deposited on the back surface side of the structure of (F) by sputtering or vacuum vapor deposition, and is further formed on the conductor film 17 in the opening 41D. Correspondingly, a resist pattern 48 is formed, and in the step of FIG.
Using the 8D as a mask, an Au layer 49 is formed on the conductive film 47 by electrolytic plating to a thickness of 10 to 15 μm, also serving as a heat sink and a ground electrode of the semiconductor device.

Next, in the step of FIG. 10I, the resist pattern 48 is removed, and the opening 41 is further removed.
The thin Au film 47 covering D is removed with a cyan-based etchant, and further, the etching with the cyan-based etchant is continued in the step of FIG. 10J to dissolve and remove the conductive pattern 43A. In this step, the Au layer 49
Is also slightly etched, but is not removed by etching because of its original thickness.

Further, by removing the organic protective film 46 in the step of FIG. 10K, a semiconductor device divided into individual chips can be obtained. The semiconductor device obtained in the step of FIG. 10K has a source electrode connected to the ground electrode on the back surface via the through hole in the substrate 41 at the shortest distance, and has a structure suitable for the MMIC used in the microwave band. Having. Fourth Embodiment FIG. 11 shows a structure of a semiconductor device according to a fourth embodiment of the present invention corresponding to a modification of the first embodiment of the present invention described above. However, the same reference numerals are given to the parts described above, and the description will be omitted.

Referring to FIG. 11, in this embodiment, instead of forming the recess 21A on the GaAs substrate 21, the protrusion 21B is formed by selective growth of GaAs in this embodiment.
The lower electrode is configured to extend over the projection 21B. With such a configuration, the depth L ₃ of the contact hole 28A and the depth L of the contact hole 28B can be reduced.
₄ can be made substantially equal.

The other features of this embodiment are clear from the above description, and the description is omitted. As described above, the present invention
Alternatively, the present invention is applied to a field effect transistor such as a MESFET, but the present invention is also useful for a bipolar transistor such as an HBT. As described above, the present invention has been described with reference to the preferred embodiments. However, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the claims.

[0032]

According to the first aspect of the present invention, a relative concave portion is formed on the substrate, and the lower electrode of the capacitor forming a part of the MMIC is applied to the relative concave portion. A concave portion, the lower electrode is formed so as to extend to the outside of the concave portion, and a dielectric film and an upper electrode are sequentially formed on the lower electrode in the concave portion, so that the height of the upper electrode and the The height of the lower electrode outside the concave portion can be configured to be substantially equal. For this reason, the depth of the contact hole when the conductor pattern is contacted to the lower electrode through the contact hole outside the concave portion is the same as the depth when the conductor pattern is contacted to the upper electrode through the contact hole. Thus, the problem that the inductance of the conductor pattern deviates from the design value depending on the depth of the contact hole is solved.

According to the second feature of the present invention, a recess or a through hole is formed by etching in a stacked semiconductor structure including at least the first to third compound semiconductor layers. In this case, when the first and third compound semiconductor layers containing no P are etched with a normal HF-based etchant and only the second compound semiconductor layer containing P is etched with a chlorine-based etchant,
The problem that the second compound semiconductor layer forms an overhang in the concave portion or the through hole is solved by etching again using the chlorine-based etchant after the concave portion or the through hole is formed. Problems such as disconnection of the conductor pattern formed in the recess or through hole due to such overhang are avoided.

According to a further feature of the present invention, an active element is formed on a compound semiconductor substrate by an electron beam lithography technique, and the compound semiconductor substrate is divided into individual chips by etching. In addition, by forming a conductor pattern on the compound semiconductor substrate along the element isolation region, the problem of charge-up of the substrate due to electron beam irradiation and the problem of pattern deformation accompanying the problem are solved. Further, by etching the substrate corresponding to the element isolation region from the back surface side and removing the conductor pattern exposed as a result of the etching, a very fine high-speed semiconductor device can be obtained.

[Brief description of the drawings]

1 (A) to 1 (C) show M according to a first embodiment of the present invention.
FIG. 6 is a diagram (No. 1) for explaining the MIC manufacturing process.

FIGS. 2D to 2E show M according to a first embodiment of the present invention;
FIG. 9 is a diagram (part 2) for explaining the MIC manufacturing process.

3 (F) to 3 (H) show M according to a first embodiment of the present invention.
FIG. 11 is a diagram (No. 3) explaining the process of manufacturing the MIC.

FIG. 4 is a diagram illustrating an effect of the invention in the MMIC according to the first embodiment of the present invention.

FIGS. 5A to 5D are diagrams illustrating a process of forming a concave portion on a compound semiconductor substrate by conventional wet etching.

FIGS. 6A to 6C are diagrams (part 1) illustrating a process of forming a concave portion on a compound semiconductor substrate according to a second embodiment of the present invention.

FIGS. 7 (D) to 7 (E) are diagrams illustrating a step of forming a concave portion on a compound semiconductor substrate according to a second embodiment of the present invention (part 2).

FIGS. 8A to 8E are diagrams (part 1) illustrating the steps of manufacturing the compound semiconductor device according to the third embodiment of the present invention.

FIGS. 9 (F) to 9 (H) are views (No. 2) showing the steps of manufacturing the compound semiconductor device according to the third embodiment of the present invention.

FIGS. 10A to 10K are diagrams (No. 3) showing the steps of manufacturing the compound semiconductor device according to the third embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration of an MMIC according to a fourth embodiment of the present invention.

12A to 12C are diagrams (part 1) for explaining a conventional MMIC manufacturing process.

13 (D) to 13 (E) are views for explaining a conventional MMIC manufacturing process (part 2).

FIGS. 14 (F) to (G) are diagrams (part 3) for explaining a conventional MMIC manufacturing process.

FIG. 15 is a diagram illustrating a problem of the conventional MMIC.

[Explanation of symbols]

11, 21, 31, 41 Substrate 11A, 21A, 31A, 41A, 41B Concave portion 12, 22 Insulating film 21B Selective growth region 22A Insulating film pattern 13, 23 Lower electrode 23A Lower electrode pattern 14, 24 Dielectric film 24A Dielectric film Pattern 15, 25 Upper electrode 16, 26 Gate electrode 17A, 17B, 27A, 27B Source / drain electrode 18, 28 Interlayer insulating film 18A, 18B, 28A, 28B Contact hole 19A, 19B, 29A, 29B Wiring pattern 32 InGaP layer 33 GaAs layer 32A, 33A opening 34 resist 34A resist opening 41C, 41D substrate opening 42 mask 43 source / drain electrode 43A conductive pattern 44 gate electrode 45 wiring pattern 46 protective film 47 conductive film 48 resist pattern 4 9 Au electrode layer

Claims (26)

[Claims] 1. A semiconductor device comprising a substrate and a capacitor formed on the substrate, wherein the capacitor has a lower electrode formed at a first height level on the substrate, and a lower electrode formed on the lower electrode. A dielectric film formed thereon, and an upper electrode formed on the dielectric film, wherein the lower electrode has a second height higher than the first height level.
A semiconductor device extending up to a height level. 2. The lower electrode is formed in a concave portion formed on the surface of the substrate, extends along the side wall surface defining the concave portion to the outside of the concave portion, and the second electrode outside the concave portion. 2. The semiconductor device according to claim 1, wherein the semiconductor device is located at a level of. 3. The semiconductor device according to claim 1, wherein said upper electrode is located at substantially the same level as said second level. 4. An interlayer insulating film on the substrate to cover the capacitor, wherein the interlayer insulating film exposes a first contact hole exposing the upper electrode and a lower electrode of the second level. A second conductor hole that contacts the upper electrode via the first contact hole, and a second conductor hole on the interlayer insulating film via the second contact hole. And a second conductor pattern which is in contact with said lower electrode is formed.
The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein a projection having the second height level is formed on the substrate, and the lower electrode extends to the projection. 6. A method for manufacturing a semiconductor device comprising a substrate and a capacitor formed on the substrate, wherein a step of forming a recess on the surface of the substrate by etching, and extending over the recess to outside the recess. Forming a lower electrode of the capacitor so as to be present; forming a dielectric film of the capacitor on the lower electrode; and forming an upper electrode of the capacitor on the dielectric film corresponding to the recess. Forming a semiconductor device. 7. A step of forming an interlayer insulating film on the substrate so as to fill the capacitor, and forming a first opening in the interlayer insulating film exposing the upper electrode and a lower portion outside the recess. Forming a second opening exposing the electrode. 8. The first group III-V compound semiconductor layer substantially free of P and the second group III-V compound formed on the first compound semiconductor layer and containing P The step of forming the recess includes a stack of a semiconductor layer and a third III-V compound semiconductor layer formed on the second III-V compound semiconductor layer and substantially not containing P. Etching the third III-V compound semiconductor layer with a first etchant until the second III-V compound semiconductor layer is exposed; and exposing the second III-V compound semiconductor layer Etching the layer with a different etchant of a second composition until the first III-V compound semiconductor layer is exposed;
Etching the first group III-V compound semiconductor layer with an etchant having a third composition different from that of the second etchant;
8. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of etching the group V compound semiconductor layer. 9. The method according to claim 8, wherein the step of etching the second III-V compound semiconductor layer is performed by the second etchant. 10. The method according to claim 8, wherein the step of etching the second III-V compound semiconductor layer is performed by a fourth etchant having a composition different from that of the second etchant. Of manufacturing a semiconductor device. 11. The first and third III-V compound semiconductor layers are made of GaAs, and the second III-V compound semiconductor layer is made of GaAs.
The group V compound semiconductor layer is made of InGaP, the first and third etchants are made of a mixture of HF, H ₂ O ₂ and H ₂ O, and the second etchant contains a chlorine compound. A method for manufacturing a semiconductor device according to claim 9. 12. The first and third III-V compound semiconductor layers are made of GaAs, and the second III-V compound semiconductor layer is made of GaAs.
The group V compound semiconductor layer is made of InGaP, the first and third etchants are made of a mixture of HF, H ₂ O ₂ and H ₂ O, and the fourth etchant contains a chlorine-based compound. A method for manufacturing a semiconductor device according to claim 10. 13. A first group III-V compound semiconductor layer, and a second group III-V compound semiconductor layer formed on the first compound semiconductor layer.
III-V compound semiconductor layers having different compositions;
A semiconductor including a third layer formed on the second III-V compound semiconductor layer and having a composition different from that of the second III-V compound semiconductor layer. In the method for etching a laminated structure, the third III-V compound semiconductor layer is etched with a first etchant until the second III-V compound semiconductor layer is exposed, thereby forming the third III-V compound semiconductor layer. Forming a first opening in the group V compound semiconductor layer; and exposing the exposed second III-V compound semiconductor layer with a second etchant having a different composition from the first etchant. Etching until the first III-V compound semiconductor layer is exposed, and etching the second III-V compound semiconductor layer.
Forming a second opening corresponding to the first opening in the group V compound semiconductor layer; and forming the first III-V compound semiconductor layer in a composition with respect to the second etchant. Etching with a different third etchant to form a third opening corresponding to the first opening in the first group III-V compound semiconductor layer; After the step of etching the group V compound semiconductor layer, the first opening and the third
The second III projecting between the second III
Etching the group V compound semiconductor layer. 14. The step of etching the second III-V compound semiconductor layer projecting between the first opening and the third opening, using the second etchant. 2. The method according to claim 1, wherein the step is executed.
3. The etching method according to 3. 15. The step of etching the second III-V compound semiconductor layer protruding between the first opening and the third opening, wherein the second etchant has a composition different from that of the second etchant. 14. The etching method according to claim 13, wherein the etching method is performed by using a different fourth etchant. 16. The first and third III-V compound semiconductor layers do not substantially contain P, and the second III-V compound semiconductor layer does not contain P.
The etching method according to claim 13, wherein the -V group compound semiconductor layer contains P. 17. The semiconductor device according to claim 17, wherein said first and third group III-V compound semiconductor layers are made of GaAs.
The group V compound semiconductor layer is made of InGaP, the first and third etchants are made of a mixture of HF, H ₂ O ₂ and H ₂ O, and the second etchant contains a chlorine compound. The etching method according to claim 14. 18. The semiconductor device according to claim 18, wherein said first and third III-V compound semiconductor layers are made of GaAs.
The group V compound semiconductor layer is made of InGaP, the first and third etchants are made of a mixture of HF, H ₂ O ₂ and H ₂ O, and the fourth etchant contains a chlorine-based compound. The etching method according to claim 15. 19. The chlorine-based compound may be HCl, or an aqueous solution containing HCl and phosphoric acid, or HCl and phosphoric acid and hydrogen peroxide, or Cl ₂ , SiCl ₄ or BCl ₃ , N ₂ , CHF ₃ , CF ₄ and SF
The etching method of any one of claims 13 to 17, characterized in than becomes that a mixture of any one of _6. 20. A method of manufacturing a semiconductor device on a compound semiconductor substrate, wherein a conductive pattern is formed on a first surface of the compound semiconductor substrate along an element isolation region, and the conductive pattern is formed on the first surface of the compound semiconductor substrate. Forming a device region so as to define the device region; and forming a groove corresponding to the device isolation region on a second opposing surface of the compound semiconductor substrate, the groove reaching the first surface. A method of manufacturing a semiconductor device, comprising: forming a conductive pattern by etching so as to expose the conductive pattern; and removing the exposed conductive pattern. 21. The method according to claim 20, further comprising the step of forming an electrode pattern on the element region substantially simultaneously with the step of forming the conductor pattern. 22. Simultaneously with the step of forming the groove, an opening is formed on the second surface of the compound semiconductor substrate so as to expose the electrode pattern, and the opening is formed on the second surface. 22. The semiconductor device according to claim 20, wherein a back electrode is formed on the second surface of the compound semiconductor substrate so as to fill the opening from the first surface to the second surface. A method for manufacturing a semiconductor device. 23. A step of forming an active element on the first surface of the compound semiconductor substrate using an electron beam drawing technique after the step of forming the conductor pattern and before the etching step. 21. The method of manufacturing a semiconductor device according to claim 20, wherein: 24. A compound semiconductor substrate comprising: a first group III-V compound semiconductor layer substantially free of P; and a second I-type layer formed on the first compound semiconductor layer and containing P.
The trench including a stack of a II-V compound semiconductor layer and a third III-V compound semiconductor layer formed on the second III-V compound semiconductor layer and substantially not containing P; Forming the third III-V compound semiconductor layer with the first III-V compound semiconductor layer using a first etchant.
Etching the group III-V compound semiconductor layer until the second group III-V compound semiconductor layer is exposed, and exposing the second group III-V compound semiconductor layer to the first group III-V compound semiconductor layer with an etchant having a second composition different from the first group III-V compound semiconductor layer. Etching the first III-V compound semiconductor layer with an etchant having a different composition from the third and the second etchant; and etching the second III-V compound semiconductor layer. 25. The method of manufacturing a semiconductor device according to claim 20, further comprising: a step of etching the group V compound semiconductor layer. 25. The method according to claim 24, wherein the step of etching the second III-V compound semiconductor layer is performed by the second etchant. 26. The method according to claim 24, wherein the step of etching the second III-V compound semiconductor layer is performed by a fourth etchant having a composition different from that of the second etchant. Of manufacturing a semiconductor device.