JPH11274334A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11274334A JPH11274334A JP7688098A JP7688098A JPH11274334A JP H11274334 A JPH11274334 A JP H11274334A JP 7688098 A JP7688098 A JP 7688098A JP 7688098 A JP7688098 A JP 7688098A JP H11274334 A JPH11274334 A JP H11274334A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- semiconductor device
- mark
- insulating film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特に、配線基板の表裏面のうちの表面側に半導体チ
ップが設けられ、裏面側に複数の外部接続用端子が設け
られたパッケージ構造を有する半導体装置に適用して有
効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a package structure in which a semiconductor chip is provided on a front surface of a wiring substrate and a plurality of external connection terminals are provided on the back surface. The present invention relates to a technology effective when applied to a semiconductor device having the same.
【０００２】[0002]
【従来の技術】半導体装置として、ＢＧＡ(Ｂall Ｇrid
Ａrray)型の半導体装置が知られている。このＢＧＡ型
半導体装置は、配線基板の表裏面のうちの表面側に半導
体チップが設けられ、裏面側に複数の外部接続用端子が
設けられたパッケージ構造になっている。2. Description of the Related Art As a semiconductor device, BGA (B all G rid
( Array) type semiconductor devices are known. This BGA type semiconductor device has a package structure in which a semiconductor chip is provided on the front side of the front and back surfaces of a wiring board, and a plurality of external connection terminals are provided on the back side.
【０００３】半導体チップは、表裏面のうち、電極パッ
ド(ボンディングパッド)が形成された表面(回路形成面)
を上向きにした状態で配線基板の表面のチップ塔載領域
上に塔載され、配線基板の表面上に形成された樹脂封止
体によって封止されている。半導体チップの電極パッド
は、導電性のワイヤを介して、配線基板の表面に形成さ
れたワイヤ接続用の電極パッド(ランド端子)と電気的に
接続されている。A semiconductor chip has a front surface (circuit forming surface) on which an electrode pad (bonding pad) is formed on the front and back surfaces.
Is mounted on the chip mounting area on the surface of the wiring substrate with the substrate facing upward, and is sealed by a resin sealing body formed on the surface of the wiring substrate. The electrode pads of the semiconductor chip are electrically connected to wire-connecting electrode pads (land terminals) formed on the surface of the wiring board via conductive wires.
【０００４】外部接続用端子は、半田材からなる球形状
の半田バンプで形成され、配線基板の裏面に形成された
バンプ接続用の電極パッド(ランド端子)に電気的にかつ
機械的に接続されている。外部接続用端子は、実装基板
上に半導体装置を実装する際、実装基板の電極パッドに
電気的にかつ機械的に接続される。配線基板のワイヤ接
続用電極パッド、バンプ接続用電極パッドの夫々は、配
線基板に形成された配線を介して互いに電気的に接続さ
れている。The external connection terminals are formed of spherical solder bumps made of a solder material and are electrically and mechanically connected to bump connection electrode pads (land terminals) formed on the back surface of the wiring board. ing. The external connection terminals are electrically and mechanically connected to the electrode pads of the mounting board when the semiconductor device is mounted on the mounting board. Each of the electrode pads for wire connection and the electrode pads for bump connection of the wiring board is electrically connected to each other via wiring formed on the wiring board.
【０００５】前記ＢＧＡ型半導体装置は、これに限定さ
れないが、配線基板の表面のチップ塔載領域上に接着剤
を介在して半導体チップを塔載し、その後、半導体チッ
プの電極パッドと配線基板のワイヤ接続用電極パッドと
をワイヤで電気的に接続し、その後、配線基板の表面上
に半導体チップ及びワイヤ等を封止する樹脂封止体を形
成し、その後、配線基板のバンプ接続用電極パッド上に
外部接続用端子である半田バンプを形成することによっ
て製造される。外部接続用端子である半田バンプは、配
線基板の裏面を上向きにした状態で、配線基板のバンプ
接続用電極パッド上に例えばＰｂ−Ｓｎ組成の半田球を
供給し、その後、半田球を溶融することによって形成さ
れる。[0005] The BGA type semiconductor device mounts a semiconductor chip on a chip mounting area on a surface of a wiring board with an adhesive interposed therebetween. Is electrically connected to the electrode pad for wire connection with a wire, and thereafter, a resin sealing body for sealing the semiconductor chip, the wire, and the like is formed on the surface of the wiring board, and then, the electrode for bump connection of the wiring board is formed. It is manufactured by forming solder bumps as external connection terminals on the pads. The solder bump serving as an external connection terminal supplies a solder ball having, for example, a Pb-Sn composition onto the bump connection electrode pad of the wiring board with the back surface of the wiring board facing upward, and then melts the solder ball. Formed by
【０００６】なお、ＢＧＡ型半導体装置については、例
えば特開平７−２７３２４６号公報に記載されている。The BGA type semiconductor device is described in, for example, Japanese Patent Application Laid-Open No. 7-273246.
【０００７】また、工業調査会発行の電子材料〔１９９
７年９月１日発行、第３４頁乃至第４０頁〕には、絶縁
性フィルムを基材とする配線基板を用いたＴ−ＢＧＡ
(Ｔape−Ｂall Ｇrid Ａrray）型半導体装置が記載され
ている。[0007] Also, an electronic material [199
Published on September 1, 1995, pages 34 to 40] describes a T-BGA using a wiring board having an insulating film as a base material.
(T ape- B all G rid A rray) type semiconductor device is described.
【０００８】[0008]
【発明が解決しようとする課題】ＢＧＡ型半導体装置に
おいて、樹脂封止体の上面の角部には装置の方向(向き)
を明確にするための目印(インデックス)が設けられてい
るので、樹脂封止体の上面側から装置を見た場合、装置
の方向を把握することができるが、配線基板の裏面には
方向(向き)を明確にするための目印(インデックス)が設
けられていないので、配線基板の裏面側から装置を見た
場合、装置の方向を把握することができない。In the BGA type semiconductor device, the direction (orientation) of the device is located at the corner of the upper surface of the resin sealing body.
When the device is viewed from the top side of the resin sealing body, the direction of the device can be grasped, but the direction ( Since a mark (index) for clarifying the direction is not provided, when the device is viewed from the back side of the wiring board, the direction of the device cannot be grasped.
【０００９】本発明の目的は、配線基板の裏面側から半
導体装置の方向(向き)を把握することが可能な技術を提
供することにある。An object of the present invention is to provide a technique capable of grasping the direction (direction) of a semiconductor device from the back side of a wiring board.
【００１０】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１１】[0011]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.
【００１２】配線基板の表裏面のうちの表面側に半導体
チップが設けられ、裏面側に複数の外部接続用端子が設
けられたパッケージ構造を有する半導体装置であって、
前記配線基板の裏面において、そのＸ方向の中心線及び
Ｙ方向の中心線によって四分割された四つの領域の夫々
に目印が設けられ、前記四つの領域のうち、一つの領域
に設けられた目印は他の領域に設けられた目印と異なっ
ている。前記一つの領域に設けられた目印は、前記配線
基板の表裏面に亘って形成された貫通孔で構成され、前
記他の領域に設けられた目印は、前記配線基板の表裏面
に亘って形成された貫通孔と、この貫通孔を塞ぐように
前記配線基板の表面に形成された閉塞体とで構成されて
いる。A semiconductor device having a package structure in which a semiconductor chip is provided on the front surface of the front and back surfaces of a wiring board, and a plurality of external connection terminals are provided on the back surface,
On the back surface of the wiring substrate, a mark is provided in each of four regions divided by a center line in the X direction and a center line in the Y direction, and a mark provided in one of the four regions. Is different from the marks provided in other areas. The mark provided in the one area is constituted by a through hole formed over the front and back surfaces of the wiring board, and the mark provided in the other area is formed over the front and back surfaces of the wiring board. And a closing body formed on the surface of the wiring board so as to close the through hole.
【００１３】上述した手段によれば、配線基板の裏面の
四つの領域のうちの一つの領域に設けられた目印によっ
て半導体装置の方向(向き)を明確にすることができるの
で、配線基板の裏面側から半導体装置の方向を把握する
ことができる。According to the above-described means, the direction (direction) of the semiconductor device can be clarified by the mark provided in one of the four regions on the back surface of the wiring board. The direction of the semiconductor device can be grasped from the side.
【００１４】[0014]
【発明の実施の形態】以下、本発明の構成について、Ｂ
ＧＡ型半導体装置に本発明を適用した実施の形態ととも
に説明する。なお、実施の形態を説明するための図面に
おいて、同一機能を有するものは同一符号を付け、その
繰り返しの説明は省略する。BEST MODE FOR CARRYING OUT THE INVENTION The structure of the present invention
A description will be given together with an embodiment in which the present invention is applied to a GA semiconductor device. In the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.
【００１５】図１は本発明の一実施形態であるＢＧＡ
(Ｂall Ｇrid Ａrray)型半導体装置の平面図であり、図
２は図１に示すＡ−Ａ線の位置で切った断面図であり、
図３は前記ＢＧＡ型半導体装置を構成する配線基板の平
面図であり、図４は前記ＢＧＡ型半導体装置の底面図で
あり、図５は図４の要部拡大底面図であり、図６は図５
に示すＢ−Ｂ線の位置で切った断面図であり、図７は図
５に示すＣ−Ｃ線の位置で切った断面図である。FIG. 1 shows a BGA according to an embodiment of the present invention.
Is a plan view of (B all G rid A rray) type semiconductor device, FIG. 2 is a sectional view taken along the position of line A-A shown in FIG. 1,
FIG. 3 is a plan view of a wiring board constituting the BGA type semiconductor device, FIG. 4 is a bottom view of the BGA type semiconductor device, FIG. 5 is an enlarged bottom view of a main part of FIG. 4, and FIG. FIG.
7 is a sectional view taken along the line BB shown in FIG. 7, and FIG. 7 is a sectional view taken along the line CC shown in FIG.
【００１６】図１及び図２に示すように、本実施形態の
半導体装置は、配線基板１の表裏面のうちの表面側に半
導体チップ２０が設けられ、裏面側に外部接続用端子と
して複数の半田バンプ２４が設けられたパッケージ構造
になっている。As shown in FIGS. 1 and 2, in the semiconductor device of this embodiment, a semiconductor chip 20 is provided on the front side of the front and back surfaces of the wiring board 1, and a plurality of external connection terminals are provided on the back side. It has a package structure in which solder bumps 24 are provided.
【００１７】前記半導体チップ２０は、例えば、単結晶
珪素からなる半導体基板及びこの半導体基板上に形成さ
れた多層配線層を主体とする構成になっている。半導体
チップ２０の平面形状は方形状で形成され、本実施形態
においては、８［ｍｍ］×８［ｍｍ］の正方形で形成さ
れている。The semiconductor chip 20 is mainly composed of, for example, a semiconductor substrate made of single crystal silicon and a multilayer wiring layer formed on the semiconductor substrate. The planar shape of the semiconductor chip 20 is formed in a square shape, and in the present embodiment, is formed as a square of 8 [mm] × 8 [mm].
【００１８】前記半導体チップ２０には、論理回路シス
テム、記憶回路システム、或いはそれらの混合回路シス
テム等が塔載されている。これらの回路システムは、半
導体基板に形成された半導体素子、多層配線層に形成さ
れた配線等によって構成されている。The semiconductor chip 20 includes a logic circuit system, a storage circuit system, a mixed circuit system thereof, and the like. These circuit systems are composed of a semiconductor element formed on a semiconductor substrate, wiring formed on a multilayer wiring layer, and the like.
【００１９】前記半導体チップ２０の表裏面のうちの表
面(回路形成面)には、半導体チップ２０の外周囲の各辺
に沿って配列された複数の電極パッド(ボンディングパ
ッド)２０Ａが形成されている。この複数の電極パッド
２０Ａの夫々は、多層配線層のうちの最上層の配線層に
形成され、回路システムを構成する半導体素子に配線を
介して電気的に接続されている。複数の電極パッド２０
Ａの夫々は、例えばアルミニウム(Ａｌ)膜若しくはアル
ミニウム合金膜で形成されている。A plurality of electrode pads (bonding pads) 20A arranged along each side of the outer periphery of the semiconductor chip 20 are formed on the front surface (circuit formation surface) of the front and back surfaces of the semiconductor chip 20. I have. Each of the plurality of electrode pads 20A is formed on the uppermost wiring layer of the multilayer wiring layer, and is electrically connected to a semiconductor element constituting a circuit system via a wiring. Multiple electrode pads 20
Each of A is formed of, for example, an aluminum (Al) film or an aluminum alloy film.
【００２０】前記半導体チップ２０は、電極パッド２０
Ａが形成された表面を上向きにした状態で配線基板１の
表面のチップ塔載領域に接着剤２１を介在して塔載さ
れ、配線基板１の表面上に形成された樹脂封止体２３に
よって封止されている。The semiconductor chip 20 includes an electrode pad 20
A is mounted on the chip mounting area on the surface of the wiring substrate 1 with the adhesive 21 interposed therebetween with the surface on which the A is formed facing upward, and the resin sealing body 23 formed on the surface of the wiring substrate 1 It is sealed.
【００２１】前記配線基板１は、例えば５０［μｍ］程
度の厚さの絶縁性フィルムを基材とする構成になってい
る。配線基板１の平面形状は方形状で形成され、本実施
形態においては１０［ｍｍ］×１０［ｍｍ］の正方形で
形成されている。The wiring board 1 has a configuration in which an insulating film having a thickness of, for example, about 50 [μm] is used as a base material. The planar shape of the wiring board 1 is formed in a square shape, and in this embodiment, is formed as a square of 10 [mm] × 10 [mm].
【００２２】前記配線基板１の表面には配線パターンが
形成されている。この配線パターンは、図２及び図３に
示すように、複数の電極パッド(ランド端子)４、複数の
配線５、複数の電極パッド(ランド端子)６及び複数の配
線７等を有するパターンで形成されている。電極パッド
４は配線５を介して電極パッド６と電気的に接続され、
電極パッド６は配線７と電気的に接続されている。これ
らの電極パッド４、配線５、電極パッド６及び配線７等
は、絶縁性フィルムの表面に接着層を介在して金属箔を
貼り付けた後、この金属箔にエッチング加工を施すこと
によって形成される。本実施形態では、金属箔として１
８［μｍ］程度の厚さの銅(Ｃｕ)箔が用いられている。
電極パッド４の平面形状は円形状で形成され、電極パッ
ド６の平面形状は方形状で形成されている。A wiring pattern is formed on the surface of the wiring board 1. As shown in FIGS. 2 and 3, the wiring pattern is formed by a pattern having a plurality of electrode pads (land terminals) 4, a plurality of wirings 5, a plurality of electrode pads (land terminals) 6, a plurality of wirings 7, and the like. Have been. The electrode pad 4 is electrically connected to the electrode pad 6 via the wiring 5,
The electrode pad 6 is electrically connected to the wiring 7. The electrode pad 4, the wiring 5, the electrode pad 6, the wiring 7, and the like are formed by attaching a metal foil to the surface of the insulating film with an adhesive layer therebetween, and then performing an etching process on the metal foil. You. In this embodiment, 1 is used as the metal foil.
A copper (Cu) foil having a thickness of about 8 [μm] is used.
The planar shape of the electrode pad 4 is formed in a circular shape, and the planar shape of the electrode pad 6 is formed in a square shape.
【００２３】前記複数の電極パッド４のうち、大半の電
極パッド４は配線基板１のチップ塔載領域に配置され、
残りの電極パッド４は配線基板１のチップ塔載領域を囲
む周辺領域に配置されている。電極パッド４は配線基板
１の表裏面に亘って形成された接続孔２を塞ぐように形
成され、その裏面には接続孔２を通して半田バンプ２４
が電気的にかつ機械的に接続されている。半田バンプ２
４は、例えば６３［重量％］Ｐｂ−３７［重量％］Ｓｎ
組成の金属材で形成されている。接続孔２の平面形状は
円形状で形成され、その平面サイズは電極パッド４の平
面サイズよりも小さい寸法で形成されている。接続孔２
は、絶縁性フィルムの表面に金属箔を貼り付けるための
接着層を形成した後、絶縁性フィルムの接続孔形成領域
に例えば打ち抜き加工若しくはレーザ加工を施すことに
よって形成される。Most of the plurality of electrode pads 4 are arranged in the chip mounting area of the wiring board 1,
The remaining electrode pads 4 are disposed in a peripheral area surrounding the chip mounting area of the wiring board 1. The electrode pad 4 is formed so as to cover the connection hole 2 formed over the front and back surfaces of the wiring board 1.
Are electrically and mechanically connected. Solder bump 2
4 is, for example, 63 [% by weight] Pb-37 [% by weight] Sn
It is formed of a metal material having a composition. The planar shape of the connection hole 2 is formed in a circular shape, and the planar size is formed smaller than the planar size of the electrode pad 4. Connection hole 2
Is formed by forming, for example, an adhesive layer for attaching a metal foil on the surface of an insulating film, and then performing, for example, punching or laser processing on a connection hole forming region of the insulating film.
【００２４】前記複数の電極パッド４のうち、配線基板
１のチップ塔載領域に設けられた電極パッド４は、その
上層に形成された絶縁膜９で覆われ、半導体チップ２０
の裏面との接触が生じないようになっている。絶縁膜９
は点在するように電極パッド４毎に形成され、その平面
形状は円形状で形成されている。絶縁膜９は、絶縁性フ
ィルムの表面に配線パターンを形成した後、絶縁性フィ
ルムの表面上の全面に均一な膜厚の感光性樹脂膜を形成
し、その後、ベーク処理、感光処理、現像処理、洗浄処
理等を施すことによって形成される。Of the plurality of electrode pads 4, the electrode pads 4 provided in the chip mounting area of the wiring board 1 are covered with an insulating film 9 formed thereon, and
No contact with the back surface of the device occurs. Insulating film 9
Are formed for each electrode pad 4 so as to be scattered, and the plane shape thereof is formed in a circular shape. The insulating film 9 is formed by forming a wiring pattern on the surface of the insulating film, forming a photosensitive resin film having a uniform thickness on the entire surface of the insulating film, and then performing a baking process, a photosensitive process, and a developing process. , And a cleaning process.
【００２５】前記配線７の一部分は、その上層に形成さ
れた絶縁膜１０で覆われている。絶縁膜１０は、配線基
板１の各辺毎に形成され、配線基板１の辺に沿って延在
している。この絶縁膜１０は、前述の絶縁膜９と同一工
程で形成される。A part of the wiring 7 is covered with an insulating film 10 formed thereon. The insulating film 10 is formed on each side of the wiring board 1 and extends along the side of the wiring board 1. This insulating film 10 is formed in the same step as the above-described insulating film 9.
【００２６】前記複数の電極パッド６の夫々は、配線基
板１の周辺領域に形成され、半導体チップ２０の各辺に
沿って配列されている。これらの電極パッド６は、導電
性のワイヤ２２を介して半導体チップ２０の電極パッド
２０Ａに電気的に接続されている。ワイヤ２２として
は、例えば金(Ａｕ)ワイヤを用いている。ワイヤ２２の
接続方法としては、例えば熱圧着に超音波振動を併用し
たボンディング法を用いている。Each of the plurality of electrode pads 6 is formed in a peripheral area of the wiring board 1 and is arranged along each side of the semiconductor chip 20. These electrode pads 6 are electrically connected to electrode pads 20A of the semiconductor chip 20 via conductive wires 22. As the wire 22, for example, a gold (Au) wire is used. As a connection method of the wire 22, for example, a bonding method using ultrasonic vibration in combination with thermocompression bonding is used.
【００２７】前記樹脂封止体２２の平面形状は方形状で
形成され、本実施形態においては正方形で形成されてい
る。樹脂封止体２２は、半導体チップ２０及びワイヤ２
２等を封止し、電極パッド４、配線５、電極パッド６等
を覆うように形成されている。樹脂封止体２２は、低応
力化を図る目的として、例えばフェノール系硬化剤、シ
リコーンゴム及びフィラーが添加されたエポキシ系の樹
脂で形成されている。The planar shape of the resin sealing body 22 is formed in a square shape, and in the present embodiment is formed in a square shape. The resin sealing body 22 includes the semiconductor chip 20 and the wire 2.
2 and the like are formed so as to cover the electrode pad 4, the wiring 5, the electrode pad 6, and the like. The resin sealing body 22 is formed of, for example, an epoxy resin to which a phenol-based curing agent, silicone rubber, and a filler are added for the purpose of reducing stress.
【００２８】前記樹脂封止体２２は、大量生産に好適な
トランスファモールド法によって形成されている。トラ
ンスファモールド法は、ポット、ランナー、流入ゲート
及びキャビティ等を備えた成形金型を使用し、ポットか
らランナー及び流入ゲートを通してキャビティ内に樹脂
を加圧注入して樹脂封止体を形成する方法である。The resin sealing body 22 is formed by a transfer molding method suitable for mass production. The transfer molding method is a method of using a molding die having a pot, a runner, an inflow gate, a cavity, and the like, and injecting a resin from the pot into the cavity through the runner and the inflow gate to form a resin sealing body. is there.
【００２９】前記樹脂封止体２３の上面の角部には、図
１に示すように、半導体装置の方向(向き)を明確にする
ための目印(インデックス)２５が設けられている。従っ
て、樹脂封止体２３の上面側から半導体装置を見た場
合、半導体装置の方向を把握することができる。As shown in FIG. 1, a mark (index) 25 for clarifying the direction (direction) of the semiconductor device is provided at a corner of the upper surface of the resin sealing body 23. Therefore, when the semiconductor device is viewed from the upper surface side of the resin sealing body 23, the direction of the semiconductor device can be grasped.
【００３０】図４及び図５に示すように、前記配線基板
１の裏面において、配線基板１のＸ方向の中心線Ｐ１及
びＹ方向の中心線Ｐ２によって四分割された四つの領域
の夫々には目印１３が設けられている。この四つの領域
のうち、一つの領域に設けられた目印１３Ａは、図５及
び図６に示すように、配線基板１の表裏面に亘って形成
された貫通孔３で構成されている。また、四つの領域の
うち、他の三つの領域に設けられた目印１３Ｂは、図
５、図６及び図７に示すように、配線基板１の表裏面に
亘って形成された貫通孔３と、この貫通孔３を塞ぐよう
に配線基板１の表面に形成された閉塞体１１とで構成さ
れている。即ち、配線基板１の裏面において、配線基板
１のＸ方向の中心線Ｐ１及びＹ方向の中心線Ｐ２によっ
て四分割された四つの領域の夫々に目印１３が設けら
れ、四つの領域のうち、一つの領域に設けられた目印１
３Ａは他の三つの領域に設けられた目印１３Ｂと異って
いることから、配線基板１の裏面の四つの領域のうちの
一つの領域に設けられた目印１３Ａによって半導体装置
の方向(向き)を明確にすることができる。As shown in FIGS. 4 and 5, on the back surface of the wiring board 1, there are four regions divided by a center line P1 in the X direction and a center line P2 in the Y direction of the wiring board 1, respectively. A mark 13 is provided. Of the four regions, the mark 13A provided in one region is constituted by a through hole 3 formed over the front and back surfaces of the wiring board 1, as shown in FIGS. The marks 13B provided in the other three of the four regions are formed with the through holes 3 formed over the front and back surfaces of the wiring board 1 as shown in FIGS. And a closing body 11 formed on the surface of the wiring board 1 so as to close the through hole 3. That is, on the rear surface of the wiring board 1, the mark 13 is provided in each of four areas divided into four by the center line P1 in the X direction and the center line P2 in the Y direction of the wiring board 1, and one of the four areas is provided with a mark 13. Mark 1 provided in one area
3A is different from the mark 13B provided in the other three regions, and therefore, the direction (direction) of the semiconductor device is determined by the mark 13A provided in one of the four regions on the back surface of the wiring board 1. Can be clarified.
【００３１】なお、目印１３Ａは、配線基板１の裏面の
四つの領域のうち、樹脂封止体２３の上面の角部に設け
られた目印２５と対応する領域に設けられている。ま
た、本実施形態において、Ｘ方向の中心線Ｐ１及びＹ方
向の中心線Ｐ２とは、配線基板１の互いに対向する辺を
結ぶ中心線のことであり、配線基板１の互いに対向する
角部を結ぶ対角線のことではない。The mark 13A is provided in a region corresponding to the mark 25 provided at the corner of the upper surface of the resin sealing body 23 among the four regions on the back surface of the wiring board 1. In the present embodiment, the center line P1 in the X direction and the center line P2 in the Y direction are center lines connecting sides of the wiring board 1 that face each other. It is not a connecting diagonal.
【００３２】前記配線基板１の裏面の四つの領域の夫々
に設けられた各目印１３は、配線基板１のチップ塔載領
域内に配置されている。本実施形態において、各目印１
３は、配線基板１の中心の近傍に集中して配置されてい
る。また、各目印１３は、互いに等間隔となるように配
線基板１の対角線上に配置されている。Each mark 13 provided in each of the four regions on the back surface of the wiring substrate 1 is arranged in the chip mounting region of the wiring substrate 1. In the present embodiment, each mark 1
Reference numeral 3 is arranged in a concentrated manner near the center of the wiring board 1. The marks 13 are arranged on the diagonal line of the wiring board 1 so as to be equidistant from each other.
【００３３】前記配線基板１の裏面の四つの領域のう
ち、一つの領域に設けられた目印１３Ａは、他の三つの
領域に設けられた目印１３Ｂと異なり、貫通孔３によっ
て構成されているので、配線基板１のチップ塔載領域に
接着剤を塗布して半導体チップ２０を塔載する際、接着
剤が貫通孔３内に流れ込んでしまう。そこで、貫通孔３
内への接着剤の流れ込みを堰き止める目的として、図３
及び図６に示すように、配線基板１の表面に貫通孔３の
周囲を囲む堰堤(ダム)１２が設けられている。Since the mark 13A provided in one of the four regions on the back surface of the wiring substrate 1 is different from the mark 13B provided in the other three regions, the mark 13A is formed by the through hole 3. When the adhesive is applied to the chip mounting area of the wiring board 1 and the semiconductor chip 20 is mounted, the adhesive flows into the through-hole 3. Therefore, the through hole 3
Fig. 3 shows the purpose of blocking the flow of adhesive into the interior.
As shown in FIG. 6, a dam 12 surrounding the periphery of the through hole 3 is provided on the surface of the wiring board 1.
【００３４】前記貫通孔３及び閉塞体８の平面形状は円
形状で形成され、閉塞体８の平面サイズは貫通孔３の平
面サイズよりも小さい寸法で形成されている。貫通孔３
は前述の接続孔２と同一工程で形成され、閉塞体８は前
述の電極パッド４と同一工程で形成される。The through hole 3 and the closing body 8 are formed in a circular plane shape, and the closing body 8 has a plane size smaller than that of the through hole 3. Through hole 3
Are formed in the same step as the connection hole 2 described above, and the closing body 8 is formed in the same step as the electrode pad 4 described above.
【００３５】前記閉塞体８は、図３、図６及び図７に示
すように、その上層に形成された絶縁膜１１で覆われ、
半導体チップ２０の裏面との接触が生じないようになっ
ている。絶縁膜１１は点在するように閉塞体８毎に形成
され、その平面形状は円形状で形成されている。絶縁膜
１１は前述の絶縁膜９と同一工程で形成される。As shown in FIGS. 3, 6 and 7, the closing member 8 is covered with an insulating film 11 formed thereon.
The contact with the back surface of the semiconductor chip 20 does not occur. The insulating film 11 is formed for each closed body 8 so as to be scattered, and its planar shape is formed in a circular shape. The insulating film 11 is formed in the same step as the insulating film 9 described above.
【００３６】次に、前記半導体装置の製造に用いられる
フレーム構造体について、図８を用いて説明する。図８
はフレーム構造体の要部平面図である。Next, a frame structure used for manufacturing the semiconductor device will be described with reference to FIG. FIG.
3 is a plan view of a main part of the frame structure. FIG.
【００３７】図８に示すように、フレーム構造体３０
は、これに限定されないが、例えば、枠体３１で規定さ
れた領域３２を一方向に複数個配列した多連フレーム構
造になっており、各領域３２内に可撓性の絶縁性フィル
ム１Ａを有している。領域３２及び絶縁性フィルム１Ａ
の夫々の平面形状は方形状で形成されている。As shown in FIG. 8, the frame structure 30
Although not limited to this, for example, it has a multiple frame structure in which a plurality of regions 32 defined by the frame body 31 are arranged in one direction, and a flexible insulating film 1A is provided in each region 32. Have. Region 32 and insulating film 1A
Are formed in a square shape.
【００３８】前記絶縁性フィルム１Ａは、互いに対向す
る二辺の夫々の部分が枠体３１の互いに対向する長手方
向の二つの枠部分の夫々に接着剤を介在して接着固定さ
れている。絶縁性フィルム１Ａは、例えばポリイミド系
の絶縁樹脂若しくはエポキシ系の絶縁樹脂で形成され、
例えば５０［μｍ］程度の厚さで形成されている。The insulating film 1A has two sides facing each other adhered and fixed to each of the two longitudinally facing frame portions of the frame body 31 with an adhesive therebetween. The insulating film 1A is formed of, for example, a polyimide-based insulating resin or an epoxy-based insulating resin,
For example, it is formed with a thickness of about 50 [μm].
【００３９】前記絶縁性フィルム１Ａの基板形成領域３
３は、詳細に図示していないが、前述の配線基板１とほ
ぼ同様の構成になっており、配線パターン（電極パッド
４、配線５、電極パッド６、配線７）、接続孔２、貫通
孔３、閉塞体８、絶縁膜９、絶縁膜１０、絶縁膜１１、
堰堤１２、目印１３等を有する構成になっている。この
絶縁性フィルム１Ａの基板形成領域３３は、半導体装置
の製造プロセスにおいて切り抜かれ、配線基板１として
使用される。The substrate forming region 3 of the insulating film 1A
Although not shown in detail, 3 has substantially the same configuration as the wiring board 1 described above, and includes wiring patterns (electrode pads 4, wiring 5, electrode pads 6, and wiring 7), connection holes 2, and through holes. 3, closing body 8, insulating film 9, insulating film 10, insulating film 11,
It has a configuration having a bank 12, a mark 13, and the like. The substrate forming region 33 of the insulating film 1A is cut out in the semiconductor device manufacturing process and used as the wiring substrate 1.
【００４０】前記枠体３１は、金属板にエッチング加工
又はプレス打抜き加工を施すことによって形成される。
金属板としては例えば銅系合金からなるものを用いる。The frame 31 is formed by subjecting a metal plate to etching or press punching.
As the metal plate, for example, a plate made of a copper-based alloy is used.
【００４１】次に、前記半導体装置の製造方法につい
て、図９乃至図１３（製造方法を説明するための要部断
面図）を用いて説明する。Next, a method of manufacturing the semiconductor device will be described with reference to FIGS. 9 to 13 (a cross-sectional view of a main part for describing the manufacturing method).
【００４２】まず、前述のフレーム構造体３０を準備す
る。フレーム構造体３０は枠体３１で規定された領域３
２内に絶縁性フィルム１Ａを有し、絶縁性フィルム１Ａ
の基板形成領域３３は、配線パターン（電極パッド４、
配線５、電極パッド６、配線７）、接続孔２、貫通孔
３、閉塞体８、絶縁膜９、絶縁膜１０、絶縁膜１１、堰
堤１２、目印１３等を有する構成になっている。First, the above-mentioned frame structure 30 is prepared. The frame structure 30 is a region 3 defined by the frame 31.
2 having an insulating film 1A and an insulating film 1A
The substrate forming region 33 has a wiring pattern (electrode pad 4,
The wiring 5, the electrode pad 6, the wiring 7), the connection hole 2, the through hole 3, the closing body 8, the insulating film 9, the insulating film 10, the insulating film 11, the bank 12, the mark 13, and the like are provided.
【００４３】次に、前記絶縁性フィルム１Ａの表面のチ
ップ塔載領域に接着剤２１を多点塗布法で供給する。接
着剤２１としては、例えばエポキシ系又はポリイミド系
の熱硬化性絶縁樹脂を用いる。Next, the adhesive 21 is supplied to the chip mounting area on the surface of the insulating film 1A by a multi-point coating method. As the adhesive 21, for example, a thermosetting insulating resin of epoxy type or polyimide type is used.
【００４４】次に、図９に示すように、前記絶縁性フィ
ルム１Ａの表面のチップ塔載領域に接着剤２１を介在し
て半導体チップ２０を塔載し、その後、熱処理を施して
接着剤２１を硬化させる。この工程において、接着剤２
１からアウトガスが発生するが、図１０に示すように、
絶縁性フィルム１Ａのチップ塔載領域には目印１３Ａと
しての貫通孔３が形成されていることから、アウトガス
は貫通孔３を通して外部に放出される。即ち、接着剤２
１の硬化時に発生するアウトガスを外部に逃すことがで
きる。また、絶縁性フィルム１Ａのチップ塔載領域には
目印１３Ａとしての貫通孔３の周囲を囲む堰堤１２が形
成されていることから、貫通孔３内への接着剤２１の流
れ込みを堰き止めることができる。Next, as shown in FIG. 9, the semiconductor chip 20 is mounted on the chip mounting area on the surface of the insulating film 1A with the adhesive 21 interposed therebetween. To cure. In this step, the adhesive 2
Although outgas is generated from No. 1, as shown in FIG.
Since the through hole 3 as the mark 13A is formed in the chip tower area of the insulating film 1A, the outgas is discharged to the outside through the through hole 3. That is, the adhesive 2
Outgas generated during curing of No. 1 can be released to the outside. Further, since the dam 12 surrounding the periphery of the through hole 3 as the mark 13A is formed in the chip mounting area of the insulating film 1A, it is possible to stop the flow of the adhesive 21 into the through hole 3. it can.
【００４５】次に、前記半導体チップ２０の電極パッド
２０Ａと絶縁性フィルム１Ａの表面に形成された電極パ
ッド６とを導電性のワイヤ２２で電気的に接続する。ワ
イヤ２２としては例えば金ワイヤを用いる。ワイヤ２２
の接続方法としては例えば熱圧着に超音波振動を併用し
たボンディング法を用いる。Next, the electrode pads 20A of the semiconductor chip 20 and the electrode pads 6 formed on the surface of the insulating film 1A are electrically connected by conductive wires 22. As the wire 22, for example, a gold wire is used. Wire 22
For example, a bonding method using ultrasonic vibration in combination with thermocompression bonding is used.
【００４６】次に、前記フレーム構造体３０を成形金型
の上型と下型との間に装着すると共に、成形金型の上型
と下型とで形成されるキャビティ内に半導体チップ２０
を配置する。成形金型は、キャビティの他に、ポット、
ランナー及びゲート等を備えている。Next, the frame structure 30 is mounted between the upper die and the lower die of the molding die, and the semiconductor chip 20 is placed in a cavity formed by the upper die and the lower die of the molding die.
Place. In addition to the cavity, the mold, pot,
A runner and a gate are provided.
【００４７】次に、前記成形金型のポットに樹脂タブレ
ットを投入し、その後、樹脂タブレットをトランスファ
モールド装置のプランジャで加圧し、キャビティに樹脂
を供給して、図１１に示すように、樹脂封止体２３を形
成する。この工程において、樹脂封止体２３の上面の角
部に半導体装置の方向(向き)を明確にするための目印２
５が形成される。Next, a resin tablet is put into the pot of the molding die, and then the resin tablet is pressurized by a plunger of a transfer molding apparatus to supply the resin to the cavity, and as shown in FIG. The stop 23 is formed. In this step, a mark 2 for clarifying the direction (direction) of the semiconductor device is provided at a corner of the upper surface of the resin sealing body 23.
5 are formed.
【００４８】次に、図１２に示すように、前記絶縁性フ
ィルム１Ａの裏面を上向きにした状態で、電極パッド４
の裏面上に例えば６３［重量％］Ｐｂ−３７［重量％］
Ｓｎ組成の金属材からなる半田球２４Ａを供給する。半
田球２４Ａの供給は、ガラスマスクを用いたボール供給
法若しくは吸引治具を用いたボール供給法で行う。この
工程において、絶縁性フィルム１Ａの基板形成領域３３
の裏面には配線基板１の裏面と同様の目印１３が設けら
れていることから、目印１３Ａによって絶縁性フィルム
１Ａの方向(向き)を把握しながら半田球２４Ａの供給を
行うことができる。本実施形態のように、電極パッド４
の配列が中心線に対して対称となっている場合、絶縁性
フィルム１Ａの向きが間違っていても電極パッド４の裏
面上に半田球２４Ａを供給することはできるが、電極パ
ッド４の配列が中心線に対して非対称の場合、絶縁性フ
ィルム１Ａの向きの間違によって電極パッド４の裏面上
に半田球２４Ａが供給されない不具合が生じてしまう。Next, as shown in FIG. 12, the electrode pad 4 was placed with the back surface of the insulating film 1A facing upward.
63% by weight Pb-37 [% by weight]
A solder ball 24A made of a metal material having a Sn composition is supplied. The solder balls 24A are supplied by a ball supply method using a glass mask or a ball supply method using a suction jig. In this step, the substrate forming region 33 of the insulating film 1A is formed.
Since the mark 13 similar to the back surface of the wiring board 1 is provided on the back surface of the wiring board 1, the solder balls 24A can be supplied while grasping the direction (direction) of the insulating film 1A by the mark 13A. As in the present embodiment, the electrode pad 4
Are symmetrical with respect to the center line, the solder balls 24A can be supplied on the back surface of the electrode pad 4 even if the direction of the insulating film 1A is wrong. In the case of being asymmetrical with respect to the center line, there is a problem that the solder balls 24A are not supplied on the back surface of the electrode pad 4 due to the wrong orientation of the insulating film 1A.
【００４９】次に、赤外線リフロー法を使用し、前記半
田球２４Ａを溶融して半田バンプ２４を形成する。半田
バンプ２４は接続孔２を通して電極パッド４の裏面に固
着され、電気的にかつ機械的に接続される。Next, the solder balls 24A are melted to form solder bumps 24 by using an infrared reflow method. The solder bump 24 is fixed to the back surface of the electrode pad 4 through the connection hole 2 and is electrically and mechanically connected.
【００５０】この後、前記絶縁性フィルム１Ａの基板形
成領域３３を切り抜いて配線基板１を形成することによ
り、図１乃至図７に示す半導体装置が完成する。Thereafter, by cutting out the substrate forming region 33 of the insulating film 1A to form the wiring substrate 1, the semiconductor device shown in FIGS. 1 to 7 is completed.
【００５１】この後、半導体装置は、携帯電話、ビデオ
カメラ、ノート型パーソナルコンピュータ等の電子機器
に組み込まれる実装基板上に実装される。半導体装置の
実装は、外部接続用端子である半田バンプ２４を例えば
赤外線リフロー法で溶融し、この半田バンプ２４を実装
基板の電極パッドに接合することによって行なわれる。
この実装時において、樹脂封止体２３及び接着剤２１に
含まれている水分が熱によって気化膨張して水蒸気とな
るが、配線基板１には目印１３Ａとしての貫通孔３が形
成されていることから、水蒸気は貫通孔３を通して外部
に放出される。Thereafter, the semiconductor device is mounted on a mounting board incorporated in an electronic device such as a mobile phone, a video camera, and a notebook personal computer. The mounting of the semiconductor device is performed by melting the solder bumps 24 serving as external connection terminals by, for example, an infrared reflow method, and joining the solder bumps 24 to the electrode pads of the mounting board.
At the time of this mounting, the moisture contained in the resin sealing body 23 and the adhesive 21 is vaporized and expanded by heat to become water vapor, but the through hole 3 as the mark 13A is formed in the wiring board 1. Thus, the water vapor is released to the outside through the through holes 3.
【００５２】このように、本実施形態によれば、以下の
効果が得られる。As described above, according to the present embodiment, the following effects can be obtained.
【００５３】（１）配線基板１の裏面において、そのＸ
方向の中心線Ｐ１及びＹ方向の中心線Ｐ２によって四分
割された四つの領域の夫々に目印１３が設けられ、この
四つの領域のうち、一つの領域に設けられた目印１３Ａ
は他の三つの領域に設けられた目印１３Ｂと異なってい
ることから、配線基板１の裏面の四つの領域のうちの一
つの領域に設けられた目印１３Ａによって半導体装置の
方向(向き)を明確にすることができるので、配線基板１
の裏面側から半導体装置の方向を把握することができ
る。(1) On the back surface of the wiring board 1, the X
A mark 13 is provided in each of four areas divided into four by the center line P1 in the direction and the center line P2 in the Y direction, and a mark 13A provided in one of the four areas.
Is different from the marks 13B provided in the other three regions, the direction (direction) of the semiconductor device is clearly defined by the marks 13A provided in one of the four regions on the back surface of the wiring board 1. Wiring board 1
The direction of the semiconductor device can be grasped from the back side of the semiconductor device.
【００５４】また、半導体装置の製造プロセスにおい
て、配線基板(絶縁性フィルム１Ａ)１の裏面を上向きに
した状態で電極パッド４の裏面上に半田球２４Ａを供給
する際、目印１３Ａによって配線基板１の方向(向き)を
把握しながら半田球２４Ａの供給を行うことができるの
で、配線基板１の向きの間違によって生じる半田球２４
Ａの供給不良を防止することができる。この結果、半導
体装置の製造における歩留まりを高めることができる。In the process of manufacturing the semiconductor device, when the solder balls 24A are supplied onto the back surface of the electrode pads 4 with the back surface of the wiring board (insulating film 1A) 1 facing upward, the mark 13A indicates the wiring board 1 The solder balls 24A can be supplied while grasping the direction (direction) of the solder balls 24A.
A supply failure can be prevented. As a result, the yield in manufacturing the semiconductor device can be increased.
【００５５】（２）配線基板１の裏面の四つの領域の夫
々に設けられた各目印１３は、配線基板１の中心の近傍
に集中して配置され、更に、互いに等間隔となるように
配線基板１の対角線上に配置されていることから、配線
基板１の裏面側から半導体装置の方向(向き)を正確に把
握することができる。(2) The marks 13 provided in each of the four regions on the back surface of the wiring board 1 are arranged in a concentrated manner near the center of the wiring board 1 and are further arranged so as to be equidistant from each other. Since the semiconductor device is arranged on the diagonal line of the substrate 1, the direction (direction) of the semiconductor device can be accurately grasped from the back surface side of the wiring substrate 1.
【００５６】（３）配線基板１の裏面の四つの領域の夫
々に設けられた各目印は配線基板１のチップ塔載領域内
に配置されていることから、半導体装置を実装基板上に
実装する際、樹脂封止体２３及び接着剤２１に含まれて
いる水分が実装時の熱によって気化膨張した水蒸気を目
印１３Ａとしての接続孔３を通して外部に放出すること
ができるので、水分の気化膨張による樹脂封止体２３の
亀裂を防止することができる。この結果、半導体装置の
熱に対する信頼性を高めることができる。(3) Since the marks provided in the four regions on the back surface of the wiring board 1 are arranged in the chip mounting area of the wiring board 1, the semiconductor device is mounted on the mounting board. At this time, the water vapor contained in the resin sealing body 23 and the adhesive 21 can be released to the outside through the connection hole 3 serving as the mark 13A due to the vaporization and expansion of heat due to the heat at the time of mounting. Cracking of the resin sealing body 23 can be prevented. As a result, the reliability of the semiconductor device against heat can be improved.
【００５７】また、半導体装置の製造プロセスにおい
て、配線基板(絶縁性フィルム１Ａ)１の表面のチップ塔
載領域に接着剤２１を介在して半導体チップ２０を塔載
する際、接着剤２１の硬化時に発生するアウトガスを目
印１３Ａとしての貫通孔３を通して外部に逃すことがで
きるので、半導体チップ２０下における配線基板１の膨
れ及びしわを防止することができる。この結果、半導体
装置の平坦度を高めることができる。In the process of manufacturing a semiconductor device, when the semiconductor chip 20 is mounted on the chip mounting area on the surface of the wiring substrate (insulating film 1A) 1 with the adhesive 21 interposed therebetween, the adhesive 21 is cured. Since outgas generated at the time can be released to the outside through the through hole 3 serving as the mark 13A, swelling and wrinkling of the wiring board 1 under the semiconductor chip 20 can be prevented. As a result, the flatness of the semiconductor device can be improved.
【００５８】また、半導体装置の製造プロセスにおい
て、配線基板(絶縁性フィルム１Ａ)１の表面上に樹脂封
止体２３をトランスファモールド法に基づいて形成する
際、目印１３Ａとしての貫通孔３を通して配線基板１の
裏面側へ樹脂が廻り込むのを半導体チップ２０によって
防止できるので、半導体装置の外観不良を抑制すること
ができる。この結果、半導体装置の生産性を高めること
ができる。In the manufacturing process of the semiconductor device, when the resin sealing body 23 is formed on the surface of the wiring substrate (insulating film 1A) 1 based on the transfer molding method, the wiring is formed through the through hole 3 as the mark 13A. Since the semiconductor chip 20 can prevent the resin from flowing to the back side of the substrate 1, the appearance defect of the semiconductor device can be suppressed. As a result, the productivity of the semiconductor device can be improved.
【００５９】（４）配線基板１の表面のチップ塔載領域
１０Ｂに目印１３Ａとしての貫通孔３の周囲を囲む堰堤
(ダム)１２が形成されていることから、半導体装置の製
造プロセスにおいて、配線基板(絶縁性フィルム１Ａ)１
の表面のチップ塔載領域に接着剤２１を介在して半導体
チップ１０を塔載する際、貫通孔３内への接着剤２１の
流れ込みを堰き止めることができるので、配線基板１の
裏面への接着剤２１の廻り込みを防止できる。この結
果、半導体装置の外観不良を抑制することができるの
で、半導体装置の生産性を高めることができる。(4) A dam surrounding the periphery of the through hole 3 as the mark 13A in the chip tower mounting area 10B on the surface of the wiring board 1.
Since the (dam) 12 is formed, the wiring board (insulating film 1A) 1
When the semiconductor chip 10 is mounted on the chip mounting area on the surface of the semiconductor chip 10 with the adhesive 21 interposed therebetween, the flow of the adhesive 21 into the through-hole 3 can be blocked, so that The adhesive 21 can be prevented from sneaking around. As a result, the appearance defect of the semiconductor device can be suppressed, so that the productivity of the semiconductor device can be increased.
【００６０】（５）枠体３１で規定された領域３２内に
絶縁性フィルム１Ａを有するフレーム構造体３０を用い
て半導体装置の製造を行うことから、絶縁性フィルム１
Ａの搬送性を高めることができると共に、ハンドリング
性を高めることができる。(5) Since the semiconductor device is manufactured using the frame structure 30 having the insulating film 1A in the region 32 defined by the frame 31, the insulating film 1
The transportability of A can be improved, and the handleability can be improved.
【００６１】なお、本実施形態では、フレーム構造体３
０を用いて半導体装置を製造する例について説明した
が、絶縁性フィルム１Ａの基板形成領域３３を切り抜い
て配線基板１を形成し、この配線基板１を用いて半導体
装置を製造してもよい。In this embodiment, the frame structure 3
Although the example in which the semiconductor device is manufactured using 0 is described, the wiring substrate 1 may be formed by cutting out the substrate forming region 33 of the insulating film 1A, and the semiconductor device may be manufactured using the wiring substrate 1.
【００６２】また、本実施形態では、配線基板１の裏面
の四つの領域のうち、一つの領域の目印１３Ａを貫通孔
３で構成し、他の三つの領域の夫々の目印１３Ｂを貫通
孔３及び閉塞体８で構成した例について説明したが、図
１４（半導体装置の要部底面図）、図１５(図１４に示
すＤ−Ｄ線の位置で切った断面図）及び図１６（図１４
に示すＥ−Ｅ線の位置で切った断面図）に示すように、
配線基板１の裏面の四つの領域のうち、一つの領域の目
印１３Ａを貫通孔３及び閉塞体８で構成し、他の三つの
領域の夫々の目印１３Ｂを貫通孔３で構成してもよい。
この場合、目印１３Ｂとしての貫通孔３の周囲を堰堤
(ダム)１２によって囲む。このような実施形態において
も、前述の実施形態と同様の効果が得られる。In the present embodiment, of the four regions on the back surface of the wiring board 1, the mark 13A of one region is formed by the through hole 3, and the mark 13B of the other three regions is formed by the through hole 3. 14 and FIG. 14 (a cross-sectional view taken along the line DD shown in FIG. 14) and FIG. 16 (FIG. 14).
(A cross-sectional view taken along the line EE shown in FIG.
Of the four regions on the back surface of the wiring board 1, the mark 13A of one region may be constituted by the through hole 3 and the closing body 8, and the mark 13B of the other three regions may be constituted by the through hole 3. .
In this case, the surrounding of the through hole 3 as the mark 13B is a dam
Surrounded by (dam) 12. In such an embodiment, the same effect as in the above-described embodiment can be obtained.
【００６３】また、本実施形態では、平面形状が正方形
の配線基板１を有する半導体装置について説明したが、
配線基板１の平面形状は長方形であってもよい。In this embodiment, the semiconductor device having the wiring substrate 1 having a square planar shape has been described.
The planar shape of the wiring board 1 may be rectangular.
【００６４】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.
【００６５】例えば、本発明は、ガラス繊維に樹脂等を
含浸させた樹脂基板からなる配線基板若しくはセラミッ
クスからなる配線基板を有する半導体装置に適用でき
る。For example, the present invention can be applied to a semiconductor device having a wiring substrate made of a resin substrate in which glass fiber is impregnated with a resin or the like or a wiring substrate made of ceramics.
【００６６】また、本発明は、配線基板の裏面側に外部
接続用端子として電極パッド（ランド端子）が設けられ
たパッケージ構造を有するＬＧＡ(Ｌand Ｇrid Ａrray)
型半導体装置に適用できる。[0066] Further, the present invention is the electrode pad on the back side of the wiring board as an external connection terminal LGA having a package structure (land terminal) are provided (L and G rid A rray)
The present invention can be applied to a type semiconductor device.
【００６７】また、本発明は、半田バンプに限らず、配
線基板の裏面側に外部接続用端子としてバンプが設けら
れたパッケージ構造を有する半導体装置に適用できる。The present invention is not limited to solder bumps, and can be applied to a semiconductor device having a package structure in which bumps are provided as external connection terminals on the back surface of a wiring board.
【００６８】[0068]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【００６９】配線基板の裏面側から半導体装置の方向を
把握することができる。The direction of the semiconductor device can be grasped from the back side of the wiring board.
【００７０】また、半導体装置の製造における歩留まり
を高めることができる。Further, the yield in the manufacture of a semiconductor device can be increased.
【００７１】また、半導体装置の熱に対する信頼性を高
めることができる。Further, the reliability of the semiconductor device against heat can be improved.
【００７２】また、半導体装置の平坦度を高めることが
できる。Further, the flatness of the semiconductor device can be improved.
【００７３】また、半導体装置の生産性を高めることが
できる。Further, the productivity of the semiconductor device can be improved.
【図１】本発明の一実施形態である半導体装置の平面図
である。FIG. 1 is a plan view of a semiconductor device according to an embodiment of the present invention.
【図２】図１に示すＡ−Ａ線の位置で切った断面図であ
る。FIG. 2 is a sectional view taken along a line AA shown in FIG.
【図３】前記半導体装置を構成する配線基板の平面図で
ある。FIG. 3 is a plan view of a wiring board constituting the semiconductor device.
【図４】前記半導体装置の底面図である。FIG. 4 is a bottom view of the semiconductor device.
【図５】図４の要部拡大図である。FIG. 5 is an enlarged view of a main part of FIG. 4;
【図６】図５に示すＢ−Ｂ線の位置で切った断面図であ
る。FIG. 6 is a sectional view taken along the line BB shown in FIG.
【図７】図５に示すＣ−Ｃ線の位置で切った断面図であ
る。FIG. 7 is a sectional view taken along the line CC shown in FIG. 5;
【図８】前記半導体装置の製造に用いられるフレーム構
造体の要部平面図である。FIG. 8 is a plan view of a main part of a frame structure used for manufacturing the semiconductor device.
【図９】前記半導体装置の製造方法を説明するための要
部断面図である。FIG. 9 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor device.
【図１０】前記半導体装置の製造方法を説明するための
要部断面図である。FIG. 10 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor device.
【図１１】前記半導体装置の製造方法を説明するための
要部断面図である。FIG. 11 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor device;
【図１２】前記半導体装置の製造方法を説明するための
要部断面図である。FIG. 12 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor device;
【図１３】前記半導体装置の製造方法を説明するための
要部断面図である。FIG. 13 is a fragmentary cross-sectional view for explaining the method for manufacturing the semiconductor device.
【図１４】本発明の変形例である半導体装置の要部底面
図である。FIG. 14 is a bottom view of a main part of a semiconductor device according to a modification of the present invention.
【図１５】図１４に示すＤ−Ｄ線の位置で切った断面図
である。15 is a cross-sectional view taken along a line DD shown in FIG.
【図１６】図１４に示すＥ−Ｅ線の位置で切った断面図
である。16 is a sectional view taken along the line EE shown in FIG.
１…配線基板、１Ａ…絶縁性フィルム、２…接続孔、３
…貫通孔、４…電極パッド、５…配線、６…電極パッ
ド、７…配線、８…閉塞体、９，１０，１１…絶縁膜、
１２…堰堤（ダム）、１３…目印、２０…半導体チッ
プ、２１…接着剤、２２…ワイヤ、２３…樹脂封止体、
２４…半田バンプ、２４Ａ…半田球、２５…目印、３０
…フレーム構造体、３１…枠体、３２…規定領域、３３
…基板形成領域。DESCRIPTION OF SYMBOLS 1 ... Wiring board, 1A ... Insulating film, 2 ... Connection hole, 3
... through-hole, 4 ... electrode pad, 5 ... wiring, 6 ... electrode pad, 7 ... wiring, 8 ... closing body, 9, 10, 11 ... insulating film,
12 dam, 13 mark, 20 semiconductor chip, 21 adhesive, 22 wire, 23 resin sealing body,
24: solder bump, 24A: solder ball, 25: mark, 30
... frame structure, 31 ... frame, 32 ... prescribed area, 33
... Substrate formation area.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 今野 貴史 北海道亀田郡七飯町字中島145番地 日立 北海セミコンダクタ株式会社内 (72)発明者 春田 亮 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 竹谷 則明 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takashi Konno 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi Hokkai Semiconductor Co., Ltd. (72) Inventor Noriaki Takeya 3550 Kida Yomachi, Tsuchiura-city, Ibaraki Pref.
Claims (4)
体チップが設けられ、裏面側に複数の外部接続用端子が
設けられたパッケージ構造を有する半導体装置であっ
て、前記配線基板の裏面において、そのＸ方向の中心線
及びＹ方向の中心線によって四分割された四つの領域の
夫々に目印が設けられ、前記四つの領域のうち、一つの
領域に設けられた目印は他の領域に設けられた目印と異
なっていることを特徴とする半導体装置。1. A semiconductor device having a package structure in which a semiconductor chip is provided on a front side of a front and back surface of a wiring board and a plurality of external connection terminals are provided on a back side, wherein the back surface of the wiring board is provided. In the above, a mark is provided in each of the four areas divided into four by the center line in the X direction and the center line in the Y direction, and the mark provided in one of the four areas is provided in another area. A semiconductor device, which is different from a provided mark.
記配線基板の表裏面に亘って形成された貫通孔で構成さ
れ、前記他の領域に設けられた目印は、前記配線基板の
表裏面に亘って形成された貫通孔と、この貫通孔を塞ぐ
ように前記配線基板の表面に形成された閉塞体とで構成
されていることを特徴とする請求項１に記載の半導体装
置。2. The mark provided in the one area is constituted by a through hole formed over the front and back surfaces of the wiring board, and the mark provided in the other area is provided on the surface of the wiring board. 2. The semiconductor device according to claim 1, comprising a through hole formed over the back surface, and a closing body formed on the surface of the wiring board so as to close the through hole.
記配線基板の表裏面に亘って形成された貫通孔と、この
貫通孔を塞ぐように前記配線基板の表面に形成された閉
塞体とで構成され、前記他の領域に設けられた目印は、
前記配線基板の表裏面に亘って形成された貫通孔で構成
されていることを特徴とする請求項１に記載の半導体装
置。3. A mark provided in the one area includes a through hole formed over the front and back surfaces of the wiring board, and a closing body formed on the surface of the wiring board so as to cover the through hole. And the mark provided in the other area is:
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises a through hole formed over the front and back surfaces of the wiring board.
プ塔載領域上に接着剤を介在して塔載され、前記各目印
は前記配線基板のチップ塔載領域内に配置されているこ
とを特徴とする請求項２又は請求項３に記載の半導体装
置。4. The semiconductor chip is mounted on a chip mounting area of the wiring board with an adhesive interposed therebetween, and each mark is arranged in the chip mounting area of the wiring board. The semiconductor device according to claim 2 or 3, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7688098A JP3703960B2 (en) | 1998-03-25 | 1998-03-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7688098A JP3703960B2 (en) | 1998-03-25 | 1998-03-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11274334A true JPH11274334A (en) | 1999-10-08 |
| JP3703960B2 JP3703960B2 (en) | 2005-10-05 |
Family
ID=13617958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7688098A Expired - Fee Related JP3703960B2 (en) | 1998-03-25 | 1998-03-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3703960B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002033347A (en) * | 2000-07-17 | 2002-01-31 | Rohm Co Ltd | Semiconductor device |
| JP2010124001A (en) * | 2010-03-08 | 2010-06-03 | Rohm Co Ltd | Semiconductor device |
-
1998
- 1998-03-25 JP JP7688098A patent/JP3703960B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002033347A (en) * | 2000-07-17 | 2002-01-31 | Rohm Co Ltd | Semiconductor device |
| JP2010124001A (en) * | 2010-03-08 | 2010-06-03 | Rohm Co Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3703960B2 (en) | 2005-10-05 |
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