TWI461126B - Package substrate, package structure and methods for manufacturing same - Google Patents

Description

Chip package substrate and structure and manufacturing method thereof

The present invention relates to the field of circuit board manufacturing, and in particular to a chip package substrate and a chip package structure, and a method of fabricating the chip package substrate and the chip package structure.

The chip package substrate can provide electrical connection, protection, support, heat dissipation, assembly and the like for the wafer to achieve multi-pin, reduce package volume, improve electrical performance and heat dissipation, ultra-high density or multi-chip modularization. .

The chip package substrate comprises an insulating substrate, a conductive trace pattern disposed on a surface of the insulating substrate, and a cover film covering a surface of the substrate exposed from the conductive trace and a surface of a portion of the conductive trace pattern, and the plurality of electrical connection pads exposed from the cover film . When the wafer is packaged by a flip chip package, a plurality of contact bumps of the wafer are soldered to corresponding electrical connection pads on the chip package substrate, and then an underfill is disposed in a gap between the wafer and the chip package substrate. However, when a multi-layer wafer is packaged on a package, when a flip chip package of a certain wafer is performed, a region adjacent to the wafer package substrate is provided with a plurality of electrical connection pads, and the bottom is disposed at the bottom. In the case of a filler, the electrical connection pads around the wafer may be contaminated by the underfill, thereby degrading the quality of the package structure.

Therefore, it is necessary to provide a chip package substrate which can effectively improve the quality of a wafer package. And structure and its making method.

A method for fabricating a chip package substrate, comprising the steps of: providing a circuit board, comprising: a base layer; a first conductive line pattern disposed on a surface of the base layer; and a first conductive line pattern formed on the first conductive line pattern and partially covering the first conductive line pattern a first solder resist layer, the portion of the first conductive trace pattern exposed from the first solder resist layer constitutes a plurality of first electrical contact pads and a plurality of second electrical contact pads, the plurality of second electrical contact pads surrounding the plurality The first electrical contact pads are respectively disposed on the plurality of first electrical contact pads, and the plurality of first solder bumps are respectively electrically connected to the corresponding first electrical contact pads; Forming a dry film type solder resist layer on the solder resist layer, the dry film type solder resist layer having a hollow portion that completely exposes the plurality of first solder bumps and surrounding the plurality of first solder bumps and a portion of the first solder mask adjacent to the first solder bump, the dry film solder mask completely covering the plurality of second electrical contact pads; forming a plurality of openings on the dry film solder mask to expose the plurality Plural second electrical a second solder bump is respectively formed on the plurality of second electrical contact pads, and the plurality of second solder bumps are electrically connected to the corresponding second electrical contact pads, respectively, and the plurality of second solder bumps The surface of the dry film type solder resist layer is protruded to form a chip package substrate.

A chip package substrate comprising a first substrate layer, a first conductive trace pattern formed on a surface of the first base layer, a first solder resist layer formed on the first conductive trace pattern, a dry film solder resist layer, and a plurality Second solder bump. The first solder resist layer partially covers the first conductive trace pattern, and the first conductive trace pattern exposed from the first solder resist layer constitutes a plurality of first electrical contact pads and a plurality of second electrical contact pads, the plural second An electrical contact pad is disposed around the plurality of first electrical contact pads. A first solder bump is formed on the plurality of first electrical contact pads. The dry film type solder mask has a hollow portion and a complex a plurality of openings, the hollow portion completely exposing the plurality of first solder bumps and a portion of the first solder resist layer surrounding the plurality of first solder bumps and adjacent to the plurality of first solder bumps, the plurality of openings The plurality of second electrical contact pads are respectively exposed. The plurality of second solder bumps are respectively formed on the plurality of second electrical contact pads.

A method for fabricating a chip package structure, comprising the steps of: providing a chip package substrate as described above as a first chip package substrate; providing a first wafer having a one-to-one correspondence with the plurality of first solder bumps a plurality of contact bumps; respectively connecting the plurality of contact bumps to the corresponding first solder bumps and electrically conducting; and filling an underfill between the first wafer and the first chip package substrate to The first wafer is fixed to the first chip package substrate to form a first chip package structure.

A chip package structure includes a first chip package substrate and a first wafer. The first chip package substrate includes a first substrate layer, a first conductive trace pattern formed on a surface of the first substrate layer, a first solder resist layer formed on the first conductive trace pattern, and formed on the first solder resist a dry film solder mask on the layer and a plurality of second solder bumps. The first solder resist layer partially covers the first conductive trace pattern, and the first conductive trace pattern exposed from the first solder resist layer constitutes a plurality of first electrical contact pads and a plurality of second electrical contact pads, the plural second An electrical contact pad is disposed around the plurality of first electrical contact pads. A first solder bump is formed on the plurality of first electrical contact pads. The dry film type solder mask has a hollow portion and a plurality of openings, the hollow portion completely exposing the plurality of first solder bumps and surrounding the plurality of first solder bumps and adjacent to the plurality of first solder bumps a portion of the first solder mask, the plurality of openings respectively exposing the plurality of second electrical contact pads. The plurality of second solder bumps are respectively formed on the plurality of second electrical contact pads. The first wafer has contact bumps in one-to-one correspondence with the plurality of first solder bumps, The plurality of contact bumps are respectively connected to the corresponding first solder bumps and electrically connected, and the first wafer and the first solder resist layer are filled with an underfill to fix the first wafer.

The chip package substrate has a dry film type solder mask layer, and the dry film type solder resist layer can effectively block the underfill agent from contaminating the second electrical contact when being filled between the first wafer and the first chip package substrate. Pads to enhance the quality of the chip package substrate and the chip package structure.

10‧‧‧First circuit board

11‧‧‧First basal layer

12‧‧‧First conductive line pattern

13‧‧‧Second conductive line pattern

14‧‧‧First solder mask

15‧‧‧Second solder mask

111‧‧‧ first surface

112‧‧‧ second surface

121‧‧‧First electrical contact pads

122‧‧‧Second electrical contact pads

131‧‧‧ Third electrical contact pad

124‧‧‧First solder bump

17‧‧‧Dry film type solder mask

171‧‧‧镂空部

172‧‧‧ openings

125‧‧‧Second solder bumps

20‧‧‧First chip package substrate

30‧‧‧First chip

40‧‧‧First chip package structure

70‧‧‧Second chip package structure

80,90‧‧‧ wafer stacking structure

31‧‧‧Contact bumps

32‧‧‧Bottom filler

34‧‧‧ solder balls

51‧‧‧second circuit board

52‧‧‧Second basal layer

53‧‧‧ Third conductive circuit pattern

54‧‧‧fourth conductive line pattern

55‧‧‧The third solder mask

56‧‧‧four solder mask

521‧‧‧ third surface

522‧‧‧ fourth surface

57‧‧‧Electrical hole

531,531a‧‧‧4th electrical contact pad

551‧‧‧Fixed area

541‧‧‧ fifth electrical contact pad

58‧‧‧Surface treatment layer

60, 60a‧‧‧second chip package substrate

50, 50a‧‧‧second chip

501‧‧‧bond wire

502‧‧ ‧ adhesive layer

59,59a‧‧‧Package colloid

542‧‧‧First solder ball

132‧‧‧Second solder ball

91a‧‧‧ solder balls

92a‧‧‧Second bottom filler

1 is a cross-sectional view of a first circuit board according to a first embodiment of the present invention.

2 is a top plan view of the first circuit board of FIG. 1.

Figure 3 is a cross-sectional view showing the first solder bump formed on the first wiring board of Figure 1.

Figure 4 is a cross-sectional view showing the dry film type solder resist layer formed on the first wiring board of Figure 3.

Figure 5 is a cross-sectional view showing the selective etching of the dry film type solder mask of the first wiring board of Figure 4 to expose the surface of the plurality of second electrical contact pads.

6 is a cross-sectional view of the first chip package substrate formed after the second solder bump is formed on the surface of the second electrical contact pad exposed from the dry film type solder mask on the first wiring board of FIG. 5.

7 is a cross-sectional view showing the first wafer placed on the first chip package substrate of FIG. 6.

Figure 8 is a cross-sectional view of the first wafer and the first wafer package substrate of Figure 7 after filling the underfill.

Figure 9 is a cross-sectional view showing a second wiring board according to a first embodiment of the present invention.

Figure 10 is a plan view of the second circuit board of Figure 9.

Figure 11 is a cross-sectional view showing a second chip package substrate formed after depositing a surface treatment layer on the second wiring board of Figure 10.

Figure 12 is a cross-sectional view showing the second wafer package substrate of Figure 11 after the second wafer is attached.

Figure 13 is a cross-sectional view showing the encapsulant coated with the second wafer and the second wafer package substrate of Figure 12 .

14 is a cross-sectional view showing a second chip package structure formed after forming a plurality of first solder balls on the second chip package substrate in FIG.

15 is a cross-sectional view showing the second wafer package structure of FIG. 14 fixedly connected to the first chip package structure of FIG.

16 is a cross-sectional view showing a wafer stack package structure formed after forming a plurality of second solder balls on the first wafer package structure in FIG.

Figure 17 is a cross-sectional view showing a wafer stack package structure according to a second embodiment of the present invention.

Referring to FIG. 1 to FIG. 17 , a first embodiment of the present invention provides a method for fabricating a chip package structure, including the following steps:

In the first step, referring to FIG. 1 and FIG. 2, a first circuit board 10 is provided. The first circuit board 10 includes a first base layer 11 and first conductive layers respectively disposed on opposite surfaces of the first base layer 11. The line pattern 12 and the second conductive line pattern 13, and the first solder resist layer 14 and the second solder resist layer 15 respectively formed on the first conductive line pattern 12 and the second conductive line pattern 13.

The first substrate layer 11 is a multi-layer substrate comprising a plurality of resin layers alternately arranged and a plurality of layers of conductive trace patterns (not shown). The first substrate layer 11 includes a first first The first conductive trace pattern 12 is disposed on the first surface 111 of the first base layer 11 , and the second conductive trace pattern 13 is disposed on the second surface 112 of the first base layer 11 . on. The plurality of conductive trace patterns of the first base layer 11 and the plurality of conductive trace patterns of the first base layer 11 and the first conductive trace pattern 12 and the second conductive trace pattern 13 respectively pass through the conductive vias (not shown) ) Electrical connection.

The first solder resist layer 14 covers a portion of the first conductive trace pattern 12 and the first surface 111 exposed from the first conductive trace pattern 12 to expose a portion of the first conductive trace pattern 12 from the first solder resist layer 14 The plurality of first electrical contact pads 121 and the plurality of second electrical contact pads 122 are formed. The first electrical contact pads 121 are arranged in an array, and the plurality of second electrical contact pads 122 are disposed around the plurality of first electrical contact pads 121. As shown in FIG. 2, the electrical contact pads inside the dotted frame are The first electrical contact pads 121 , the electrical contact pads on the outside of the dashed frame are the second electrical contact pads 122 , and the plurality of second electrical contact pads 122 are disposed around the plurality of first electrical contact pads 121 .

The second solder resist layer 15 covers a portion of the second conductive trace pattern 13 and the second surface 112 exposed from the second conductive trace pattern 13 to expose a portion of the second conductive trace pattern 13 from the second solder resist layer 15 The plurality of third electrical contact pads 131 are formed, and the third electrical contact pads 131 are arranged in an array. The plurality of first electrical contact pads 121 and the plurality of second electrical contact pads 122 pass through the first conductive trace pattern 12, the conductive traces of the second conductive trace pattern 13, and the conductive trace patterns and conductive vias in the first base layer 11. The plurality of third electrical contact pads 131 are electrically connected.

The first conductive line pattern 12 and the second conductive line pattern 13 can be formed by selectively etching a copper layer. In this embodiment, the first circuit board 10 is a double-sided circuit board. Of course, it should be noted that the first circuit board 10 can be a rigid circuit board. The flexible circuit board may be a flexible circuit board. When the first circuit board 10 is a flexible circuit board, the second conductive circuit pattern 13 of the first circuit board 10 may further be provided with a reinforcing piece to support the first process. A circuit board 10 is removed after the wafer is packaged.

In the second step, referring to FIG. 3, first solder bumps 124 are formed on the surface of the plurality of first electrical contact pads 121, respectively.

In this embodiment, a plurality of first solder bumps 124 are respectively formed on the surface of the plurality of first electrical contact pads 121 by electroplating or printing, and the plurality of first solder bumps 124 protrude from the first The surface of the solder resist layer 14. The first solder bumps 124 may be columnar, spherical, or the like. In this embodiment, they are columnar, and the material thereof generally includes mainly tin.

In the third step, referring to FIG. 4, a dry film type solder resist layer 17 is formed on the surface of the first solder resist layer 14, and the dry film type solder resist layer 17 is hollowed out corresponding to the area of the plurality of first solder bumps 124 to form a hollow. Part 171. The dry film type solder resist layer 17 covers a portion of the surface of the first solder resist layer 14 around the region where the plurality of first solder bumps 124 are located, and completely covers the surface of the plurality of second electrical contact pads 122. The hollow portion 171 completely exposes the plurality of first solder bumps 124 and a portion of the first solder resist layer 14 surrounding the plurality of first solder bumps 124 and adjacent to the plurality of first solder bumps 124, the hollow portion An edge of the 171 surrounds the periphery of the plurality of first solder bumps 124.

The dry film type solder resist layer 17 is formed by mechanical cutting or laser cutting before covering the first solder resist layer 14, and then formed on the surface of the first solder resist layer 14 by press bonding. . In this embodiment, the thickness of the dry film type solder resist layer 17 is greater than the height of the first solder bump 124 protruding from the first solder resist layer 14.

In the fourth step, referring to FIG. 5, a plurality of openings 172 respectively corresponding to the plurality of second electrical contact pads are formed on the dry film type solder mask layer 17, and the surfaces of the plurality of second electrical contact pads 122 are respectively The plurality of openings 172 are exposed to the dry film type solder resist layer 17. The method of forming the plurality of openings 172 may be selective etching, exposure development, or laser etching.

In the fifth step, referring to FIG. 6, the second solder bumps 125 are respectively formed on the surface of the plurality of second electrical contact pads 122, thereby forming the first chip package substrate 20.

In this embodiment, a plurality of second solder bumps 125 may be respectively formed on the surface of the plurality of second electrical contact pads 122 by electroplating or printing, and the plurality of second solder bumps 125 protrude from the dry film. The surface of the solder resist layer 17. The second solder bumps 125 may be columnar, spherical, or the like. In this embodiment, they are columnar, and the material thereof is generally mainly tin.

The first chip package substrate 20 includes a first base layer 11, a first conductive trace pattern 12, a second conductive trace pattern 13, a first solder resist layer 14, a second solder resist layer 15, and a dry film solder resist layer 17. The first substrate layer 11 includes an opposite first surface 111 and a second surface 112. The first conductive trace pattern 12 is disposed on the first surface 111 of the first substrate layer 11. The second conductive trace pattern 13 is disposed on the first substrate 111. On the second surface 112 of the first substrate layer 11, the first conductive trace pattern 12 and the second conductive trace pattern 13 are electrically connected to each other through the conductive trace pattern and the conductive vias in the first base layer 11.

The first solder resist layer 14 covers a portion of the first conductive trace pattern 12 and the first surface 111 exposed from the first conductive trace pattern 12 to expose a portion of the first conductive trace pattern 12 from the first solder resist layer 14 The plurality of first electrical contact pads 121 and the plurality of second electrical contact pads 122 are formed. The first electrical contact pads 121 are arranged in an array, and the plurality of second electrical contact pads 122 are disposed around the plurality of first electrical contact pads 121. The second solder resist layer 15 covers a portion of the second conductive trace pattern 13 and the second conductive trace pattern The exposed second surface 112 of the shape 13 exposes a portion of the second conductive trace pattern 13 from the second solder resist layer 15 to form a plurality of third electrical contact pads 131. The third electrical contact pads 131 are arranged in an array. cloth. The plurality of first electrical contact pads 121 and the plurality of second electrical contact pads 122 pass through the conductive lines of the first conductive trace pattern 12 and the second conductive trace pattern 13 and the conductive trace patterns and conductive vias in the first base layer 11 The plurality of third electrical contact pads 131 are electrically connected.

The surfaces of the plurality of first electrical contact pads 121 are respectively formed with first solder bumps 124 protruding from the surface of the first solder resist layer 14. The first solder bumps 124 may be columnar, spherical, or the like. In this embodiment, they are columnar, and the material thereof generally includes mainly tin.

The dry film type solder resist layer 17 covers a part of the surface of the first solder resist layer 14 , and the dry film type solder resist layer 17 has a hollow portion 171 corresponding to the region where the plurality of first solder bumps 124 are located, and the hollow portion 171 The plurality of first solder bumps 124 and a portion of the first solder resist layer 14 surrounding the plurality of first solder bumps 124 and adjacent to the plurality of first solder bumps 124 are completely exposed. The surface of the plurality of second electrical contact pads 122 is exposed on the dry film solder resist layer 17, and the plurality of second solder bumps 125 are respectively formed on the surface of the plurality of second electrical contact pads 122, and the plurality of second solders The bumps 125 protrude from the surface of the dry film type solder resist layer 17.

The first chip package substrate 20 may further encapsulate the first wafer 30 thereon by a subsequent step to form a first chip package structure 40, and package the second chip package structure 70 on the first chip package structure 40 to form The wafer stacks the package structure 80. Of course, the first chip package substrate 20 can also be packaged and shipped to a wafer packaging factory for subsequent wafer packaging. The specific chip packaging steps are as described in steps 6 through 14.

In a sixth step, referring to FIG. 7, a first wafer 30 is provided. The first wafer 30 is a flip-chip wafer, and the first wafer 30 has a first and a plurality of first electrical contact pads 121, respectively. Corresponding plurality of contact bumps 31 are connected to the corresponding first solder bumps 124 and electrically connected.

The contact bumps 31 are also typically made of solder, the material of which is primarily tin. The connection between the plurality of contact bumps 31 and the corresponding first solder bumps 124 may be as follows: First, the first wafer 30 is disposed on the first chip package substrate 20, and the plurality of contact bumps 31 are respectively corresponding to The first solder bumps 124 are in contact with each other; then, the first wafer 30 and the first chip package substrate 20 are passed through a reflow oven, and the contact bumps 31 and the first solder bumps 124 are melted and combined to be cooled and solidified. The contact bump 31 and the first solder bump 124 are connected to each other and electrically connected. As shown in FIG. 8, the contact bump 31 and the first solder bump 124 are fusion bonded to form a solder ball 34.

In the seventh step, referring to FIG. 8 , the underfill 32 is filled in the gap between the first wafer 30 and the first chip package substrate 20 to package the first wafer 30 and the first chip package substrate 20 . . The underfill 32 bonds the surface of the first wafer 30 and the surface of the first solder resist layer 14 and surrounds the solder balls 34 formed by the fusion bonding of the contact bumps 31 and the first solder bumps 124 to form a first chip package. Structure 40.

The filling of the underfill 32 is performed by capillary action to infiltrate the material of the liquid underfill 32 from the edge of the first wafer 30 to the inner region between the first wafer 30 and the first wafer package substrate 20. The underfill 32 is typically an epoxy such as the underfill material Loctite 3536.

The first chip package substrate 20 in the first chip package structure 40 of the present embodiment has a dry film type solder resist layer 17 which can effectively block the underfill 32 from being filled in the first wafer 30. Contaminating the second electrical property with the first chip package substrate 20 Contact pad 122.

In the eighth step, referring to FIG. 9 and FIG. 10, a second circuit board 51 is provided. The second circuit board 51 includes a second base layer 52, and third conductive layers respectively disposed on opposite surfaces of the second base layer 52. A line pattern 53 and a fourth conductive line pattern 54, and a third solder resist layer 55 and a fourth solder resist layer 56 formed on the third conductive line pattern 53 and the fourth conductive line pattern 54, respectively.

In this embodiment, the second substrate layer 52 may be a flexible resin layer, such as Polyimide (PI), Polyethylene Terephthalate (PET) or polyethylene naphthalate. Polythylene Naphthalate (PEN) may also be a hard resin layer such as an epoxy resin, a fiberglass cloth or the like. The second substrate layer 52 includes an opposite third surface 521 and a fourth surface 522. The third conductive trace pattern 53 is disposed on the third surface 521 of the second substrate layer 52. The fourth conductive trace pattern 54 is disposed on The fourth surface 522 of the second substrate layer 52 is on the fourth surface 522. The third conductive line pattern 53 and the fourth conductive line pattern 54 are electrically conducted through the plurality of conductive holes 57.

The third solder resist layer 55 covers a portion of the third conductive trace pattern 53 and the third surface 521 exposed from the third conductive trace pattern 53 to expose a portion of the third conductive trace pattern 53 from the third solder resist layer 55. A plurality of fourth electrical contact pads 531 are formed. The surface of the third solder resist layer 55 has a wafer holding region 551. As shown in FIG. 10, the area enclosed by the broken line frame is a wafer holding portion 551 for fixing the wafer thereon. The plurality of fourth electrical contact pads 531 are disposed around the wafer holding area 551.

The fourth solder resist layer 56 covers a portion of the fourth conductive trace pattern 54 and the fourth surface 522 of the second base layer 52 exposed from the fourth conductive trace pattern 54 such that the portion of the fourth conductive trace pattern 54 is from the first The four solder resist layers 56 are exposed to form a plurality of fifth electrical contacts The pad 541, the plurality of fifth electrical contact pads 541 are in one-to-one correspondence with the plurality of second solder bumps 125. The plurality of fourth electrical contact pads 531 are electrically conducted to the plurality of fifth electrical contact pads 541 through the conductive lines of the third conductive trace pattern 53 and the fourth conductive trace pattern 54 and the conductive vias 57.

The third conductive line pattern 53 and the fourth conductive line pattern 54 may be formed by selectively etching a copper layer. In this embodiment, the second circuit board 51 is a double-sided circuit board. Of course, the second circuit board 51 can also be a multi-layer board with more than two layers of conductive circuit patterns, that is, the second base layer 52 can be a multi-layer substrate. The multilayer resin layer and the multilayer conductive wiring pattern are alternately arranged.

In the ninth step, referring to FIG. 11, the surface of the plurality of fourth electrical contact pads 531 is plated with gold to form a plurality of surface treatment layers 58 to protect the plurality of fourth electrical contact pads 531 from oxidation and facilitate subsequent wire bonding. Thereby, the second chip package substrate 60 is formed.

In the tenth step, referring to FIG. 12, a second wafer 50 is provided. The second wafer 50 is a wire bonding (WB) wafer, and the second wafer 50 is electrically connected to the fourth electrical contact pad 531. Specifically, the second wafer 50 has a plurality of bonding contacts and a plurality of bonding wires 501 extending from the plurality of bonding contacts, and the bonding wires 501 are in one-to-one correspondence with the fourth electrical contact pads 531. One end of the plurality of bonding wires 501 is electrically connected to the second wafer 50, and the other end is electrically connected to the surface treatment layer 58 of the surface of the plurality of fourth electrical contact pads 531, thereby making the second wafer 50 and the third conductive line The graphic 53 is electrically connected.

Preferably, the second wafer 50 is fixed to the wafer fixing area 551 on the surface of the third solder resist layer 55 by an adhesive layer 502, and the bonding wire 501 can be connected to the corresponding surface treatment layer 58 by soldering. The material of the bonding wire 501 is generally gold.

In the eleventh step, referring to FIG. 13, the molding process is performed, and the third solder resist 55 and the fourth electrical contact exposed by the bonding wires 501, the second wafer 50 and the second chip package substrate 60 are encapsulated by the encapsulant 59. The surface treatment layer 58 on the surface of the pad 531 is encapsulated. The bonding wires 501 and the second wafer 50 are completely covered in the encapsulant 59. In this embodiment, the encapsulant 59 is a black rubber. Of course, the encapsulant 59 can also be encapsulated with other materials, and is not limited to this embodiment.

In the twelfth step, referring to FIG. 14, the balls are respectively soldered on the surface of the plurality of fifth electrical contact pads 541 to form a plurality of first solder balls 542 to form a second chip package structure 70.

The material of the first solder ball 542 generally includes tin. The first solder ball 542 can be fabricated by a method of template ball implantation, and specifically includes the steps of: printing or coating the surface of the plurality of fifth electrical contact pads 541. Solder; then the solder ball is placed on the corresponding fifth electrical contact pad 541 by a template. Of course, the first solder ball 542 can also be formed by other ball placement methods, such as spray solder paste ball, laser ball placement, etc., and is not limited to this embodiment.

The second chip package structure 70 includes a second chip package substrate 60, a second wafer 50, an encapsulant 59, and a plurality of first solder balls 542. The second wafer 50 is fixed to the wafer fixing area 551 of the surface of the third solder resist layer 55 by an adhesive layer 502. The second wafer 50 has a plurality of bonding contacts and a plurality of bonding wires extending from the plurality of bonding contacts. 501. The bonding wires 501 are in one-to-one correspondence with the fourth electrical contact pads 531. One end of the plurality of bonding wires 501 is electrically connected to the second wafer 50, and the other end is electrically connected to the surface treatment layer 58 of the surface of the plurality of fourth electrical contact pads 531, thereby realizing the second wafer 50 and the third conductive The line pattern 53 is electrically connected. The bonding wires 501, the second solder mask layer 55 exposed on the second wafer 50 and the second chip package substrate 60, and the surface treatment layer 58 on the surface of the fourth electrical contact pad 531 are all packaged in the encapsulant 59. The first first welding The ball 542 is in one-to-one correspondence with the plurality of fifth electrical contact pads 541, respectively formed on the corresponding fifth electrical contact pads 541, and the first solder balls 542 protrude from the surface of the fourth solder resist layer 56.

Referring to FIG. 15 , the second chip package structure 70 is connected and fixed to the first chip package structure 40 , and the plurality of first solder balls 542 are respectively physically connected and electrically conductive with the corresponding second solder bumps 125 . through.

The plurality of first solder balls 542 are physically connected to the corresponding second solder bumps 125 and electrically connected to each other by: placing the second chip package structure 70 on the first chip package structure 40 and Each of the first solder balls 542 is in contact with the corresponding second solder bumps 125; then the second chip package structure 70 and the first chip package structure 40 are integrally passed through the reflow oven so that each of the first solder balls 542 is respectively After being melt-bonded with the corresponding second solder bumps 125, the film is cooled and solidified, thereby achieving connection and fixing of the second chip package structure 70 to the first chip package structure 40.

In the fourteenth step, referring to FIG. 16, the balls are respectively soldered on the surface of the plurality of third electrical contact pads 131 to form a plurality of second solder balls 132, thereby forming a package on package (PoP) package structure 80. The material of the second solder ball 132 generally comprises mainly tin, which is formed in a similar manner to the formation of the first solder ball 542. The second solder ball 132 protrudes from the surface of the second solder resist layer 15 for electrical connection with other electronic devices such as a computer motherboard.

The wafer stack package structure 80 includes the first chip package structure 40, the second chip package structure 70, and a plurality of second solder balls 132. The first chip package structure 40 and the second chip package structure 70 are fused by the plurality of first solder balls 542 and the plurality of second solder bumps 125 to achieve mutual connection and electrical connection. The plurality of second solder balls 132 are respectively formed on the surface of the plurality of third electrical contact pads 131 and protrude from the second solder resist The surface of layer 15 is used to electrically connect to other electronic devices such as computer motherboards. The first wafer 30 is electrically connected to the second solder ball 132 through the first electrical contact pad 121 , the conductive trace pattern in the first base layer 11 , and the conductive via and the third electrical contact pad 131 . The second wafer 50 is electrically connected to the fourth electrical contact pad 531, the conductive via 57, the second electrical contact pad 122, the conductive trace pattern in the first substrate layer 11, and the conductive via and the third electrical contact pad 131. The second solder ball 132.

The first chip package structure 40 of the present embodiment has a dry film type solder resist layer 17 on the surface of the first electrical contact pad 121, and a portion of the second solder bump 125 is embedded in the dry film type solder resist. In the layer 17, when the second solder bumps 125 are set to a predetermined height, the dry film solder resist layer 17 exposes the second solder bumps 125 to a height outside the first chip package substrate 20, In the case where the surface tension of the material of the liquid second solder bumps 125 is the same, the cross section of the formed second solder bumps 125 can be made small, so that the second solder bumps 125 can be on the first chip package substrate 20 The higher the density of the arrangement, the more favorable the packaging of the wafer with high-density leads, the more flexible the design of the wafer.

Referring to FIG. 17, a second embodiment of the present invention provides a wafer stack package structure 90, which is similar in structure to the wafer stack package structure 80 of the first embodiment, except that the wafer stack package structure 90 is The second wafer 50a is a flip chip package, and the second wafer 50a and the second chip package substrate 60a of the wafer stack package 90 are packaged in a flip chip package. The fourth electrical contact pads 531a of the second chip package substrate 60a are distributed in an array. The surface of the plurality of fourth electrical contact pads 531a and the second wafer 50a have a plurality of solder balls 91a. The plurality of solder balls 91a will A plurality of fourth electrical contact pads 531a are connected to the second wafer 50a and electrically connected. a second underfill 92a is filled in the second wafer 50a and the second chip package base Between the plates 60a, the second underfill 92a bonds the surface of the second wafer 50a and the surface of the second chip package substrate 60a and surrounds the plurality of solder balls 91a. The encapsulant 59a completely covers the exposed surface of the second wafer 50a and the second chip package substrate 60a. It can be understood that, in this embodiment, since the second underfill 92a has fixedly packaged the second wafer, the encapsulant 59a may also be omitted.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be covered by the following claims.

20‧‧‧First chip package substrate

30‧‧‧First chip

32‧‧‧Bottom filler

14‧‧‧First solder mask

34‧‧‧ solder balls

40‧‧‧First chip package structure

Claims (14)

A method for fabricating a chip package substrate, comprising the steps of: providing a circuit board, comprising: a base layer; a first conductive line pattern disposed on a surface of the base layer; and a first conductive line pattern formed on the first conductive line pattern and partially covering the first conductive line pattern a first solder resist layer, the portion of the first conductive trace pattern exposed from the first solder resist layer constitutes a plurality of first electrical contact pads and a plurality of second electrical contact pads, the plurality of second electrical contact pads surrounding the plurality The first electrical contact pads are respectively disposed on the plurality of first electrical contact pads, and the plurality of first solder bumps are respectively electrically connected to the corresponding first electrical contact pads; Forming a dry film type solder resist layer on the solder resist layer, the dry film type solder resist layer having a hollow portion that completely exposes the plurality of first solder bumps and surrounding the plurality of first solder bumps and a portion of the first solder mask adjacent to the first solder bump, the dry film solder mask completely covering the plurality of second electrical contact pads; forming a plurality of openings on the dry film solder mask to expose the plurality Plural second electrical a second solder bump is respectively formed on the plurality of second electrical contact pads, and the plurality of second solder bumps are electrically connected to the corresponding second electrical contact pads, respectively, and the plurality of second solder bumps The surface of the dry film type solder resist layer is protruded to form a chip package substrate. The method of fabricating a chip package substrate according to claim 1, wherein the circuit board further comprises a second conductive trace pattern and a second solder resist layer, the second conductive trace pattern being formed on the base layer away from the first conductive a surface of the circuit pattern, the second solder resist layer is formed on the second conductive trace pattern, the second solder resist layer partially covers the second conductive trace pattern, and the second conductive trace pattern is exposed from the second solder resist layer The portion constitutes a plurality of third electrical contact pads, and the first conductive trace pattern is electrically connected to the second conductive trace pattern. A chip package substrate includes a first substrate layer, a first conductive line pattern formed on a surface of the first substrate layer, and a first solder resist layer formed on the first conductive line pattern, the first solder mask partially covering The first conductive trace pattern, the first conductive trace pattern exposed from the first solder resist layer constitutes a plurality of first electrical contact pads and a plurality of second electrical contact pads, the plurality of second electrical contact pads surrounding the plurality of An electrical contact pad is disposed, wherein the plurality of first electrical contact pads are formed with a first solder bump, wherein the chip package substrate further comprises a dry film solder mask layer and a plurality of second solder bumps, the stem The film type solder resist layer has a hollow portion and a plurality of openings, the hollow portion completely exposing the plurality of first solder bumps and a portion surrounding the plurality of first solder bumps and adjacent to the plurality of first solder bumps a first solder mask, the plurality of openings respectively exposing the plurality of second electrical contact pads, the plurality of second solder bumps being respectively formed on the plurality of second electrical contact pads, and protruding from the dry film type solder mask Layer surface The chip package substrate of claim 3, wherein the circuit board further comprises a second conductive trace pattern and a second solder resist layer, the second conductive trace pattern being formed on the first base layer away from the first conductive trace a surface of the pattern, the second solder resist layer is formed on the second conductive trace pattern, the second solder resist layer partially covers the second conductive trace pattern, and the second conductive trace pattern is exposed from the second solder resist layer The portion constitutes a plurality of third electrical contact pads, and the first conductive trace pattern is electrically connected to the second conductive trace pattern. A method of fabricating a chip package structure, comprising the steps of: providing a chip package substrate as claimed in claim 3 as a first chip package substrate; providing a first wafer having the first plurality of solder bumps a plurality of corresponding contact bumps; the plurality of contact bumps are respectively connected to the corresponding first solder bumps and electrically connected; and the underfill is infiltrated by capillary action and filled in the first wafer and the first Between a chip package substrate, the first wafer is fixed to the first chip package substrate, thereby forming a first chip package structure. The method of fabricating a chip package structure according to claim 5, further comprising the steps of: providing a second chip package structure, comprising: a second chip package substrate and a second wafer packaged on the second chip package substrate, the The two-chip package substrate includes a second substrate layer, a third conductive line pattern and a fourth conductive line pattern respectively formed on opposite surfaces of the second substrate layer, and are respectively formed on the third conductive line pattern and the fourth conductive line pattern a third solder mask layer and a fourth solder resist layer, the third conductive trace pattern is electrically connected to the fourth conductive trace pattern, the third solder resist layer partially covering the third conductive trace pattern, the third conductive trace pattern The portion exposed from the third solder resist layer constitutes a plurality of fourth electrical contact pads, the fourth solder mask layer partially covering the fourth conductive trace pattern, and the portion of the fourth conductive trace pattern exposed from the fourth solder resist layer Forming a plurality of fifth electrical contact pads, the second chip is packaged on a side of the third solder resist layer of the second chip package substrate and electrically connected to the plurality of fourth electrical contact pads, the first The fifth electrical contact pads are in one-to-one correspondence with the second solder bumps; the ball is respectively soldered on the surface of the plurality of electrical contact pads to form a plurality of first solder balls; and the plurality of first solder balls are respectively corresponding to The second solder bumps are physically connected and electrically connected to connect the second chip package structure to the first chip package structure. The method of fabricating a chip package structure according to claim 6, wherein the first chip package substrate further comprises a second conductive trace pattern and a second solder resist layer, the second conductive trace pattern being formed on the first base layer A second solder resist layer is formed on the second conductive trace pattern, the second solder resist layer partially covers the second conductive trace pattern, and the second conductive trace pattern is from the surface The exposed portions of the two solder resist layers constitute a plurality of third electrical contact pads, and the first conductive trace pattern is electrically connected to the second conductive trace pattern. The method of fabricating a chip package structure according to claim 7, further comprising the steps of: respectively soldering balls on the plurality of third electrical contact pads to form a plurality of second solder balls. The method of fabricating a chip package structure according to claim 6, wherein the second wafer is a wire bonding wafer, and the second wafer and the plurality of fourth electrical contact pads are connected to the plurality of fourth electrical contacts. The plurality of corresponding bonding wires are electrically connected to the touch pads, and the second chip package further comprises an encapsulant, the third colloid and the third solder resist layer exposed on the bonding wires, the second wafer and the second chip package substrate Four electrical contact pads cover the package. The method of fabricating a chip package structure according to claim 6, wherein the second wafer is packaged on the second chip package substrate by flip chip packaging. A chip package structure includes: a first chip package substrate, a first substrate layer, a first conductive trace pattern formed on a surface of the first substrate layer, a first solder resist layer formed on the first conductive trace pattern, a dry film type solder resist layer formed on the first solder resist layer and a plurality of second solder bumps, the first solder resist layer partially covering the first conductive trace pattern, and the first exposed from the first solder resist layer The conductive circuit pattern constitutes a plurality of first electrical contact pads and a plurality of second electrical contact pads, the plurality of second electrical contact pads are disposed around the plurality of first electrical contact pads, and the plurality of first electrical contact pads are formed thereon a first solder bump, the dry film solder resist layer has a hollow portion and a plurality of openings, the hollow portion completely exposing the plurality of first solder bumps and surrounding the plurality of first solder bumps and the plurality a portion of the first solder mask adjacent to the solder bump, the plurality of openings respectively exposing the plurality of second electrical contact pads, the plurality of second solder bumps being respectively formed on the plurality of second electrical contact pads, and convex Out of this dry film type solder mask And a first wafer having a contact bump corresponding to the plurality of first solder bumps, wherein the plurality of contact bumps are respectively connected to the corresponding first solder bumps and electrically connected, An underfill is filled between the first wafer and the first solder resist layer to fix the first wafer. The chip package structure of claim 11, wherein the chip package structure further comprises a second chip package substrate and a second wafer packaged on the second chip package substrate, the second chip package substrate comprising a second substrate layer a third conductive trace pattern and a fourth conductive trace pattern respectively formed on opposite surfaces of the second base layer, and third solder resist layers and fourth formed on the third conductive trace pattern and the fourth conductive trace pattern, respectively Solder mask, the third conductive line The pattern is electrically connected to the fourth conductive line pattern, the third solder mask layer partially covers the third conductive line pattern, and the portion of the third conductive line pattern exposed from the third solder resist layer constitutes a plurality of fourth electrical contact pads The fourth solder mask layer partially covers the fourth conductive trace pattern, the portion of the fourth conductive trace pattern exposed from the fourth solder resist layer constitutes a plurality of fifth electrical contact pads, and the second chip is encapsulated in the second The third solder resist layer side of the chip package substrate is electrically connected to the plurality of fourth electrical contact pads, and the fifth electrical contact pads are in one-to-one correspondence with the second solder bumps, and each of the fifth electrical contact pads The surfaces are each formed with a first solder ball that is physically and electrically connected to the corresponding second solder bump. The chip package structure of claim 12, wherein the second wafer is a wire bonding wafer, and the second wafer and the plurality of fourth electrical contact pads are in one-to-one correspondence with the plurality of fourth electrical contact pads. The plurality of bonding wires are electrically connected, the second chip package structure further comprising an encapsulant, the encapsulation colloid, the third solder mask and the fourth electrical contact pad exposed on the bonding wires, the second chip and the second chip package substrate Overlay. The chip package structure of claim 12, wherein the second wafer is packaged on the second chip package substrate by flip chip packaging.