JPH11273253A - Pulse width control circuit and disk recording control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a desired pulse waveform without using a high speed clock by selecting output signals of respective delay elements of a second delay circuit which inputs the output which is to be obtained by allowing a logical circuit to logically operate the input signal selected by a selection circuit and the delayed signal in which outputs of respective delay elements of a first delay circuit which makes the input signal its input is selected. SOLUTION: A delay circuit 10 inputs the output signal (EFMD)2 which is selected by a selection signal SW in a selecting circuit 23 and a selector 11 selects output signals of respective delay elements 40 in accordance with a select signal SEL1. An AND gate 12 logically operates the EFMD2 and the delayed signal selected by the selctor 11 to output the result to a delay circuit 30. A selector 31 selects output signals of respective delay elements 40 in accorance with a select signal SEL2 and an output signal WDAT in which the phase of a signal in which the pulse width of the input signal EFM is controlled is controlled is outputted. Thus, delay quantities are set highly accurately and proper recordings made to correspond to kinds of media and rotational speeds of the media are made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width control circuit comprising a delay circuit in which a plurality of delay elements are connected,
Also, the present invention relates to a disk recording control circuit capable of adjusting the recording timing of a recording mark using the pulse width control circuit in a disk recording device.

[0002]

2. Description of the Related Art Some optical disk devices and magneto-optical disk devices are capable of writing data as well as reproducing data. In such a device, a recording mark corresponding to a data modulation signal is formed on a disk by a laser device. The data is written on the recording medium by recording the data on the recording medium.

For example, in a CD-R, first, data to be written is modulated into an EFM signal by an EFM encoder, and the EFM signal is transmitted to a laser device so that a recording mark corresponding to the EFM signal is recorded on a disk. ing. However, since the recording state changes depending on the type of media on which data is recorded and the rotation speed of the disc,
By simply sending an EFM signal to the laser device,
The desired recording mark cannot be recorded. Therefore,
Attempts have been made to record a desired recording mark by delaying the rising and falling timings of the EFM signal. And like this, EFM
To delay a signal, generally, a plurality of logic circuits such as D flip-flops operating in synchronization with a clock are connected and used.

[0004]

The EFM signal is an EFM signal.
A signal synchronized with a reference signal called a clock,
It has a pulse width of 3 to 11 cycles of this clock. Therefore, as described above, D which operates in synchronization with the clock
When a delay circuit is constituted by flip-flops, a clock higher than the EFM clock must be used as a clock applied to the D flip-flop. A clock that is twice as fast is required.

[0005] However, this EFM clock is originally a clock having a considerably high frequency.
28 MHz "and" 34.56 MHz "at 8 × speed. Therefore, the clock applied to the D flip-flop is extremely high, ie, “276.48 MHz” at 4 × speed and “552.96 MHz” at 8 × speed. For this reason, it is actually impossible to supply such a high-speed clock, and it is extremely difficult to produce a logic circuit that operates stably in synchronization with such a high-speed clock.

Further, since the logic circuit is susceptible to external factors such as power supply fluctuation and temperature change, it is difficult to control with high accuracy when the pulse width to be controlled is very short.

[0007]

According to the present invention, there is provided a logic circuit for delaying an input signal for a predetermined period according to a reference clock, a logic operation output signal of an output signal of the logic circuit and the input signal being input to one end, and A selection circuit that inputs the input signal to one end and selects one of them according to information indicating pulse width reduction / expansion, and first and second delay circuits that delay input signals by connecting a plurality of delay elements A delay circuit, and first and second output circuits for selecting one of the output signals of each delay element stage for each of the first and second delay circuits and outputting the selected signal as a delay signal
And a logic circuit for performing a logical operation on the input signal of the first delay circuit and the delay signal of the first selector, and the signal selected by the selection circuit is provided to the first delay circuit. An output signal of the logic circuit as a second input signal;
Or the signal selected by the selection circuit is used as the input signal of the second delay circuit, and the delay signal from the second selector is used as the input signal of the first delay circuit. As a pulse width control circuit.

Further, in the present invention, the delay circuit is constituted by connecting a plurality of delay elements in a ring shape, and a VCO controlled by a control voltage to which a delay amount of each stage is input, and an output of the VCO. A phase comparator for inputting a signal or a frequency-divided signal thereof and a reference signal and comparing the phases of the two signals; a low-pass filter for generating the control voltage according to a phase difference detected by the phase comparator; A plurality of delay elements having the same configuration as the delay element are connected to each other, and a delay line is provided, which delays and outputs an input signal and controls the delay amount of each stage by the control voltage. I do.

Further, in the present invention, a disk recording control circuit is constituted by the pulse width control circuit, a modulation signal to be recorded is supplied as an input signal, and a select signal corresponding to the type and / or rotation speed of the medium is supplied to the disk recording control circuit. An output signal that is input to the first and second selectors and is sent to a recording device that records a recording mark corresponding to the modulation signal on a disc, so that the recording timing of the recording mark can be adjusted.

[0010]

FIG. 1 is a block diagram showing an embodiment of a pulse width control circuit according to the present invention, in which a pulse width of an input signal is controlled and a phase of a pulse width-controlled signal is controlled. For example, two delay circuits 10 and 30 are used. Each of the delay circuits 10 and 30 is configured by connecting a plurality of delay elements 40 composed of inverters in series, and outputs one of the output signals of each stage to the select signals SEL1 and SE.
Selectors 11 and 31 that select according to L2 are connected to the delay circuits 10 and 30, respectively. Further, selector 1
1. An AND gate 12 for inputting the delay signal selected in 1 and an input signal to the delay circuit 10 is provided.
2 are supplied as input signals to the delay circuit 30.

Here, each of the delay circuits 10 and 30 is configured by connecting 16 stages of delay elements 40, and the delay amount dt of one delay element is 1/16 of the period T of EFMCK as a reference clock. Is set to A D flip-flop (hereinafter, referred to as D-FF) 21 for delaying the input EFM signal for 1T period in synchronization with EFMCK in the preceding stage of the delay circuit 10 and the output signals EFMD1 and EFM of the D-FF 21 An OR gate 22 to be input, a selection circuit 23 that inputs an output of the OR gate 22 to a B terminal, inputs a signal EFMD1 to an A terminal, and selects one of the input signals A and B according to the selection signal SW; The output of the selection circuit 23 is synchronized with EFMCK, and the output signal
The FF 24 is connected.

In this embodiment, the rising and falling of the input EFM signal can be delayed by different amounts. When the rising delay Tdf is larger than the falling delay Tdb, the final output is reduced. Pulse width PD
When the rising delay amount Tdf is smaller than the falling delay amount Tdb, the final output pulse width PD becomes longer. Therefore, a signal indicating whether the pulse width is to be reduced or expanded is set as a selection signal SW, and this signal SW
Indicates that the signal EFMD1 input to the A terminal is selected by the selection circuit 23, and the OR gate output input to the B terminal is selected when the signal indicates expansion.

The operation for expanding the pulse width will be described below with reference to FIG. 6 and the operation for shortening the pulse width will be described with reference to FIG. First, in FIG. 6, as shown in FIG. 6B, assuming that a 6T EFM signal corresponding to six periods of EFMCK (FIG. 6A) is input to the D-FF 21,
By 21 the EFM signal is delayed by 1T as shown in FIG. 6c. In the OR gate 22, the logical sum of the delayed signal EFMD1 and the input EFM signal is obtained, so that the output is shown in FIG.
As shown in (1), the input EFM signal is a signal whose pulse width is extended by 1T period. Therefore, when “0” indicating expansion of the pulse width is input as the selection signal SW, the selection circuit 23 selects the output signal expanded by 1T from the OR gate 22. Then, this signal is output to the next stage D-FF 24 at EF.
The signal EFMD2 (FIG. 6e) is synchronized with MCK and input to the delay circuit 10. In the delay circuit 10, each delay element sequentially delays the input EFMD2 signal by T / 16.

Here, if the difference (absolute value) between the rising delay amount Tdf and the falling delay amount Tdb is Tdd, and the amount obtained by subtracting this Tdd from 1T is Td, the select signal SEL1 to the selector 11 becomes , This delay amount Td
Is input. A signal designating the number of delay stages n corresponding to. Therefore, the selector 11 outputs the delay signal EFMD3 (FIG. 6f) whose rising is delayed by Td and sends it to the AND gate 12. Since the input signal EFMD2 is directly applied to the other input terminal of the AND gate 12, the output signal of the AND gate 12 is a signal having a pulse width shorter than the signal EFMD2 by Td as shown in FIG. Becomes This EF
The pulse width of the MD2 signal is 1 more than the pulse width of the input EFM signal.
Since the signal is expanded by T, the output signal of the AND gate 12 eventually has a desired pulse width PD expanded by Tdd from the EFM signal.

Next, the output of the AND gate becomes an input signal of the delay circuit 30 in the next stage. In the delay circuit 30, similarly to the delay circuit 10, the output signal of the AND gate 12 is sequentially delayed by T / 16 by each delay element, and the delay signal of the number n of stages specified by SEL2 is selected by the selector 31. As SEL2, a signal designating the number of delay stages n corresponding to the falling delay amount Tdb, that is, the addition amount of the difference Tdd and the rising delay amount Tdf, is input.
As shown in FIG. 6H, the pulse width PD of the ND gate output does not change, and only the phase is shifted by the added amount (Tdd + Tdf). As a result, as the final output signal WDAT,
From the rising timing t1 of the EFMCK, a desired pulse having a pulse width PD whose rising is delayed by Tdf and whose falling is delayed by Tdb is obtained.

The number of stages n specified by SEL1 is "10".
Then, the pulse width PD is, from the EFM signal pulse width 6T,
(16-10) T / 16 = 6T / 16 The pulse width is expanded, and if the number of stages n specified by SEL2 is "10", the rising delay amount Tdf is Tdf = (10-
6) T / 16 = 4T / 16 is set. Then, the fall delay amount Tdb is Tdb = 10T / 16, which is the number of stages specified by SEL2.

On the other hand, when shortening the pulse width, "1" is input as the selection signal SW, so that the selection circuit 23 has the same pulse width as the input EFM signal and is delayed by 1T as shown in FIG. 7c. The signal EFMD1 is selected. This signal is further delayed by 1T in the D-FF 24 and the signal EFMD shown in FIG.
It becomes 2 and is input to the delay circuit 10. In this case, SEL1
For example, a signal designating the number of delay stages n corresponding to the difference Tdd between the rising delay amount Tdf and the falling delay amount Tdb is input. Therefore, the selector 11 outputs the delay signal EFMD3 (FIG. 7e) whose rising edge is delayed by Tdd and sends it to the AND gate 12. AND gate 12
Since the input signal EFMD2 is applied as it is to the other input terminal, the output signal of the AND gate 12 is a signal whose pulse width is shorter than the signal EFMD2 by Tdd, as shown in FIG. 6F. That is, the output signal of the AND gate 12 has a desired pulse width PD shorter than the EFM signal by Tdd.

Next, the output of the AND gate becomes an input signal of the delay circuit 30 in the next stage. In the delay circuit 30, similarly to the delay circuit 10, the output signal of the AND gate 12 is sequentially delayed by T / 16 by each delay element, and the delay signal of the number n of stages specified by SEL2 is selected by the selector 31. As SEL2, a signal designating the number of delay stages n corresponding to the fall delay amount Tdb, that is, the sum of the difference Tdd and the rise delay amount Tdf is input.
As shown in FIG. 7g, the pulse width PD of the ND gate output does not change, and only the phase is shifted by Tdb. As a result, as the final output signal WDAT, the rising edge becomes Tdf = (Tdd) from the rising timing t1 of EFMCK.
+ Tdb) A desired pulse having a pulse width PD which is delayed and whose fall is delayed by Tdb is obtained.

If the number n of stages specified by SEL1 is "8", the pulse width PD is set to 8 from the EFM signal pulse width 6T.
If the pulse width is shortened by T / 16 and the number n of stages specified by SEL2 is “4”, the rising delay amount Tdf
Is set to Tdf = (8 + 4) .T / 16 = 12T / 16. Then, the fall delay amount Tdb is Tdb = 4T / 16, which is the number of stages specified by SEL2.

As described above, the rising and falling delay amounts Tdf and Tdb can be set by the select signals SEL1 and SEL2. It should be noted that the same output as in FIG. 1 can be obtained by inputting the EFMD2 signal to the delay circuit 30, inputting the delay signal of the selector 31 to the delay circuit 10, and setting the output of the AND gate 12 as the final output signal WDAT. be able to. Further, a comparator may be used as the delay element 40 instead of the inverter.

Next, the pulse width control circuit described above is referred to as C
FIG. 8 shows an example in which the present invention is applied to a disk recording control circuit for DR.
This will be described with reference to FIG. FIG. 8 is a block diagram showing the configuration of the entire disc recording device for CD-R,
Data to be written to 0 is first sent to the EFM encoder 51.
And is supplied to the pulse width control circuit 52 shown in FIG. 1 together with EFMCK. The disk recording control circuit 54 includes the pulse width control circuit 52, the register 53, and the arithmetic circuit 500. The output signal of the pulse width control circuit 52 is supplied to a laser device 55 such as a laser pickup, and the disk corresponds to the EFM signal. A recording mark is recorded. In addition, information indicating the type of media and the rotation speed of the disk to be used is input to the microcomputer 56 for controlling the entire disk recording device.
9, a rising delay amount Tdf and a falling delay amount Tdb are stored in advance in the table 57 connected to the medium 6, as shown in FIG. Note that the stored delay amount is stored as a numerical value indicating how many times the unit delay amount T / 16.

When the medium type and the rotation speed are designated, the microcomputer reads the corresponding rising and falling delay amounts Tdf and Tdb from the table, and sets these values in the register 53. The arithmetic circuit 500 calculates the difference (Tdf-Tdb) for the delay amounts Tdf and Tdb set in the register 53, and obtains Tdf <Tdf.
db, that is, when the pulse width is extended as shown in FIG. 6, "0" is output as the selection signal SW, and the difference Td
delay stage number n corresponding to delay amount Td obtained by subtracting d from 1T
Select signal SEL1 for specifying the pulse width control circuit 52
Output to On the other hand, when Tdf> Tdb, that is, when the pulse width is reduced as shown in FIG. 7, “1” is output as the selection signal SW, and the delay stage number n corresponding to the difference Tdd is output.
Select signal SEL1 for specifying the pulse width control circuit 52
Output to In each case, the number of delay stages n corresponding to the falling delay amount Tdb is used as the select signal SEL2.
Is output to the pulse width control circuit 52.

Accordingly, in the pulse width control circuit 52, the pulse width of the EFM signal input as described above is controlled to a desired pulse width by being delayed by the delay amount specified by SEL1, and specified by SEL2. The signal whose pulse width is controlled can be controlled to a desired phase by delaying by the amount of delay that has been performed. Then, since this output signal WDAT is sent to the laser device 55, in the laser device 55, the recording timing of the EFM signal is adjusted according to the type and rotation speed of the medium, and an appropriate recording mark is recorded.

Incidentally, the delay circuits 10, 3 shown in FIG.
In the delay element 40 constituting 0, since the characteristics of the transistors constituting the delay element are not uniform due to manufacturing variations, the delay amount varies. Therefore, when it is desired to set the delay amount with high accuracy, the delay circuits 10 and 30
The delay circuit 1 shown in FIG. 2 may be used. FIG. 2 shows a delay circuit 1 including a delay line 2 for delaying an input signal.
And P for controlling the delay amount of the delay line 2
The LL circuit 3 is provided. The PLL circuit 3 includes a VCO 4 whose output signal frequency changes according to the input control voltage Vt;
A programmable divider 5 for dividing the output signal of the VCO 4 by 1 / N, a reference divider 6 for dividing the input reference signal RFCK by 1 / M, and a phase for comparing the phases of the output signals of both dividers 5 and 6 Comparator 7 and phase comparator 7
Control voltage Vt corresponding to the phase difference detected by the VCO
3 and a low-pass filter 8 for supplying the power to the divider 3. Both dividers 5 and 6 are dividers whose division ratios can be changed.
The output stage of the phase comparator 7 is provided with a charge pump.

As shown in FIG. 2, the VCO 4 in the PLL circuit 3 has a ring-shaped configuration in which a plurality of delay cells 40 are connected in series, and the output of the last delay cell 41 is negatively fed back to the first stage. Thus, the output of the last stage is sent to the programmable divider 5 via the buffer 45. Each of the delay cells has first and second control terminals. The first control terminal is supplied with a constant bias Vb from the bias circuit 46, and the second control terminal is supplied with the control voltage Vt from the low-pass filter 8. Is supplied.

On the other hand, the delay line 2 is configured by connecting a plurality of delay cells 40 having the same configuration as the delay cells constituting the VCO 4 in series. Is applied. Then, one of the outputs from the delay cells in each stage is selected by the selector 20, and is taken out as a delay signal SOUT. This selector 20 corresponds to the selector 1 in FIG.
1 and 31 are selectors. The circuit shown in FIG. 2 is configured in the vicinity of the same chip, so that the delay characteristics of the delay cell are almost the same between the VCO 4 and the delay line.

Here, a specific configuration of the delay cell 40 will be described with reference to FIG. The delay cell 40 basically includes a P-channel MOS transistor and an N-channel M
Inverter 10 cascaded with OS transistors
1 and 102 are connected in series in two stages, and buffers 103 and 10 are provided behind each of the inverters 101 and 102.
4 are connected. In addition, inverters 101 and 102
P-channel MOS for current control between the power supply potential
The transistors 105 and 106 are connected, and the inverter 1
N-channel MOS transistors 107 and 108 for controlling current are connected between the ground potentials 01 and 102. The gate of the P-channel MOS transistor 105 for current control is connected to the first control terminal 110,
The gate of the current control N-channel MOS transistor 107 is connected to the second control terminal 111. still,
Reference numeral 109 denotes a parasitic capacitance.

In this embodiment, a constant bias V from the bias circuit 46 is applied to the first control terminal 110.
b, and the control voltage Vt from the low-pass filter 8 is supplied to the second control terminal 111. Therefore, when the control voltage Vt increases, the current flowing through the inverters 101 and 102 increases, and the delay dt of the input signal IN decreases. When the control voltage Vt decreases, the inverters 101 and 1 decrease.
02 decreases, and the delay dt of the input signal IN increases. Thus, the delay amount dt of the delay cell 40 changes according to the magnitude of the control voltage Vt.

The final stage of the VCO 4 applies only negative feedback to the first half of the delay cell 40, that is, the inverter 101, the buffer 103, and the control transistor 10 in order to apply negative feedback.
The output of the inverter 101 is input to the delay cell 40 at the first stage of the VCO 4. Hereinafter, the operation of the embodiment shown in FIG. 2 will be described.

First, the output signal frequency f1 of the VCO 4 is divided by the programmable divider 5 into 1 / N and f1
/ N, and the reference signal frequency f0 is divided by the reference divider 6 to f0 / M. The phase of these frequency-divided signals is compared by a phase comparator 7, and a control voltage Vt corresponding to the phase difference is supplied from a low-pass filter 8 to the VCO 4. As a result, the PLL circuit 3 operates so as to eliminate the phase difference between the output signals of the two dividers, and when the PLL is locked, Expression (1) holds.

[0031]

(Equation 1)

On the other hand, in the VCO 4, the delay amount dt of each delay cell is determined by the control voltage Vt from the low-pass filter 8 as described above, and the signal dt0 input to the first-stage delay cell 40 is as shown in FIG. Are sequentially delayed by dt in each delay cell 40. The signal is inverted in the final stage delay cell 41, and the inverted signal is fed back to the first stage after the return delay dα. That is, the return delay d
Assuming that α is sufficiently smaller than dt, the half cycle T / 2 of the cycle T of the VCO 4 has a length obtained by adding the delay amount dt by the number of stages D of the delay cells 40. Therefore, the delay amount dt is represented by the equation (2).

[0033]

(Equation 2)

Here, the period T is 1 / f1, and when the PLL circuit 3 locks as described above, the equation (1) holds. Therefore, in the locked state, the delay amount dt is expressed by the equation (3). You.

[0035]

(Equation 3)

That is, if the number of delay cell stages D of the VCO and the division ratios M and N are determined, the delay amount dt of the delay cell 40 becomes a constant value that depends only on the frequency f0 of the reference signal RFCK.
By the way, in the circuit shown in FIG. 2, as described above, the delay cells constituting the delay line 2 have exactly the same configuration as the delay cells of the VCO 4, and the control voltage supplied to the delay cells in the delay line 2 is also VCO 4 Delay cell 40
Is exactly the same as the control voltage Vt supplied to Therefore, the delay amount of the delay cell in the delay line 2 is VCO
4 is exactly the same as the delay amount dt of the delay cell 40, and PL
When L is locked, it has a constant value depending on the reference signal frequency f0.

The delay line 2 has a configuration in which the input signal SIN is sequentially delayed by the delay cell 40, a delay output of a desired stage is selected by the selector 20, and is output as the delay signal SOUT. Is constant when the PLL is locked, so that the delay amount of the delay signal output from the selector 20 in the delay line 2 also has a desired constant value. In other words, the delay line 2 does not require adjustment at the time of manufacture, and can set the delay amount with the accuracy guaranteed by the PLL circuit 3, so that it is possible to set a high accuracy in the order of psec. Moreover, since the PLL is guaranteed against power supply fluctuations and temperature fluctuations, the delay amount of the delay line 2 is not affected by these fluctuations.

Further, the delay amount dt can be easily changed only by changing the frequency f0 of the reference signal RFCK and the frequency division ratios M and N, so that the resolution of the delay line 2 can be easily set. For example, when the number of stages D of the VCO 4 is “16 stages”, the frequency division ratios M and N are each “2”, and f0 is “17.2”.
8 MHz ”, the delay amount dt is“ 1.
81 nsec. " Then, the dividing ratios M and N are each set to “4”.
If you change f0 to "34.56 MHz",
From Expression (3), the delay amount dt is “0.90 nsec”, which is a resolution on the order of psec.

Further, as shown in the VCO characteristics of FIG.
The frequency range in which the LL locks is wide, and the delay amount dt of the delay cell can be changed within this range.
Can be widened. In the embodiment described above, an example is described in which the delay element in the delay cell is configured by an inverter. However, a configuration in which a comparator is used instead of the inverter may be used. A constant bias is applied to one of the current control transistors 105 and 106 in the delay cell, and the other current control transistor 107 and
Although the control voltage Vt from the low-pass filter 8 is supplied to only 108, the control voltage Vt may be supplied to both current control transistors.

[0040]

According to the present invention, a desired pulse waveform can be obtained without using a high-speed clock.
In particular, when a PLL circuit is used, the delay amount can be set with high accuracy. Further, if the present invention is applied to a disk recording device, it becomes possible to realize appropriate recording corresponding to the media type and the rotation speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pulse width control circuit according to the present invention.

FIG. 2 is a block diagram illustrating another embodiment of a delay circuit.

FIG. 3 is a circuit diagram showing a specific configuration of a delay cell in the embodiment.

FIG. 4 is a timing chart for explaining the operation of the VCO in the embodiment.

FIG. 5 is a characteristic diagram showing a VCO characteristic and a delay characteristic in the embodiment.

FIG. 6 is a timing chart for explaining an operation when a pulse width is extended in the embodiment shown in FIG. 1;

FIG. 7 is a timing chart for explaining an operation when the pulse width is reduced in the embodiment shown in FIG. 1;

FIG. 8 is a block diagram showing an embodiment of a disk recording control circuit according to the present invention.

FIG. 9 is an explanatory diagram showing storage contents of a table in the embodiment.

[Explanation of symbols]

1, 10, 30 delay circuit 2 delay line 3 PLL circuit 4 VCO 5 programmable divider 6 reference divider 7 phase comparator 8 low-pass filter 12 AND gate 20, 11, 31 selector 21, 24 D-FF 22, 32 OR gate 23 selection Circuit 40 Delay cell 50 Disk 51 EFM encoder 52 Pulse width control circuit 54 Disk recording control circuit 55 Laser device 101, 102 Inverter 105, 106, 107, 108 Current control transistor 110 First control terminal 111 Second control terminal 500 Arithmetic circuit

Claims (4)

[Claims] 1. A logic circuit for delaying an input signal for a predetermined period according to a reference clock, a logic operation output signal of an output signal of the logic circuit and the input signal being input to one end, and the input signal being input to the other end. A selection circuit for selecting one of them in accordance with information indicating reduction / expansion of a pulse width, a first and a second delay circuit for connecting a plurality of delay elements to delay an input signal, First and second selectors for selecting one of the output signals of each delay element stage for each of the two delay circuits and outputting the selected signal as a delay signal; input signals of the first delay circuit and delays of the first selector A logic circuit for performing a logical operation with a signal, a signal selected by the selection circuit being an input signal of the first delay circuit, and an output signal of the logic circuit being an input signal of a second delay circuit. Or the selection A pulse width control circuit, wherein a signal selected by the selection circuit is used as an input signal of the second delay circuit, and a delay signal from the second selector is used as an input signal of the first delay circuit. 2. A first select signal corresponding to a difference between a rising delay amount and a falling delay amount of a final output signal or a delay amount obtained by subtracting the difference from the predetermined period is supplied to the first selector. 2. The pulse width control circuit according to claim 1, wherein a second select signal corresponding to the fall delay amount is supplied to the second selector. 3. A delay circuit comprising a plurality of delay elements connected in a ring shape in a plurality of stages, a VCO controlled by a control voltage to which a delay amount of each stage is input, and an output signal of the VCO or a corresponding output signal. A phase comparator that receives the frequency signal and the reference signal and compares the phases of the two signals; a low-pass filter that generates the control voltage according to the phase difference detected by the phase comparator; a delay element of the VCO; 2. A delay line comprising a plurality of delay elements having the same configuration connected to each other, the delay line outputting an input signal delayed and controlling the delay amount of each stage by the control voltage. The described pulse width control circuit. 4. A pulse width control circuit according to claim 1, wherein a modulation signal to be recorded is supplied as an input signal, and a select signal corresponding to the type and / or rotation speed of the medium is supplied. An output signal that is input to the first and second selectors and is sent to a recording device that records a recording mark corresponding to the modulation signal on a disk, so that the recording timing of the recording mark can be adjusted. Disk recording control circuit.