JP2001313551A - Pulse width control circuit and recording compensation circuit for optical disk using the pulse width control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the duty of an output pulse to a desired value independently of a clock waveform of a synchronous circuit such as a shift register. SOLUTION: A clock frequency divider circuit (DIV) 110 outputs a signal MPR resulting from applying 1/2 frequency division to a clock signal CLK to a programmable delay line (DL-MTX) 140. A counter circuit (CNT) 120 counts a reference delay stage number DREF equivalent to one period of the clock, a duty adjustment circuit (DUTY-ADJ) 130 calculates a delay setting stage number DREFH on the basis of the reference delay stage number DREF and outputs it to the programmable delay line (DL-MTX) 140. The programmable delay line (DL-MTX) 140 generates a delay signal DMPR resulting from delaying the clock frequency division signal MPR on the basis of the delay setting stage number DREFH and generates a delay signal ZMRP resulting from delaying the clock frequency division signal MPR0 stage. A pulse train generating circuit (MP-GEN) 150 calculates an exclusive OR between the delay signals DMPR and ZMPR and provides an output of a pulse train MP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse width control circuit and a recording compensation circuit for an optical disk using the pulse width control circuit, and more particularly to a pulse width control circuit for generating a pulse train having a desired duty ratio and this pulse width control circuit. The present invention relates to a recording compensation circuit for an optical disk using the same.

[0002]

2. Description of the Related Art High-density optical recording devices are roughly classified into a magneto-optical disk system and a phase change disk system.
In particular, recently, a magnetic head is unnecessary, the size of an optical head is easily reduced, direct overwrite can be easily realized, the signal strength is high, and the S / N of a reproducing system is advantageous. The changing disk system is attracting attention, and development is being emphasized. FIG. 15 is a configuration diagram of an example of a high-density optical recording device. The disk 400 is, for example, a phase change disk and is driven to rotate by a spindle motor 310. The spindle motor 310 drives the disk 400 to rotate at a constant rotation speed (number of rotations) by the servo 320. At the time of data reproduction, a laser diode controller (hereinafter, LDC) is supplied according to a pulse supplied from a pulse generation circuit (hereinafter, WP) 340.
) 350 is driven, and the optical head 360 irradiates the disc 400 with laser light of a reproduction level. This reflected light is received by the optical head 360, photoelectrically converted and RF
(Radio Frequency) signal is supplied to a reproduction circuit (hereinafter referred to as RP) 370. Demodulated data demodulated by the RP 370 is sent to the system controller, and a reproduction process is performed.

On the other hand, when recording data, the data sent from the system controller is modulated by the data modulator 330, converted into a write pulse signal corresponding to the modulated data by the WP 340, and supplied to the LDC 350.
The LDC 350 is driven, and a laser beam for recording is emitted from the optical head 360. FIG. 16 shows an output signal of WP and a laser pulse emission waveform of LDC. W
P340 generates write laser control signals P2 and P3 according to the read laser control signal P1 and the input modulated input data D1. LDC3 at the time of recording
The 50 laser pulse emission waveform P4 has a form in which a pulse is superimposed on a DC bias signal.

In a high-density optical recording apparatus, it is necessary to record a minute mark row at an accurate position. In particular, since a phase change disk is a pure thermal recording, the management of heat during recording is the most important. In order to accurately manage the heat, a continuous pulse train is used as a laser beam used for forming a mark. In addition, this pulse train is not simply a pulse synchronized with the clock, but what is called recording compensation for setting the position and width optimally is essential.

An example of such a phase change disk recording compensation method will be described. FIG. 17 shows an operation waveform of an example of the phase change disk recording compensation circuit. When a pulse width of one clock is T and n * T (n is an integer) mark is recorded, M is a mark corresponding to 1 (H level), and S is 0.
(L level), and the amount of delay is x, y
Then, the recording pulse is

[0006]

XS + (1.5−x) M + (n−2) (0.5S + 0.5M) + yM + (0.5−y) S (1) or

[0007]

XS + (1.5−x) M + (n−3) (0.5S + 0.5M) + 0.5S + yM + (1.0−y) S (2)

As a method of generating a pulse train as shown in equations (1) and (2), for example, a recording pulse generating circuit using a multi-stage shift register has been proposed. FIG. 18 is a timing chart of a recording pulse generation circuit using a multi-stage shift register. Using a multi-stage shift register, DAT delayed by one clock cycle (hereinafter referred to as T) with respect to CDATA0 in which input data is latched by clock CLK.
A0, DATA1, DA delayed by 0.5T each
Generate TA2, DATA3, and DATA4 and DATA5 (not shown). Using a logic circuit, TOP = DA
TA2 * 〜DATA5 (〜DATA5 indicates an inverter of DATA5. Hereinafter, 〜 indicates an inverter). Also, END = ~ DATA0 * DAT
A3, MP = TOP + END + CLK. GATE
= DATA1 + DATA2, REC = GATE * MP, thereby obtaining a recording pulse REC when x = 0 and y = 0 in the equation (1). Here, DDAT which is DATA2 delayed by xT using two delay amount variable elements is used.
A2, DATE1 which is DATA1 delayed by yT, AGATE = DDATA2 * DDATA1, REC =
By setting GATE * MP, any x and y can be calculated by the equation (1).
The recording pulse GREC whose rising and falling are controlled, which is expressed by the following expression, is obtained. Therefore, if there is a normal logic circuit and a variable delay element, the above-described recording compensation circuit can be realized.

As such a recording compensation circuit, a delay element composed of two stages of inverters, a delay lock loop for counting and outputting how many stages of the clock 1T the delay element corresponds to, and a relative delay with respect to the output 1T A recording compensation circuit using a variable delay circuit composed of a multiplier for multiplying an amount has been proposed. In this circuit, the values of the delay amounts x and y in Equations (1) and (2) can be set from the outside, and the delay amounts are stable against disturbances such as temperature fluctuations and individual differences such as process variations. . In addition, general CMOS (Complementary Metal Oxide Semiconduc
tor) process.

In response to the recent trend toward higher densities and higher transfer rates of phase change disk systems, not only the above-described equations (1) and (2) but also more complex ones have been used. ing. In addition, the laser power often uses three or more values. In particular, since the control of the pulse width is an important parameter that greatly affects the recording characteristics, for example, (0.5S + 0.5
The duty ratio of the multi-pulse portion expressed by M) is also controlled. If the multi-pulse portion can be stably supplied with the same pulse width, the recording / reproducing characteristics are improved.

[0011]

However, the variable delay circuit used in the conventional recording compensation circuit has a problem that it is difficult to stably generate multi-pulses of the same width. Therefore, there is a problem that a stable recording compensation circuit for a phase change disk cannot be formed.

In the circuit described above, in generating the multi-pulse portion of the equations (1) and (2), the CLK signal is converted to a logical 1
We use as one. That is, since the rising and falling edges of CLK are the reference positions for the rising and falling edges of the multi-pulse, respectively, when the input clock duty fluctuates due to the above-described disturbance, individual difference, etc., FIG. As described above, it is impossible to always generate pulses having the same width. In particular, when it is necessary to control the duty ratio of the multi-pulse, the stability of this portion greatly affects the recording characteristics of the system.

As means for avoiding this phenomenon, for example,
A method has been proposed in which the rising edges of the clock CLK and the DCLK obtained by delaying the CLK by 0.5T using a delay lock loop are used as reference positions for the rising and falling edges of the new clock ACLK. I have.

However, the clock AC generated in this manner is
Using LK for only some of the synchronous logic circuits causes clock skew with other synchronous logic circuit parts using the clock CLK before adjustment, which is likely to cause inconvenience in circuit design. In addition, a clock signal in an IC is usually driven by a cell having a high driving capability, and special processing such as optimization of a wiring length is often performed. For this reason, replacing some or all of the clocks with ACLK generated by a logic circuit in the IC leads to insertion of an extra gate or the like in the clock net, which may cause a problem in reliability of the entire IC. is there.

The present invention has been made in view of such a point, and a pulse capable of controlling a duty of an output pulse to a desired value without depending on a clock waveform of a synchronous circuit portion such as a shift register. An object of the present invention is to provide a width control circuit and a recording compensation circuit for an optical disk using the pulse width control circuit.

[0016]

According to the present invention, in order to solve the above-mentioned problems, in a pulse width control circuit for generating a pulse train having a desired duty ratio, a clock signal synchronized with an output pulse is input, and the clock signal is output. A clock frequency divider circuit for generating a clock frequency-divided signal divided by 2, a count circuit for counting the number of reference delay stages corresponding to one cycle of the clock signal and outputting the count value, and inputting and setting the count value in advance A duty adjustment circuit for calculating the number of delay setting stages in accordance with the predetermined duty ratio, and a programmable circuit for delaying the clock division signal by the number of delay stages and outputting the clock division signal and delaying the clock division signal by 0 stages for output .The delay line and the programmable delay line delay the set number of delays Pulse width control circuit, comprising a pulse train generating circuit for generating a pulse train having a predetermined duty ratio from the output signal and the 0-stage delayed output signal, is provided.

In the pulse width control circuit having such a configuration,
The clock divider circuit generates a clock divided signal obtained by dividing the clock signal by two, and the count circuit counts the number of reference delay stages corresponding to one cycle of the clock. The duty adjustment circuit calculates the number of delay setting stages according to a delay ratio determined by a preset clock duty ratio. The programmable delay line
The clock division signal is delayed and output according to the number of delay setting stages calculated by the duty adjustment circuit, and the clock division signal is delayed by 0 stages and output. The pulse train generation circuit generates a pulse train having a predetermined duty ratio from the output signal delayed by the number of delay setting stages output from the programmable delay line and the output signal delayed by 0 stages.

According to another aspect of the present invention, there is provided a recording compensation circuit for an optical disk for recording data in accordance with a recording pulse obtained by synthesizing a starting pulse, a multi-pulse, and an ending pulse. A clock divider circuit that generates a clock divided signal obtained by dividing the clock signal by 2, a count circuit that counts the number of reference delay stages corresponding to one cycle of the clock signal, and outputs the count value; A duty adjustment circuit that inputs the count value and calculates the number of delay setting stages in accordance with a predetermined duty ratio set in advance; and outputs the clock divided signal with the delay set stage number delayed and outputs the clock divided signal. A programmable delay line for delaying the output by 0 stages, A pulse train control circuit including a pulse train control circuit for generating a pulse train having a predetermined duty ratio from the output signal delayed by the delay setting number of stages and the output signal delayed by the zero stage by a ray line, as a multi-pulse generator An optical disc recording compensation circuit is provided.

In the optical disk recording compensating circuit having such a configuration, the clock frequency dividing circuit of the pulse width control circuit, which is a multi-pulse generator, generates a clock divided signal by dividing the clock signal by two. Also, the counting circuit
The number of reference delay stages corresponding to one cycle of the clock is counted. The duty adjustment circuit calculates the number of delay setting stages according to a delay ratio determined by a preset clock duty ratio. The programmable delay line delays and outputs the clock divided signal according to the number of delay setting stages calculated by the duty adjustment circuit, and outputs the clock divided signal with a delay of 0 stages. The pulse train generation circuit generates a multi-pulse having a predetermined duty ratio from the output signal delayed by the number of delay setting stages output from the programmable delay line and the output signal delayed by zero stages. The generated multi-pulse is used as a recording pulse for an optical disk together with a start pulse and an end pulse obtained by adding a predetermined delay amount to the multi-pulse.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a pulse width control circuit according to an embodiment of the present invention.

A pulse width control circuit according to the present invention receives a clock signal CLK, generates a clock frequency dividing signal MPR, a clock frequency dividing circuit (DIV) 110, and a count circuit (CNT) 1 for counting the number of reference delay stages DREF.
20, the number of delay setting stages D according to a predetermined duty ratio
Duty adjustment circuit (DUTY_A for calculating REFH)
DJ) 130, delayed signal DMPR obtained by delaying clock divided signal MPR by the number of delay setting stages, and clock divided signal MP
It comprises a programmable delay line (DL_MTX) 140 for generating a delay signal ZMPR obtained by delaying R by 0 stages, and a pulse train generation circuit (MP_GEN) 150 for generating a pulse train MP from the delay signals DMPR and ZMPR.

The clock divider circuit (DIV) 110 receives the clock signal CLK, generates a clock divided signal MPR obtained by dividing the clock signal CLK by two, and outputs it to the programmable delay line (DL_MTX) 140. The clock frequency dividing circuit (DIV) 110 can be composed of, for example, a D-flip-flop circuit. FIG. 2 is a block diagram of a D-flip-flop circuit which is an example of a clock frequency dividing circuit. D-flip-flop circuit (hereinafter, D-FF)
110a) receives the clock signal CLK, inverts the signal at the rising and falling edges, and outputs the inverted signal. That is, assuming that the period of the clock signal CLK is T, a pulse signal MPR having a period 2T obtained by dividing the frequency by 2 is output. The clock frequency dividing circuit (DIV) 110 can be constituted by a differentiating circuit or the like.

Returning to FIG. Count circuit (C
NT) 120 counts the number of reference delay stages DREF corresponding to one cycle of the clock, and outputs this to duty adjustment circuit (DUTY_ADJ) 130. The clock cycle changes under the influence of temperature, power supply voltage and the like. The reference delay stage number DREF according to the fluctuation of the clock cycle
Is, for example, a delay lock loop.

The delay lock loop counts down or counts up according to the length of clock repetition to calculate the number of delay stages, and calculates the current number of delay stages and the number of delay stages one clock before obtained by shifting the number of delay stages. This is a circuit for comparing and outputting the smaller one as the reference delay stage number. Here, a delay lock detection circuit that calculates the number of delay stages will be described. FIG. 3 is a block diagram of a delay lock detection circuit constituting the count circuit. A delay lock detection circuit according to the present invention includes a shift register 121 including two stages of D-FFs 121a and 121b, a first comparator 122, and a second comparator 1.
23, an AND gate 124, a D-FF 125, a selector 126, and a D-FF 127. The number of delay stages DUPD to be counted is determined by the shift register 121.
Supplied to In the shift register 121, with respect to the current number of delay stages DUPD, the number of delay stages DR1, D-FF12
As the output of 1b, the number of delay stages DR2 two clocks before is obtained. Note that the clock supplied to the shift register 121 is a data pulse TP4. In the comparator 122,
A comparison is made between the current delay stage number DUPD and the delay stage number DR1 one clock before, for example, DUPD> DR1
In the case of, data output is performed. Further, the comparator 123
Compares the current delay stage number DUPD with the delay stage number DR2 two clocks before, for example, DUPD = D
If R2, data output is performed. That is, AN
From the D gate 124, DUPD> DR1 and DUPD =
The logical product in the case of DR2 is output. D-FF125
Latches the number of delay stages in the case of DUPD = DR2 with a data pulse TP4 and outputs a delay lock signal LOC
High level data is output as K. Selector 12
6 receives the number of delay stages DR1 one clock before and the current number of delay stages DUPD, and selectively outputs the inputted number of delay stages DUPD and DR1 based on the logical product from the AND gate 124. For example, the number of delay stages D
UPD and DR2 match and the number of delay stages DUPD
Is larger than DR1, the number of delay stages DR1 is output. Otherwise, the number of delay stages DUPD is output. The number of delay stages selected by the selector 126 (DUP
D or DR1) is supplied to the D-FF 127, is latched by the data pulse TP4, and is always output as the reference delay stage number DREF. Thus, the number of delay stages DR2 two clocks before and the current number of delay stages D
The UPD is compared, and if they match, a delay lock signal LOCK is output, and the number of delay stages DR1 one clock before is output.
Is compared with the current delay stage number DUPD, and the smaller one is output as the reference delay stage number DREF.

By forming the count circuit (CNT) 120 in such a delay locked loop configuration, the reference delay stage number DRE is changed in accordance with a change in the cycle of the clock CLK.
Since F changes, a desired delay amount can be calculated according to the period change amount of the clock CLK.

Returning to FIG. The duty adjustment circuit 130 receives the reference delay stage number DREF output from the count circuit 120, calculates the delay setting stage number DREFH corresponding to a predetermined duty ratio set in advance, and outputs it to the programmable delay line 140. For example, when a clock having a 50% duty is generated, the delay setting stage number DREFH is １ ／ of the reference delay stage number DREF corresponding to one cycle of the clock.
Should be taken as the value of. Such a duty adjustment circuit 13
0 can be constituted by, for example, a bit shift circuit or a multiplication circuit.

The case where the duty adjustment circuit 130 is constituted by a bit shift circuit will be described. FIG. 4 is a block diagram of a bit shift circuit which is an example of the duty adjustment circuit. The input reference delay stage number DREF is 6 bits (DREF [0] to [5]), the delay setting stage number DREFH is １ ／ of the reference delay stage number DREF,
That is, the duty is set to 50%. The bit shift circuit 130a inputs each bit of the reference delay stage number DREF, shifts it one bit at a time, and
Output as [5: 0]. Bit shift circuit 130a
Can be expressed as the following equation.

[0028]

DREFH [5: 0] = {1′b0, DREF [5: 1]} (3) As described above, the delay setting stage number DR is extremely simple circuit.
EFH can be obtained. Here, it is assumed that 段 of the reference delay stage number DREF is calculated.
Other ratios can also be used.

Next, a case where the duty adjustment circuit 130 is constituted by a multiplication circuit will be described. FIG. 5 is a block diagram of a multiplication circuit which is an example of the duty adjustment circuit.
This is a multiplier <MPL> used in a general IC. The multiplying circuit 130b includes a reference delay stage number DREF
And using the preset multiplication value DUTY

[0030]

DREFH = DREF × DUTY (4) Assuming that DUTY = １ ／, the number of delay setting stages DREFH is one of the reference delay stage number DREF.
/ 2, that is, 50% duty is obtained.
DUTY can be set arbitrarily.

Returning to FIG. Programmable
The delay line 140 sets the clock division signal MPR having a period of 2T to DLIN and sets the delay setting stage number DREFH to S.
Input to EL. Delay signal DM obtained by delaying input clock divided signal MPR according to delay setting stage number DREF
PR is output from SDLY. Further, a delay signal ZMPR obtained by delaying the clock division signal MPR by 0 stages is output from ZDLY. The programmable delay line 140
It is constituted by a CMOS logic circuit, such as a delay chain and a multiplexer by an NAND element and an inverter and a multiplexer. In general, a programmable delay circuit has a gate delay caused by a multiplexer even when a delay stage of zero is selected. For this reason, the programmable delay line (DL_MTX) 140 according to the present invention
In this example, a signal that is not delayed, that is, a signal that is delayed by 0 stages, is passed through a common multiplexer together with a signal that has been delayed by the number of delay stages to match the phases. For example, if the delay setting stage number DREFH is set to １ ／ of the reference delay stage number DREF, the SDLY output becomes the clock dividing signal M
PR becomes a DMPR obtained by delaying the gate delay amount of the T / 2 + multiplexer, and the ZDLY output becomes the clock signal MPR.
Is a ZMPR obtained by delaying the gate amount of the multiplexer.
For this reason, the difference between DMPR and ZMPR is the delay amount set by the delay setting stage number DREFH.

Programmable delay line 140
Is configured with a delay chain using a NAND element. FIG. 6 is a circuit diagram of a delay chain using a NAND element as an example of a programmable delay line.

This is an eight-stage programmable delay line using two stages of NAND as unit delay elements.
Delay line 141a constituted by AND element
And a multiplexer 142a for selecting a signal having a desired delay amount according to the selection signal SEL.

Next, a case where the programmable delay line (DL_MTX) 140 is composed of an inverter and a multiplexer will be described. FIG. 7 is a circuit diagram of a delay circuit using an inverter and a multiplexer as an example of a programmable delay line. The delay line 141b includes an inverter and a multiplexer 142b that selects a signal having a desired delay amount according to the selection signal SEL. This is one in which the delay line in FIG. 6 is configured by an inverter.

Returning to FIG. 1, the description will be continued. The pulse train generation circuit (MP_GEN) 150 generates a delay signal D generated by the programmable delay line (DL_MTX) 140.
MPR and ZMPR are input and a pulse train having a predetermined duty ratio is generated. The pulse train generates the rising edge of the delayed signal DMPR delayed by the number of delay setting stages and the rising edge of the delayed signal ZMPR delayed by 0 stages as the rising and falling timings of the pulse output signal. The pulse train generation circuit (MP_GEN) 150 can be configured by, for example, a logic circuit. FIG. 8 is a circuit diagram of a logic circuit which is an example of the pulse train generation circuit. Logic gate 150a
Is a delay signal DMPR delayed by the number of delay setting stages,
Exclusive logic with the delay signal ZMPR delayed by 0 stages is calculated, and is set as a pulse train MP. That is, the delay signal ZM
A pulse train MP that rises at the rise and fall of PR and falls at the rise and fall of the delay signal DMPR is generated and output.

The operation of the pulse width control circuit having such a configuration will be described with reference to FIG. Here, a description will be given assuming that a duty ratio of 50% is set.
The clock signal CLK is supplied to a clock frequency dividing circuit (DIV) 1
10, the frequency is divided by 2 and a programmable delay line (DL_MTX) 1 is generated as a clock frequency divided signal MPR.
Output to 40. The count circuit (CNT) 120
Reference delay stage number DREF corresponding to one cycle of clock
And a duty adjustment circuit (DUTY_AD
J) Output to 130. Duty adjustment circuit (DUTY
_ADJ) 130 calculates a delay setting stage number DREFH obtained by halving the reference delay stage number DREF so that the duty ratio becomes 50%,
Output to the delay line (DL_MTX) 140. Programmable delay line (DL_MTX) 140
Generates a delay signal DMPR obtained by delaying the clock divided signal MPR based on the delay setting stage number DREFH, generates a delayed signal ZMPR obtained by delaying the clock divided signal MPR0, and generates a pulse train generation circuit (MP
_GEN) 150. Pulse train generation circuit (MP
_GEN) 150 calculates the exclusive logic of the delay signals DMPR and ZMPR and outputs the result as a pulse train MP.

The operation of the above-described pulse width control circuit will be described with reference to operation waveforms. FIG. 9 is a timing chart of the pulse width control circuit according to one embodiment of the present invention. T1
The duty ratio of the clock signal CLK in the section is 75%, and the duty ratio in the section T2 is 25%. As described above, since the clock signal CLK passes through the clock divider circuit (DIV) 110 and is divided by two, even if the duty ratio of the clock signal CLK changes, the clock signal CLK is not divided into signals after the clock divided signal MPR. Is not propagated. The clock division signal MPR is set to the set delay stage number DRE.
The delay signal DMPR delayed by FH is delayed by the gate delay amount of the T / 2 + multiplexer with respect to the clock divided signal MPR. On the other hand, a delayed signal ZMPR delayed by 0 stages
Is delayed by the amount of the gate of the multiplexer with respect to the clock divided signal MPR. Delay signal DMPR and ZMPR
Are generated from the common clock frequency-divided signal MPR and pass through the common multiplexer, so that the signals are always shifted by the set delay stage number DREF. The pulse train MP uses the delay signals DMPR and ZMPR to generate D
It is generated by setting L when the signal level of both MPR and ZMPR is H or L, and setting it to H otherwise.
As described above, the phase difference between DMPR and ZMPR is T
/ 2, a pulse train with a duty ratio of 50% can be obtained.

In this manner, a pulse train having the same frequency as the clock and a duty of 50% can be realized without the need for an external circuit or the like, without being affected by individual differences such as disturbances such as temperature and power supply voltage and process variations. it can. This pulse train is a net independent of the system clock, and a clock can be supplied to other synchronous circuit portions and the like as in the conventional case. Therefore, it is not necessary to increase the load driving capability of the pulse train, and an improvement in response speed can be expected.
In addition, all circuit blocks including delay elements are CMO
It can be created by the S logic circuit process and can be realized at low cost.

Next, a case where the above-described pulse width control circuit is used for a recording compensation circuit for an optical disk will be described. FIG. 10 is a block diagram of a recording compensation circuit according to an embodiment of the present invention.

The recording compensation circuit according to the present invention comprises multi-stage shift registers 311, 312, 313, 314, 315, 3
16, 317, variable delay amount elements 321 and 322, a recording multi-pulse generator (REC_GEN) 100 which is a pulse width control circuit described above, and logic gates 331 and 3
32, 333, 334, and 335.

The AND gate 331 inputs the multi-stage shift registers 314 and 317, takes a logical product, and outputs an output signal T.
OP = DATA2 * to DATA5 are obtained. Similarly, AN
The D gate 332 outputs the output signal END = 〜DATA0 * D
ATA3 is obtained. The OR gate 334 includes a multi-pulse MP whose duty is controlled to 50% by the multi-pulse generator (REC_GEN) 100, TOP, and E.
ND is input, ORed, and output signal MP2 = TOP
+ END + MP is obtained. As a result, a recording pulse REC when x = 0 and y = 0 in the equation (1) is obtained.

Further, the variable delay amount element 321
DDATA1 obtained by delaying 1 by yT and delay amount variable element 32
2 and DDATA2 obtained by delaying DATA2 by xT with AN
The logical product is obtained by the D gate 333, and the output signal AGATE =
DDATA2 * DDATA1 is obtained. Further, AND gate 335 calculates the logical product of AGATE and MP2, thereby obtaining GREC = AGATE * MP2. As a result, a recording pulse GREC whose rising and falling are controlled, which is represented by arbitrary x and y in the equation (1), is obtained.

The operation of the above-described recording compensation circuit will be described with reference to operation waveforms. FIG. 11 is a timing chart of the recording compensation circuit according to one embodiment of the present invention. The signal names are the same as the output signal names in FIG. System clock CL
K indicates that the clock duty is 75% in the T1 section and the clock duty is 2 in the T2 section.
It has changed to 5%. However, as described above, the pulse train MP output from the multi-pulse generator 100 can stably generate pulses having the same frequency as the clock and an arbitrary duty ratio.

As described above, since the pulse duty can be accurately controlled, when applied to a recording compensation circuit of an optical disk drive or the like, stable recording characteristics and an expanded system margin are expected. In addition, since it is easy to integrate it into an IC having a delay circuit, such as a recording compensation circuit, to form a single chip, a reduction in mounting area, improvement in reliability, and reduction in power consumption can be expected.

In the above description, the duty ratio is set in advance, but the duty ratio can be made variable. FIG. 12 is a block diagram of a pulse width control circuit having a variable duty ratio according to an embodiment of the present invention. FIG.
The same components as those described above are denoted by the same reference numerals, and description thereof is omitted.

The duty adjustment circuit 131 inputs the reference delay stage number DREF corresponding to one cycle of the clock from the count circuit 120, calculates the delay setting stage number DREFR according to the duty ratio RATIO set from the outside, and calculates the programmable delay. Output to line 140. Such a duty adjustment circuit 131 is, for example,
It can be configured by a multiplication circuit. FIG. 13 is a block diagram of a multiplication circuit that makes the duty ratio variable. This is a multiplier <MPL> used in a general IC. The multiplier 131a includes a reference delay stage number DREF,
Enter the desired duty ratio RATIO,

[0047]

DREFR = DREF × RATIO (5) RATIO can be arbitrarily changed from outside.

The operation of the pulse width control circuit having such a configuration will be described with reference to FIG. Clock signal CL
K is frequency-divided by 2 by a clock frequency dividing circuit (DIV) 110 and output to a programmable delay line (DL_MTX) 140 as a clock frequency dividing signal MPR. The count circuit (CNT) 120 counts the reference delay stage number DREF corresponding to one cycle of the clock,
Output to the duty adjustment circuit (DUTY_ADJ) 131. Duty adjustment circuit (DUTY_ADJ) 131
Is an arbitrary duty ratio RATIO set externally.
Is calculated and output to the programmable delay line (DL_MTX) 140. Programmable delay line (DL_MT
X) 140, a delay signal DMPR obtained by delaying the clock divided signal MPR based on the delay setting stage number DREFR
And a delay signal ZMPR delayed by the clock division signal MPR0 stage, and output to the pulse train generation circuit (MP_GEN) 150. The pulse train generation circuit (MP_GEN) 150 outputs the delay signals DMPR and Z
The exclusive logic with the MPR is calculated and output as a pulse train MP.

The operation of the above-described pulse width control circuit will be described with reference to operation waveforms. FIG. 14 is a timing chart of a variable duty ratio pulse width control circuit according to an embodiment of the present invention. Here, RATIO = 0.375 is set. The duty ratio of the clock signal CLK in the section T1 is 75%, and the duty ratio in the section T2 is 25%. As described above, since the clock signal CLK passes through the clock divider circuit (DIV) 110 and is divided by two, even if the duty ratio of the clock signal CLK changes, the clock signal CLK is not divided into signals after the clock divided signal MPR. Is not propagated. Thus, even if the duty ratio is made variable, it is possible to generate a pulse train controlled at an arbitrary duty ratio at the same frequency as the clock.

[0050]

As described above, the pulse width control circuit of the present invention generates a clock frequency-divided signal obtained by dividing the clock signal by two, and adjusts the clock frequency-divided signal according to the delay ratio determined by the preset clock duty ratio. Calculate the number of delay setting stages. A pulse train having a predetermined duty ratio is generated from a signal obtained by delaying the clock divided signal according to the number of delay setting stages and a signal obtained by delaying the clock divided signal by 0 stages.

For this reason, in an asynchronous or synchronous digital circuit using a system clock as one element of logic, an arbitrary duty ratio can be obtained at the same frequency as the clock without being affected by individual differences such as temperature, power supply disturbance, and process variation. It is possible to generate a controlled pulse train. Further, an external circuit or the like for this is not required. Further, the generated pulse train is a net independent of the system clock, and the clock can be supplied to other synchronous circuit portions and the like as in the related art. Therefore, it is not necessary to increase the load driving capability of the pulse train, and an improvement in response speed is expected.

Further, by incorporating the above-described pulse width control circuit as a multi-pulse generator into a recording compensation circuit for an optical disk such as an optical disk drive, the recording characteristics are stabilized and the system margin is expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram of a pulse width control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a D-flip-flop circuit which is an example of a clock frequency dividing circuit.

FIG. 3 is a block diagram of a delay lock detection circuit constituting the count circuit.

FIG. 4 is a block diagram of a bit shift circuit that is an example of a duty adjustment circuit.

FIG. 5 is a block diagram of a multiplication circuit which is an example of a duty adjustment circuit.

FIG. 6 is a circuit diagram of a delay chain using a NAND element as an example of a programmable delay line.

FIG. 7 is a circuit diagram of a delay circuit using an inverter and a multiplexer as an example of a programmable delay line.

FIG. 8 is a circuit diagram of a logic circuit which is an example of a pulse train generation circuit.

FIG. 9 is a timing chart of a pulse width control circuit according to an embodiment of the present invention.

FIG. 10 is a block diagram of a recording compensation circuit according to an embodiment of the present invention.

FIG. 11 is a timing chart of a recording compensation circuit according to an embodiment of the present invention.

FIG. 12 is a block diagram of a pulse width control circuit having a variable duty ratio according to an embodiment of the present invention.

FIG. 13 is a block diagram of a multiplication circuit that makes a duty ratio variable.

FIG. 14 is a timing chart of a pulse width control circuit having a variable duty ratio according to an embodiment of the present invention.

FIG. 15 is a configuration diagram of an example of a high-density optical recording device.

FIG. 16 shows a WP output signal and an LDC laser pulse emission waveform.

FIG. 17 is an operation waveform of an example of a phase change disk recording compensation circuit.

FIG. 18 is a timing chart of a recording pulse generation circuit using a multi-stage shift register.

[Explanation of symbols]

110: clock divider circuit (DIV), 120: count circuit (CNT), 130: duty adjustment circuit (DU)
TY_ADJ), 140: programmable delay line (DL_MTX), 150: pulse train generation circuit (M
P_GEN)

Claims (12)

[Claims] 1. A pulse width control circuit for generating a pulse train having a desired duty ratio, comprising: a clock signal synchronized with an output pulse; and a clock frequency divider circuit for generating a clock frequency divided signal obtained by dividing the clock signal by two. A count circuit that counts the number of reference delay stages corresponding to one cycle of the clock signal and outputs the count value; and calculates the number of delay setting stages according to a predetermined duty ratio that is input with the count value. A duty adjustment circuit; a programmable delay line that delays the clock division signal by the delay setting number of stages and outputs the clock division signal while delaying the clock division signal by 0 stages; and a delay setting stage by the programmable delay line. A predetermined value is obtained from the delayed output signal and the 0-stage delayed output signal. Pulse width control circuit, characterized in that it comprises a pulse train generating circuit for generating a pulse train the duty ratio, the. 2. The pulse width control circuit according to claim 1, wherein said clock frequency dividing circuit is a D-flip-flop circuit which divides an external clock by two and outputs it. 3. The count circuit calculates the number of delay stages to be counted down or counted up according to the length of the repetition period of the external clock, compares the current number of delay stages with the number of delay stages one clock before, and calculates a smaller value. 2. A pulse width control circuit according to claim 1, wherein said pulse width control circuit is a delay lock loop that outputs the reference delay stage number. 4. The pulse width control circuit according to claim 1, wherein the duty adjustment circuit calculates a value that is a half of the reference delay stage number as a delay setting stage number. 5. The pulse width control circuit according to claim 1, wherein the duty adjustment circuit is a bit shift circuit that shifts the count value by a predetermined number of bits. 6. The pulse width control circuit according to claim 1, wherein the duty adjustment circuit is a multiplication circuit that multiplies the count value by an arbitrary value. 7. The pulse width control circuit according to claim 1, wherein the duty adjustment circuit can further arbitrarily set the duty ratio from outside. 8. The programmable delay line includes a complementary metal oxide semiconductor (CMOS) connected in series.
2. The pulse width control circuit according to claim 1, wherein the pulse width control circuit comprises a buffer and a CMOS multiplexer. 9. The pulse train generation circuit determines rising and falling timings of a pulse output signal based on a rising edge of the output signal delayed by the delay setting number of stages and a rising edge of the output signal delayed by the zero stage. The pulse width control circuit according to claim 1, wherein: 10. The pulse train generation circuit according to claim 1, wherein the pulse train generation circuit calculates and outputs an exclusive OR of the output signal delayed by the number of delay setting stages and the output signal delayed by zero stages. Pulse width control circuit. 11. A recording compensation circuit for an optical disk for recording data according to a recording pulse obtained by synthesizing a start pulse, a multi-pulse, and an end pulse, wherein a clock signal synchronized with an output pulse is input, and the clock signal is A clock frequency dividing circuit for generating a clock frequency divided signal divided by 2, a count circuit for counting the number of reference delay stages corresponding to one cycle of the clock signal and outputting a count value thereof; A duty adjustment circuit that calculates the number of delay setting stages in accordance with the predetermined duty ratio, and a delay circuit that outputs the clock divided signal with the number of delay setting stages delayed and outputs the clock divided signal with a delay of 0 stage. A delay line and the programmable delay line (B) a pulse train generation circuit that generates a pulse train having a predetermined duty ratio from the output signal delayed by the set number of stages and the output signal delayed by zero, and a pulse width control circuit having: Optical disk recording compensation circuit. 12. The optical disk recording compensation circuit according to claim 11, wherein said pulse width control circuit generates a pulse train having a duty ratio of 50%.