JPH11272445A - Interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize picture transfer at low cost, at a high speed and with high picture quality in an interface circuit for transmitting picture information between a computer and a scanner inputting device. SOLUTION: A control part 2, write buffer 4, and read buffer 5 are provided between a picture reading means 1 and a CPU 3, and a bit for identifying a command, address, read, or write is provided in data from a computer side to a scanner inputting device side. Thus, the number of times of control data transfer and the number of signal lines in an interface can be reduced, and picture transfer can be realized at low cost, at a high speed and with high picture quality.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a scanner input device,
More specifically, the present invention relates to an interface circuit for transferring image data from a scanner to a computer and transferring control commands and data from the computer to a scanner input device.

[0002]

2. Description of the Related Art There is a system in the market for inputting image data such as a photograph read by a scanner into a computer and performing image processing such as image editing and deformation. In such a system, there is a need for an interface circuit for quickly, cheaply, and accurately transmitting image data having a significantly larger data amount than character data from a scanner to a computer.

FIG. 3 is a block diagram showing a conventional interface circuit. In FIG. 3, C is a scanner input device having an image reading unit 11 and a control unit 12. D indicates a computer having a CPU 13, a write buffer 14, and a read buffer 15.

The image reading means 11 outputs read image data p in response to a scanner control signal o.

When the read request signal q is input from the write buffer 14, the control unit 12 outputs a write buffer read signal r to the write buffer 14 so that the control unit address u and the read / write identification signal are output from the write buffer 14. Read s.

When the read / write identification signal s indicates a write (register write from the CPU), the control data v is read by outputting a write buffer read signal r to the write buffer 14 again to read the control data v. Store in the register specified by u.

On the other hand, when the read / write identification signal s indicates a read (register read from the CPU),
Control unit address u together with read buffer write signal t
Is output to the computer side.

The control section 12 reads an image by controlling a scanner control signal o when reading an image, and outputs a read buffer write signal t to the read buffer 15 together with the image data p.

The write buffer 14 is provided in the computer D. When a CPU write signal x is input, the write buffer 14 reads a CPU address z and control data v, and also reads a read request signal q and a read / write identification signal s corresponding to the CPU address z. Is output to the control unit 12, and when the write buffer read signal r is input, the control unit 12 outputs a control unit address u or control data v obtained from the CPU address z to the control unit 12.

When the read buffer write signal t is input, the read buffer 15 reads control data w and image data p output from the scanner input device C side, and
When the PU read signal y is inputted, the control data w and the image data p held are output.

Next, the operation of the conventional example will be described with reference to a timing chart shown in FIG. When the CPU 13 outputs the CPU write signal x, the CPU address z, and the control data v, the write buffer 14 fetches the CPU address z and the control data v, outputs the read request signal q to the scanner input device side, and A read / write identification signal s corresponding to the address z is output.

When the read request signal q is input, the control unit 12 first outputs a write buffer read signal r, and reads the control unit address u output from the write buffer 14 on the computer side.

Next, when the read / write identification signal s is write (register write from the CPU)
Outputs the write buffer read signal r again, reads the control data v output from the write buffer 14,
The control data v is written to the register corresponding to the previously read control unit address u.

On the other hand, when the read / write identification signal s is read (register read from the CPU), the control data w is taken out from the register corresponding to the previously read control unit address u together with the read buffer write signal t. Is output.

When the read buffer write signal t is input, the read buffer 15 receives the control data w input from the control unit 12. And the CPU 13 is the CPU
When the read signal y is output, the read buffer 15 outputs the held control data w to the CPU 13.

In the case of image reading, when the control unit 12 receives control data requesting start of image reading, it outputs a scanner control signal o to read an image.
The image data p is output to the read buffer 15 and a read buffer write signal t is output.

The read buffer 15 receives the image data p when the read buffer write signal t is input, and
The image data p is output to the CPU 13 in response to the CPU read signal y from the PU 13.

[0018]

In such an interface circuit, when the control data is read / written, it is necessary to always transfer the address and the control data twice in the interface portion, which lowers the transfer speed. .

In particular, when the scanner input device is not provided with a storage means such as a line memory, unless the image transfer is performed at a high speed and at a constant speed, the moving speed of the scanner becomes unstable and the image quality deteriorates. . For this reason,
The transfer of control data and the like is usually performed during a gap in image transfer, that is, during reading of invalid pixels such as dummy pixels. Can cause

As a solution to this problem, there is a method in which the address and data are first separated and the transfer speed is increased by transferring both at the same time. Connect.

There is also a method in which the operation of the scanner is specified in a command format and the transfer is performed once. However, in this case, a signal line for identifying a command or a normal address is separately required, and the cost is increased. There was a problem that it could be connected.

An object of the present invention is to solve such a problem and to provide an interface circuit capable of realizing low-cost, high-speed, high-quality image transfer.

[0023]

In the interface circuit of the present invention, a control unit, a write buffer, and a read buffer are provided between the image reading means and the CPU, and the data is transferred from the computer to the scanner input device. , Bits for identifying whether the data is a command or an address, or a read or a write.

According to the present invention, it is possible to obtain an interface circuit capable of realizing low-cost, high-speed, high-quality image transfer.

[0025]

1 is a block diagram showing an interface circuit for transmitting image information between a computer and a scanner input device according to a first embodiment of the present invention; A control command and data issued from the CPU are temporarily held between the scanner and the reading unit, a read request signal is issued to the scanner input device, and the control command and data are held according to a read signal from the scanner input device. A write buffer unit that outputs a control command or data to the scanner input device side, when a write signal is input from the scanner input device side, temporarily holds control data or image data output from the scanner input device side, A read buffer unit for outputting the data in response to a read signal from a CPU; In addition to controlling the output of image data, if there is a read request signal from the write buffer unit, a control signal or data is read from the write buffer unit by outputting a read signal, and a write signal is output. A control unit for writing control data and image data to the read buffer unit by performing a command for identifying a command or an address in data from the computer to the scanner input device. The interface circuit has a function of enabling low-cost, high-speed, high-quality image transfer.

According to a second aspect of the present invention, there is provided an interface circuit according to the first aspect, wherein a bit for identifying write or read is provided in data from the computer to the scanner input device. It has the effect of enabling high-speed and high-quality image transfer.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 is a block diagram showing an interface circuit according to a first embodiment of the present invention.

In FIG. 1, A is a scanner input device which has an image reading means 1 and a control section 2 and reads image data from an image original, and B has a CPU 3, a write buffer 4 and a read buffer 5, and 1 shows a computer that performs processing.

The image reading means 1 outputs image data b of an image read according to a scanner control signal a.
CD, contact image sensor, and the like.

When the read request signal c is input from the write buffer 4, the control section 2 outputs a write buffer read signal d to the write buffer 4 to read the address / command g. If a command is indicated (command write), the command g is executed.
If the read / write identification signal e indicates a write (CP
U), the control data h is read by outputting the write buffer read signal d again, and stored in the register specified by the address g.

On the other hand, if the read / write identification signal e indicates reading (register read from the CPU), the control data i stored in the address g is output to the computer together with the read buffer write signal f.

When reading an image, the control unit 2 controls the scanner control signal a, so that the image reading means 1 reads the image, and sends the read buffer write signal f together with the image data b to the read buffer 5. Output to

The write buffer 4 receives the CPU write signal j.
Is input, an address / command g and control data h are read, a read request signal c and a read / write identification signal e corresponding to the address / command g are output to the control unit 2, and a write buffer read signal d is input. Then, the address / command g or the control data h is output to the scanner input device.

The read buffer 5 reads the control data i and image data b output from the scanner device when the read buffer write signal f is input from the control unit 2 and holds the data when the CPU read signal k is input. The control data i and the image data b are output.

The read buffer 5 may be provided with a storage means such as a DRAM, a FIFO, a field memory, and a line memory for temporarily storing a large amount of image data.

Next, the operation of the interface circuit will be described with reference to FIG. FIG. 2 is a timing chart showing the operation of the interface circuit according to the first embodiment of the present invention. In FIG. 2, the CPU 3 outputs a CPU write signal j.
When the address / command g and the control data h are output, the write buffer 4 fetches the address / command g and the control data h, outputs a read request signal c to the control unit 2, and responds to the address / command g. The read / write identification signal e is output. When the read request signal c is input, the control unit 2 first outputs a write buffer read signal d and reads an address / command g output from the write buffer 4 on the computer side.

Next, the control unit 2 sets the read address /
If the command or bit indicating the address in the command g indicates the command (command write), the command is executed. If the bit indicates the address, the read / write identification signal e indicates the write (from the CPU). In the register write, the write buffer read signal d is output again, the control data h output from the write buffer 4 is read, and the control data h is written in the register corresponding to the previously read address g.

On the other hand, when the read / write identification signal e is read (register read from the CPU), the control data i is taken out from the register corresponding to the previously read address g together with the read buffer write signal f and output. I do.

When the read buffer write signal f is inputted, the read buffer 5 takes in the control data i inputted from the control unit 2. When the CPU 3 outputs the CPU read signal k, the read buffer 5 outputs the held control data i to the CPU 3.

When image reading is specified by a command,
After receiving the command g, the control unit 2 outputs a scanner control signal a, causes the image reading unit 1 to read an image, and causes the read buffer 5 to output the image data b. Then, a read buffer write signal f is output together with the image data b.

When the read buffer write signal f is input, the read buffer 5 takes in the image data b, and
The image data b corresponding to the CPU read signal k from U3
Is output to the CPU 3.

Therefore, by providing a bit for identifying a command or an address in an address / command g which is data of an interface from the computer to the scanner input device, a command from the CPU 3 can be issued. It becomes possible to reduce the number of transfers in the interface to one.

(Embodiment 2) The interface circuit according to Embodiment 2 of the present invention is a block diagram of the interface circuit according to Embodiment 1 of the present invention in FIG.
Instead of the read / write identification signal e, an address / command g is provided with a bit for identifying whether it is a read or a write.

In this case, the control unit 2 outputs the write buffer read signal d so that the address / command g
Is read, the command is executed if the bit for identifying the command or the address in the read address / command g indicates the command, and if the bit indicates the address, the address / command is indicated. g when the bit for identifying a write or read is a write (C
The register write from the PU) outputs the write buffer read signal d again, reads the control data h output from the write buffer 4, and writes the control data h to the register corresponding to the previously read address g.

On the other hand, when the bit for identifying write or read in the address / command g is write (register read from the CPU), the read buffer write signal f
At the same time, the control data i is extracted from the register corresponding to the previously read address g, and is output.

Therefore, by providing a bit indicating read or write in the address / command g, the read / write identification signal e, which is a signal line in the interface, can be eliminated.

In the first and second embodiments, data is read from the read buffer 5 by the CPU.
However, the same effect can be obtained by using DMA.

[0048]

As described above, according to the present invention, a control unit, a write buffer and a read buffer are provided between an image reading means and a CPU, and a command is included in data from the computer to the scanner input device. An interface that can reduce the number of control data transfers and the number of signal lines in the interface by providing bits for identifying whether the data is an address, read, or write, and realize low-cost, high-speed, high-quality image transfer. An advantageous effect that a circuit can be provided is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an interface circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the interface circuit according to the first embodiment of the present invention;

FIG. 3 is a block diagram showing a conventional interface circuit.

FIG. 4 is a timing chart showing the operation of a conventional interface circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image reading means 2 Control part 3 CPU 4 Write buffer 5 Read buffer 11 Image reading means 12 Control part 13 CPU 14 Write buffer 15 Read buffer

Claims (2)

[Claims] An interface circuit for transmitting image data between a computer and a scanner input device, wherein a control issued from the CPU is provided between a CPU of the computer and image reading means of the scanner input device. A write that temporarily holds commands and data, issues a read request signal to the scanner input device, and outputs the held control commands and data to the scanner input device in response to the read signal from the scanner input device. When a write signal is input from the buffer unit or the scanner input device side, the control unit temporarily stores control data and image data output from the scanner input device side and outputs the data in response to a read signal from the CPU. A buffer unit, while controlling output of image data from the image reading unit, If there is a read request signal from the write buffer unit, a control signal or data is read from the write buffer unit by outputting a read signal, and a read signal is output to the read buffer unit by outputting a write signal. An interface circuit including a control unit for writing control data and image data, and including a bit for identifying a command or an address in data from the computer to the scanner input device. 2. The interface circuit according to claim 1, wherein a bit for identifying write or read is provided in the data from the computer to the scanner input device.