JPH1127216A - Input existence detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make input disconnection detection time shorter and to make input disconnection release time and the input disconnection detection time well-balanced by balancing the change time of a detection signal from an input disconnection state to an input existence state and also in the reverse direction. SOLUTION: A transistor Q whose gate is applied output voltage of a voltage amplifier 10 to supplies charge current that is smaller than in the conventional manner to a capacitor C in accordance with its input voltage and also with the intervention or resistance R, makes the capacitor C charged and outputs the charge voltage of the capacitor C at a connection point of the resistance R and the capacitor C as peak voltage. The charge and discharge time of the capacitor C can be set by setting the value of the resistance R that is connected to an emitter of the transistor Q of a peak detector 11A. Input disconnection release time and input disconnection detection time of an optical input existence detection circuit 6A are respectively decided by the following. the input disconnection release time being about (VT/Iin +R).C, and the input disconnection detection time being about (C/Iin ).ΔV.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input presence / absence detection circuit for detecting the presence / absence of an input signal, and can be applied to, for example, an optical input presence / absence detection circuit for detecting the presence / absence of an optical signal in an optical receiver. .

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a main configuration of an optical receiving apparatus of an optical communication system for transmitting an optical signal by changing the on / off state of the optical signal according to the binary level of the digital signal.

In FIG. 2, an optical signal arriving at an optical receiving device via an optical fiber 1 includes a light receiving element 2a and a light receiving element 2a.
The signal is converted into an electric signal by an optical-electrical conversion unit 2 comprising a current / voltage conversion circuit 2b having a feedback resistance, and thereafter, is subjected to equalization amplification and waveform shaping by an equalization amplification unit 3, and is subjected to identification reproduction unit 4 and clock extraction. Provided to part 5. In the clock extraction unit 5, a clock signal is extracted from the input signal, and the clock signal is output to the identification reproduction unit 4, where the signal from the equalization amplification unit 3 is synchronized with the clock signal. The transmission signal (digital signal) is reproduced and output to a subsequent processing unit.

Here, in the optical receiving apparatus, the presence or absence of the input of the optical signal is detected based on the received signal converted into the electric signal (especially, the detection of the interruption of the input is often significant). A detection circuit 6 is provided, and a detection signal (input disconnection alarm signal) is output to a subsequent processing unit to change an operation mode of the subsequent processing unit.

FIG. 3 is a block diagram showing a detailed configuration of the conventional optical input presence / absence detection circuit 6 together with a detailed configuration of the clock extraction unit 5.

The clock extracting unit 5 comprises a timing filter 5a having a narrow band frequency characteristic for passing a clock frequency component, and a clock limiter 5b for pulsating an output signal thereof. Conventionally, the output signal of the timing filter 5a is input to the optical input presence / absence detection circuit 6 for the following reason.

APD (avalanche photodiode)
As described above, in the optical receiver using the light receiving element 2a in which the noise dark current increases due to the temperature characteristic, when detecting the presence or absence of the optical input based on the electric signal, the noise component leaks into the optical input presence / absence detection circuit 6. In some cases, an alarm signal indicating that the input has been cut off may erroneously indicate that an input has been made in the middle of an optical signal when there is no input. In order to solve such an inconvenience, as described above, the output signal from the timing filter 5a having a narrow band frequency characteristic and from which the noise component has been considerably removed is input to the optical input presence / absence detection circuit 6.

The optical input presence / absence detection circuit 6 detects the presence / absence of optical input based on the peak value of the input signal. That is, after the voltage amplifier 10 voltage-amplifies the output signal from the timing filter 5a, the peak voltage is detected by the peak detector 11, and the detected peak voltage and the reference voltage output from the reference voltage generation circuit 13 are compared. Are compared by, for example, a comparator 12 having an operational amplifier configuration.
A detection signal (alarm signal) indicating the presence or absence of an optical input was formed.

The peak detector 11 provided in the optical input presence / absence detection circuit 6 includes an NPN transistor Q and a capacitor C connected in series between a high power supply voltage and a low power supply voltage. The transistor Q having a gate to which the output voltage of the voltage amplifier 10 is applied supplies a charging current corresponding to the input voltage to the capacitor C to charge the capacitor C (of course, The charging voltage of the capacitor C at the time also defines the charging current amount), and the charging voltage of the capacitor C at the connection point between the emitter of the transistor Q and the capacitor C is output as a peak voltage.

[0010]

However, even with the conventional method, instantaneous noise components, such as shot noise and current noise of APD, and leakage of peak components of noise generated in an electric circuit are completely eliminated. There remains a problem that the alarm signal indicating the disconnection of the input instantaneously indicates the presence of the input in spite of the fact that the signal cannot be removed and the signal is not input. Therefore, measures such as lengthening the charging time determined by the time constant of the emitter differential resistance (re) of the transistor Q of the peak detector 11 and the capacitor capacitance C to prevent malfunction due to instantaneous noise components have been taken.

Here, the input disconnection release time and the input disconnection detection time of the optical input presence / absence detection circuit 6 are respectively the charging time of the peak detector 11 shown in the equation (1) and the charging time of the peak detector 11 shown in the equation (2). It is determined by the discharge time.

Note that the input disconnection release time of the optical input presence / absence detecting circuit 6 is a state in which the optical signal is changed to a state in which the optical input is present when the alarm signal indicates that the input is interrupted. The detection time of the optical input presence / absence detection circuit 6 is a time required for a transition as shown in FIG. This is the time until the alarm signal transitions to indicate an input disconnection.

Input disconnection release time ≒ (VT / Iin) · C (1) Input disconnection detection time ≒ (C / Iin) · ΔV (2) Here, VT is a thermal voltage (KT / q) of the transistor Q. ,
Iin is the input current to the comparator 12, and ΔV is the input difference voltage of the comparator 12.

As described above, when the input disconnection release time is to be increased to some extent in consideration of noise, (1)
As can be seen from the equation, the capacitor capacitance C is increased (Iin and VT cannot be arbitrarily set). However, in this case, as is apparent from the equation (2), the input disconnection detection time becomes considerably longer than the input disconnection release time. That is, the input disconnection release time required for detection when the state changes from the input disconnection state to the input presence state,
The balance with the input disconnection detection time required for detection when changing from the input presence state to the input disconnection state is poor.

For example, in the equation (1), when the input disconnection release time is set to 30 μs with the comparator input current Iin = 2 μA and the thermal voltage VT = 26 mV, the capacitor capacitance C
Is about 2300 pF. At this time, the input disconnection detection time is obtained by subtracting the comparator input differential voltage from the equation (2) by ΔV = 0.2
If it is V, it is 230 μs, which is almost eight times the input disconnection release time. Note that the comparator input difference voltage ΔV
Is reduced, the input disconnection detection time can be shortened. However, in this case, a small change in the charging voltage may cause erroneous detection, and setting it to less than 0.2 V is not practical.

Therefore, there is a demand for an input presence / absence detection circuit capable of shortening the input disconnection detection time as compared with the prior art, and achieving a balanced input disconnection release time and input disconnection detection time.

[0017]

In order to solve the above-mentioned problems, the present invention provides a peak detector for detecting a peak voltage of an input voltage, a reference voltage generating circuit for generating a reference voltage, and An input presence / absence detection circuit having a comparator that compares an output voltage with a reference voltage from the reference voltage generation circuit and outputs a detection signal indicating the presence / absence of an input signal; -1) a capacitor for holding a peak voltage, (A-2) a control transistor unit for controlling a charging current to the capacitor in accordance with an input voltage to the peak detector, and (A-3) an input signal. A circuit element for both change time balancing that balances the change time of the detection signal from the no input disconnection state to the input presence state with the input signal and the change time of the detection signal from the input presence state to the input disconnection state; Characterized in that it has.

A typical peak detector composed of a capacitor and a control transistor section keeps the peak voltage while following the peak voltage, so that the response speed during charging differs from the response speed during discharging. In this case, the change time of the detection signal from the input disconnection state where there is no input signal to the input existence state where the input signal is present differs from the change time of the detection signal from the input existence state to the input disconnection state. Therefore, in the present invention, in addition to the capacitor and the control transistor section, a circuit element for both change times is provided so as to balance both change times.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) First Embodiment Hereinafter, a first embodiment in which an input presence / absence detection circuit according to the present invention is applied to an optical input presence / absence detection circuit will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a detailed configuration of an optical input presence / absence detection circuit according to the first embodiment. The same reference numerals as in FIG. Is shown.

The arrangement of the optical input presence / absence detection circuit of the first embodiment in the optical receiver is also the position shown in FIG. 2 used in the above description of the related art.

Light input presence / absence detection circuit 6A of the first embodiment
In general, similarly to the conventional optical input presence / absence detection circuit 6,
It comprises a voltage amplifier 10, a peak detector 11A, a reference voltage generation circuit 13, and a comparator 12.

However, the detailed configuration of the peak detector 11A is different from the detailed configuration of the conventional peak detector 11.

The peak detector 11A according to the first embodiment includes:
The collector-emitter of the transistor Q, the resistor R, and the capacitor C are connected in series between the high power supply voltage terminal and the low power supply voltage terminal in this order, and the gate of the transistor Q is connected to the output terminal of the voltage amplifier 10; It has a configuration in which a connection point between the resistor R and the capacitor C is connected to the inverting input terminal of the comparator 12.

The optical input presence / absence detection circuit 6A of the first embodiment
Basically, it operates in the same manner as the conventional optical input presence / absence detection circuit 6.

Timing filter 5 of clock extraction unit 5
After the voltage signal output from a is amplified to a required amplitude level by the voltage amplifier 10, the peak value of the amplified signal is detected by the peak detector 11, and a DC voltage representing the peak value is generated. Such a peak DC voltage is input to the inverting input terminal of the comparator 12 and compared with the reference voltage from the reference voltage generating circuit 13 input to the non-inverting input terminal of the comparator 13. When the peak DC voltage is at a level higher than the reference voltage, the comparator 12 outputs an L-level alarm signal indicating an input presence state. When the peak DC voltage is at a level lower than the reference voltage, the comparator 12 outputs a signal. An H level alarm signal indicating an input disconnection state is output.

The peak detector 11A of the first embodiment operates as follows to form a peak DC voltage.

The transistor Q having the gate to which the output voltage of the voltage amplifier 10 is applied responds to the input voltage and the resistor R interposes, so that the charging current whose resistance R is smaller than that of the conventional transistor is supplied to the capacitor C. To charge the capacitor C (of course, the capacitor C at that time)
The charging voltage of the capacitor C also defines the charging current amount), and the charging voltage of the capacitor C at the connection point between the resistor R and the capacitor C is output as a peak voltage.

In the optical input presence / absence detection circuit 6A of the first embodiment, since the resistor R is connected to the emitter of the transistor Q in the peak detector 11A, the value of the resistor R can be set arbitrarily. , The charging and discharging time of the capacitor C can be set arbitrarily.

Light input presence / absence detection circuit 6A of the first embodiment
The input disconnection release time (charge time of the peak detector 11A) and the input disconnection detection time (discharge time of the peak detector 11A) are determined by the equations (3) and (4), respectively.
The input disconnection detection time is the same as the conventional one (Equations (2) and (4) are the same).

Input disconnection release time ≒ (VT / Iin + R) · C (3) Input disconnection detection time ≒ (C / Iin) · ΔV (4) For example, in equation (3), a resistor R = 100 kΩ, a comparator When the input current Iin = 2 μA, the thermal voltage VT = 26 mV, and the input disconnection release time is set to 30 μs, the capacitance C is about 270 pF. The input disconnection detection time at this time is
In the equation (4), if the comparator input difference voltage ΔV is 0.2 V, it becomes 27 μs, and the input disconnection release time and the input disconnection detection time become substantially equal.

According to the first embodiment, since the resistor R is added to the emitter of the transistor Q of the peak detector, the value of the resistor R can be set so as to balance the charging and discharging time, and Input disconnection detection time can be shortened compared to the conventional model, and input disconnection release time and input disconnection detection time can be prevented while ensuring that input detection errors can be prevented from being erroneously detected in the middle of a non-input state continued by a typical noise component. Can be balanced.

(B) Second Embodiment Next, a second embodiment in which the input presence / absence detection circuit according to the present invention is applied to an optical input presence / absence detection circuit will be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing a detailed configuration of the optical input presence / absence detection circuit according to the second embodiment.
The same or corresponding parts as those in FIG. 1 according to the embodiment are denoted by the same or corresponding reference numerals.

The optical input presence / absence detection circuit of the second embodiment is also arranged in the optical receiver at the position shown in FIG. 2 used in the above description of the related art.

Light input presence / absence detection circuit 6B of the second embodiment
In general, similarly to the conventional optical input presence / absence detection circuit 6,
It comprises a voltage amplifier 10, a peak detector 11B, a reference voltage generation circuit 13, and a comparator 12.

However, the detailed configuration of the peak detector 11B is different from the detailed configuration of the peak detector 11A of the first embodiment.

The peak detector 11B of the second embodiment is
The collector-emitter of the transistor Q, the resistor R, and the capacitor C are connected in series between the high power supply voltage terminal and the low power supply voltage terminal in this order, and the transistor Q is connected in parallel to the series circuit portion of the resistor R and the capacitor C. Is connected to the bias resistor RE. Further, the gate of the transistor Q is connected to the output terminal of the voltage amplifier 10,
It has a configuration in which a connection point between the resistor R and the capacitor C is connected to the inverting input terminal of the comparator 12.

Light input presence / absence detection circuit 6B of the second embodiment
Basically, the circuit operates in the same manner as the conventional or the optical input presence / absence detection circuit of the first embodiment, and the description thereof is omitted.

In the peak detector 11B of the second embodiment, the transistor Q is set to a state in which the bias current IRE flows by the bias resistor RE. When such a bias current IRE flows, the transistor Q
Depends on the input voltage applied to the gate and the resistance R
, The charging current reduced by the resistance value R is supplied to the capacitor C to charge the capacitor C (of course, the charging voltage of the capacitor C at that time also defines the charging current amount). , Resistor R and capacitor C
And outputs the charging voltage of the capacitor C at the connection point with the peak voltage. Note that the bias resistor RE also functions strongly as a discharge path for the charging voltage of the capacitor C.

Light input presence / absence detection circuit 6B of the second embodiment
The input disconnection release time (charge time of the peak detector 11B) and the input disconnection detection time (discharge time of the peak detector 11B) are determined by Expressions (5) and (6), respectively.
The input disconnection release time is the same as in the first embodiment (Equations (3) and (5) are the same).

Input disconnection release time ≒ (VT / Iin + R) · C (5) Input disconnection detection time ≒ (C / IRE) · ΔV (6) For example, in equation (5), a resistor R = 10 kΩ, a comparator When the input current Iin = 2 μA, the thermal voltage VT = 26 mV, and the input disconnection release time is set to 30 μs, the capacitance C becomes 1
It is about 300 pF. The input disconnection detection time at this time is
In the equation (6), if the bias current IRE is 10 μA and the comparator input difference voltage ΔV is 0.2 V, it becomes 26 μs, and the input disconnection release time and the input disconnection detection time are substantially equal.

According to the second embodiment, since the bias resistor RE and the resistor R are added to the emitter of the transistor Q of the peak detector, the values of the bias current IRE and the resistor R determined by the bias resistor RE are used for the charge / discharge time. The input disconnection detection time is shorter than before while ensuring that the balance can be set, and that it is possible to prevent erroneous detection of the presence of an input in the middle of a continuous no-input state due to instantaneous noise components. Thus, the input disconnection release time and the input disconnection detection time can be balanced.

In addition to the effects similar to those of the first embodiment, the provision of the bias resistor RE enables the first
Compared with the embodiment, it is expected that the peak detector 11B has a wider band and a higher speed operation.

(C) Third Embodiment Next, a third embodiment in which the input presence / absence detection circuit according to the present invention is applied to an optical input presence / absence detection circuit will be described in detail with reference to the drawings.

FIG. 5 is a block diagram showing a detailed configuration of the optical input presence / absence detection circuit according to the third embodiment.
The same or corresponding parts as those in FIG. 4 according to the embodiment are denoted by the same or corresponding reference numerals.

The optical input presence / absence detection circuit of the third embodiment is also arranged in the optical receiver at the position shown in FIG. 2 used in the above description of the related art.

Light input presence / absence detection circuit 6C of the third embodiment
Also, roughly, the voltage amplifier 10, the peak detector 11C,
It comprises a reference voltage generating circuit 13 and a comparator 12.

However, the detailed configuration of the peak detector 11C is different from the peak detectors 11A, 11A of the first and second embodiments.
B is different from the detailed configuration.

The peak detector 11C according to the third embodiment includes:
As is clear from the comparison between FIG. 4 and FIG. 5, the bias resistor RE in the peak detector 11B of the second embodiment is replaced with a constant current source Ie. This constant current source Ie
Is for constantly flowing a bias current to the transistor Q. Therefore, the peak detector 11C of the third embodiment is
It operates similarly to the peak detector 11B of the second embodiment.

In the case of a method in which a bias current is always supplied by the bias resistor RE, the bias current is affected by the temperature characteristics of the transistor Q.
(The sign Ie sometimes means a constant current value (bias current value)), and the influence of temperature fluctuation is smaller than that of the bias current.

Light input presence / absence detection circuit 6C of the third embodiment
The input disconnection release time (charge time of the peak detector 11C) and the input disconnection detection time (discharge time of the peak detector 11C) are determined by Expressions (7) and (8), respectively.
Note that the input disconnection release time is the same as in the second embodiment (Equations (5) and (7) are the same).

Input disconnection release time ≒ (VT / Iin + R) · C (7) Input disconnection detection time ≒ (C / Ie) · ΔV (8) For example, in the equation (7), a resistor R = 10 kΩ, a comparator When the input current Iin = 2 μA, the thermal voltage VT = 26 mV, and the input disconnection release time is set to 30 μs, the capacitance C becomes 1
It is about 300 pF. The input disconnection detection time at this time is
In the equation (8), the constant current (bias current) Ie is set to 10
μA and the comparator input difference voltage ΔV is 0.2 V, 26
μs, and the input disconnection release time and the input disconnection detection time are substantially equal.

According to the third embodiment, the same effect as that of the second embodiment can be obtained because the resistor R and the constant current source Ie for allowing the bias current to flow out are added to the emitter of the transistor Q. .

In addition to this, according to the third embodiment,
Since the constant current source Ie is applied as a configuration for allowing the bias current to flow out, the bias current of the transistor Q can be stabilized as compared with the second embodiment, and the input disconnection detection time varies due to a temperature change. Can be suppressed.

(D) Fourth Embodiment Next, a fourth embodiment in which the input presence / absence detection circuit according to the present invention is applied to an optical input presence / absence detection circuit will be described in detail with reference to the drawings.

FIG. 6 is a block diagram showing a detailed configuration of the optical input presence / absence detection circuit according to the fourth embodiment.
The same or corresponding parts as those in FIG. 5 according to the embodiment are denoted by the same or corresponding reference numerals.

The optical input presence / absence detection circuit of the fourth embodiment is also arranged in the optical receiver at the position shown in FIG. 2 used in the above-described conventional description.

Light input presence / absence detection circuit 6D of the fourth embodiment
Also, roughly, the voltage amplifier 10D and the peak detector 11
D, a reference voltage generating circuit 13 and a comparator 12.

However, the detailed configuration of the peak detector 11D is the same as that of the peak detector 11D of the first, second, and third embodiments.
A, 11B, and 11C are different from the detailed configuration. Also,
As the voltage amplifier 10D, a two-output configuration having a positive phase and a negative phase is applied.

The peak detector 11D according to the fourth embodiment comprises:
As is clear from the comparison between FIGS. 5 and 6, the transistor Q in the peak detector 11C of the third embodiment is replaced by a differential pair of two transistors Q1 and Q2. The positive and negative phase amplified output voltages from the voltage amplifier 10D are applied to the gates of these transistors Q1 and Q2, respectively.

Accordingly, the peak detector 1 of the fourth embodiment
1D operates almost the same as the peak detector 11B of the third embodiment, although there is a difference in whether the active element for controlling the charging current is a single transistor Q or a differential pair configuration of the transistors Q1 and Q2. Things.

In the case where the active element for controlling the charging current is a single transistor Q, the influence of the offset voltage due to manufacturing variations of the voltage amplifier 10 is determined by the peak detector 11C.
However, when a differential amplification pair configuration of the transistors Q1 and Q2 is applied as the active element for controlling the charging current, the influence of the offset voltage due to the manufacturing variation of the voltage amplifier 10D is determined by the differential operation in the peak detector 11D. Can be compensated.

Light input presence / absence detection circuit 6D of the fourth embodiment
The input disconnection release time (charging time of the peak detector 11D) and the input disconnection detection time (discharge time of the peak detector 11D) are the same as in the third embodiment, respectively, in the above-described equations (7) and (8). Determined by the formula. That is, by appropriately selecting the values of the bias current Ie, the resistor R, and the capacitor C, the input disconnection release time and the input disconnection detection time can be made substantially equal.

According to the fourth embodiment, the same effects as those of the third embodiment can be obtained. In addition to this, according to the fourth embodiment, a differential pair configuration of the transistors Q1 and Q2 is applied as an active element for controlling a charging current, and peaks occur in both the positive and negative phase outputs of the voltage amplifier 10D. Value detection, the voltage amplifier 10D
Can be compensated for.

(E) Fifth Embodiment Next, a fifth embodiment in which the input presence / absence detection circuit according to the present invention is applied to an optical input presence / absence detection circuit will be described in detail with reference to the drawings.

FIG. 7 is a block diagram showing a detailed configuration of the optical input presence / absence detection circuit according to the fifth embodiment.
The same and corresponding parts as those in FIG. 6 according to the embodiment are denoted by the same or corresponding reference numerals.

The arrangement of the optical input presence / absence detection circuit of the fifth embodiment in the optical receiver is the position shown in FIG. 2 used in the above description of the conventional art.

The optical input presence / absence detection circuit 6E of the fifth embodiment differs from the optical input presence / absence detection circuit 6E only in the internal configuration of the reference voltage generation circuit 13E.
The fourth embodiment is different from that of the fourth embodiment, and other configurations are the same as those of the fourth embodiment, and the description thereof is omitted.

The reference voltage generating circuit 13 of the fourth embodiment
Is based on a general configuration for generating a reference voltage that does not include an active element such as dividing a power supply voltage by resistance.

The reference voltage generating circuit 1 according to the fifth embodiment
3E receives an original reference voltage generator DC that generates an original reference voltage by dividing a power supply voltage by resistance, a voltage amplifier 13Ea that amplifies the voltage, and a positive-phase output and a negative-phase output of the voltage amplifier 13Ea. Transistors Q3 and Q4 forming a differential pair performing differential operation, and these transistors Q
A constant current source Ie2 for allowing a bias current to flow out of the differential pair to drive 3 and Q4, and a resistor for applying the voltage of the common emitter of the differential pair to the non-inverting input terminal of the comparator 12 as a reference voltage for comparison. R2.

The reason why the reference voltage generating circuit 13E has the above-described internal configuration is that the peak detector 11
This is for compensating the temperature fluctuation of the input voltage from D and the power supply voltage fluctuation. That is, the DC configuration is the same as that of the voltage amplifier 1 and the peak detector.
Since E has the same configuration as the connection configuration of the active elements in the peak detector 11D, the reference voltage applied to the comparator 12 in response to temperature fluctuations and power supply voltage fluctuations also changes. In the same manner as the input voltage fluctuation from the peak detector 11D to the comparator 12 to compensate for the temperature fluctuation of the input voltage from the peak detector 11D and the power supply voltage fluctuation.

The optical input presence / absence detection circuit 6E according to the fifth embodiment.
The input disconnection release time (charging time of the peak detector 11D) and the input disconnection detection time (discharge time of the peak detector 11D) are the same as in the third and fourth embodiments, respectively, using the above-described equation (7) and It is determined by equation (8). That is,
By appropriately selecting the values of the bias current Ie, the resistor R, and the capacitor C, the input disconnection release time and the input disconnection detection time can be made substantially equal.

According to the fifth embodiment, the same effects as those of the fourth embodiment can be obtained.

In addition to this, according to the fifth embodiment,
Since the reference voltage generation circuit 13E is configured so as to correspond to the detailed configuration of the peak detector 11D, the temperature fluctuation and the power supply voltage fluctuation of the input voltage from the peak detector 11D to the comparator 12 are determined by the reference voltage generation circuit 13E. Can be completely compensated for by the reference voltage.

(F) Other Embodiments In each of the embodiments described above, the output signal of the timing filter 5a is given to the optical input presence / absence detection circuit. You may make it input into an existence detection circuit.

Further, it is needless to say that the example of the circuit constant referred to in the description of each of the above embodiments is not limited to this.

In each of the above embodiments, the active element constituting the peak detector is an NPN transistor. However, a peak detector using a PNP transistor can be applied. Can be applied.

Further, in each of the above embodiments,
Although the present invention is applied to an optical input presence / absence detection circuit, the invention can be applied to an input presence / absence detection circuit in which a transmission signal from an opposing device is an electric signal (including wireless).

[0080]

As described above, according to the present invention, in the input presence / absence detection circuit for comparing the peak voltage of the input voltage with the reference voltage and outputting a detection signal indicating the presence / absence of the input signal, the peak detector includes: A capacitor that holds the peak voltage, a control transistor section that controls the charging current to the capacitor according to the input voltage to the peak detector, and a state in which the input signal has no input signal and the input signal has an input signal. It has a circuit element for both change time balancing that balances the change time of the detection signal and the change time of the detection signal from the input state to the input cutoff state. The release time and the input disconnection detection time can be balanced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment.

FIG. 2 is a block diagram illustrating an overall configuration of an optical receiving device.

FIG. 3 is a block diagram showing a conventional configuration.

FIG. 4 is a block diagram illustrating a configuration of a second embodiment.

FIG. 5 is a block diagram showing a configuration of a third embodiment.

FIG. 6 is a block diagram illustrating a configuration of a fourth embodiment.

FIG. 7 is a block diagram showing a configuration of a fifth embodiment.

[Explanation of symbols]

5 clock extractor, 5a timing filter, 6A
６6D: Optical input presence / absence detection circuit, 10, 10D, 13Ea
... voltage amplifiers, 11A to 11D ... peak detectors, 12 ...
Comparator, 13, 13E: Reference voltage generation circuit, Q, Q1
Q4: transistor, C: capacitor, R, R2: resistor, RE: bias resistor, Ie, Ie2: constant current source.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04B 10/02 10/18 (72) Inventor Masaaki Maeda 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. 72) Inventor Shoji Hyoto 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Hiroshi Okada 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (6)

[Claims] 1. A peak detector for detecting a peak voltage of an input voltage, a reference voltage generating circuit for generating a reference voltage, and comparing an output voltage from the peak detector with a reference voltage from the reference voltage generating circuit. An input presence / absence detection circuit having a comparator that outputs a detection signal indicating the presence / absence of an input signal, wherein the peak detector has a capacitor that holds a peak voltage, and a voltage that is input to the peak detector. A control transistor unit for controlling a charging current to the capacitor; a change time of the detection signal from an input disconnection state where no input signal is present to an input presence state where an input signal is present; An input presence / absence detection circuit, comprising: a circuit element for both change time balancing for balancing a signal change time. 2. The input presence / absence detection circuit according to claim 1, wherein the circuit element for both change time balancing is a resistance element interposed between the capacitor and the control transistor unit. 3. The control transistor, wherein the circuit element for both change time balancing is connected in parallel to a resistor element interposed between the capacitor and the control transistor unit, and a series circuit of the capacitor and the resistor. 2. The input presence / absence detection circuit according to claim 1, wherein the input presence / absence detection circuit is a bias resistor for the unit. 4. The control transistor, wherein both the change time balancing circuit elements are connected in parallel to a resistor element interposed between the capacitor and the control transistor section, and a series circuit of the capacitor and the resistor. 2. The input presence / absence detection circuit according to claim 1, wherein the input presence / absence detection circuit is a constant current source that supplies a bias current to the unit. 5. The control transistor unit according to claim 1, wherein the control transistor unit comprises a differential amplifier pair of two transistors to which a positive-phase input voltage and a negative-phase input voltage are input and perform a differential amplification operation. An input presence / absence detection circuit according to any one of the above. 6. The reference voltage generating circuit has an original reference voltage generating section for generating an original reference voltage, and a transistor section having the same connection configuration as a control transistor section in the peak detector. Outputting a reference voltage capable of compensating for the influence of temperature fluctuations and power supply voltage fluctuations of the control transistor section in the peak detector through the amplifying operation of the original reference voltage by the transistor section. The input presence / absence detection circuit according to any one of the above.