JPH0260351U - - Google Patents
Info
- Publication number
- JPH0260351U JPH0260351U JP1988139132U JP13913288U JPH0260351U JP H0260351 U JPH0260351 U JP H0260351U JP 1988139132 U JP1988139132 U JP 1988139132U JP 13913288 U JP13913288 U JP 13913288U JP H0260351 U JPH0260351 U JP H0260351U
- Authority
- JP
- Japan
- Prior art keywords
- clock pulse
- phase
- clock
- output
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 5
- 239000000284 extract Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Optical Communication System (AREA)
Description
第１図は本考案によるクロツクパルス抽出回路
の実施例を示す回路図、第２図は本考案によるク
ロツクパルス抽出回路におけるジツタ検波部の回
路図、第３図は、第２図の回路動作を説明するた
めの波形図、第４図はクロツクパルス抽出回路の
従来例を示す回路図である。
１……等化波形入力端子、２……クロツク抽出
フイルタ、３……リミツタ増幅部、４……クロツ
クパルス出力端子、５……レベル検出部、６……
基準電圧、７……比較器、８……光入力断検出信
号の出力端子、９……ジツタ検出部、１０……増
幅器、１１……クロツクパルス入力端子、１２…
…モノステーブル・マルチバイブレータ、１３，
１４，１５……トランジスタ、１６，１７，１８
，１９，２０……抵抗器、２１……コンデンサ、
２２，２３……電源電圧、２４……増幅器、２５
……比較器、２６，２７……基準電圧、２８……
出力端子。
FIG. 1 is a circuit diagram showing an embodiment of the clock pulse extraction circuit according to the present invention, FIG. 2 is a circuit diagram of the jitter detection section in the clock pulse extraction circuit according to the present invention, and FIG. 3 explains the operation of the circuit shown in FIG. 2. FIG. 4 is a circuit diagram showing a conventional example of a clock pulse extraction circuit. DESCRIPTION OF SYMBOLS 1...Equalized waveform input terminal, 2...Clock extraction filter, 3...Limiter amplification section, 4...Clock pulse output terminal, 5...Level detection section, 6...
Reference voltage, 7...Comparator, 8...Output terminal for optical input interruption detection signal, 9...Jitter detection section, 10...Amplifier, 11...Clock pulse input terminal, 12...
...Monostable multivibrator, 13,
14, 15...transistor, 16, 17, 18
, 19, 20...Resistor, 21...Capacitor,
22, 23...Power supply voltage, 24...Amplifier, 25
... Comparator, 26, 27 ... Reference voltage, 28 ...
Output terminal.
Claims (1)
する光受信回路に設けられ、等化波形よりクロツ
クを抽出するとともに、クロツク検波出力と基準
電圧とを比較することにより光入力断検出信号を
出力するクロツクパルス抽出回路において、前記
クロツク検波の前段に、前記抽出したクロツクパ
ルスの位相を監視し、クロツクパルスの位相が正
常の場合は所定レベル信号を出力し、クロツクパ
ルスの位相が乱れた場合は、乱れに対応した前記
所定レベル信号より低いレベル信号を出力するジ
ツタ検波部を設け、クロツクパルスの位相の乱れ
が大きい場合にも前記光入力断検出信号を出力す
るように構成したことを特徴とするクロツクパル
ス抽出回路。 A clock pulse provided in an optical receiving circuit that demodulates an optical waveform intensity-modulated by a data signal, extracts a clock from an equalized waveform, and outputs an optical input interruption detection signal by comparing the clock detection output and a reference voltage. In the extraction circuit, before the clock detection, the phase of the extracted clock pulse is monitored, and when the phase of the clock pulse is normal, a predetermined level signal is output, and when the phase of the clock pulse is disturbed, the phase of the clock pulse corresponding to the disturbance is output. A clock pulse extraction circuit comprising a jitter detection section that outputs a level signal lower than a predetermined level signal, and configured to output the optical input interruption detection signal even when there is a large phase disturbance of the clock pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988139132U JPH0646116Y2 (en) | 1988-10-25 | 1988-10-25 | Clock pulse extraction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988139132U JPH0646116Y2 (en) | 1988-10-25 | 1988-10-25 | Clock pulse extraction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0260351U true JPH0260351U (en) | 1990-05-02 |
| JPH0646116Y2 JPH0646116Y2 (en) | 1994-11-24 |
Family
ID=31402109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988139132U Expired - Lifetime JPH0646116Y2 (en) | 1988-10-25 | 1988-10-25 | Clock pulse extraction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0646116Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1127216A (en) * | 1997-07-03 | 1999-01-29 | Oki Tec:Kk | Input existence detection circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6059415A (en) * | 1983-09-13 | 1985-04-05 | Nec Corp | Clock-off detecting circuit |
| JPS63198433A (en) * | 1987-02-13 | 1988-08-17 | Nec Corp | Clock recovery circuit |
-
1988
- 1988-10-25 JP JP1988139132U patent/JPH0646116Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6059415A (en) * | 1983-09-13 | 1985-04-05 | Nec Corp | Clock-off detecting circuit |
| JPS63198433A (en) * | 1987-02-13 | 1988-08-17 | Nec Corp | Clock recovery circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1127216A (en) * | 1997-07-03 | 1999-01-29 | Oki Tec:Kk | Input existence detection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0646116Y2 (en) | 1994-11-24 |
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