JPH11265978A - Manufacture of semiconductor device and semiconductor device using the method - Google Patents

Manufacture of semiconductor device and semiconductor device using the method

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Publication number
JPH11265978A
JPH11265978A JP6737298A JP6737298A JPH11265978A JP H11265978 A JPH11265978 A JP H11265978A JP 6737298 A JP6737298 A JP 6737298A JP 6737298 A JP6737298 A JP 6737298A JP H11265978 A JPH11265978 A JP H11265978A
Authority
JP
Japan
Prior art keywords
electrode
film
capacitor
area
lower electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6737298A
Other languages
Japanese (ja)
Inventor
Mitsuru Fujisaki
満 藤崎
Yasutaka Ishibashi
保孝 石橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Kasei Microsystems Co Ltd
Original Assignee
Asahi Kasei Microsystems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Kasei Microsystems Co Ltd filed Critical Asahi Kasei Microsystems Co Ltd
Priority to JP6737298A priority Critical patent/JPH11265978A/en
Publication of JPH11265978A publication Critical patent/JPH11265978A/en
Withdrawn legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To increase the capacitance of a capacitor without changing the occupying area of the capacitor on a semiconductor substrate. SOLUTION: A polycrystal silicon film 2 formed on a semiconductor substrate 1 is etched into a head-mounting shaped conical form with a circular resist pattern 3 as a mask, and a lower electrode 2a is formed. A silicon oxide film 4 and a polycrystal silicon film 5 are formed so as to cover the lower electrode 2a, and a capacitor 10 is formed. At this time, e.g. the polycrystal silicon film 2 of the capacitor 10 is formed thicker. Etching is performed by using the above described resist pattern 3, and so on. When the tilt angle is made large with the bottom area of the lower electrode 22 being intact by this way, the area of the slant surface of the lower electrode 2a is increased accompanied by the change in slant angle. That is to say, the surface area of the silicon oxide film 4 becomes also large. Since the bottom area is same, the capacitance of the capacitor 10 is increased with the occupying area of the lower electrode 2a on the semiconductor substrate 1 being same.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置の製造
方法及びこれを用いた半導体装置に関し、特に、基板上
における占有面積を変えずに、より大きな容量が得られ
るようにしたキャパシタに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device using the same, and more particularly, to a capacitor capable of obtaining a larger capacitance without changing the area occupied on a substrate.

【0002】[0002]

【従来の技術】従来、半導体基板上にキャパシタを形成
する場合等には、例えば図4に示すように、半導体基板
1上に多結晶シリコン膜11を形成し、この上にシリコ
ン酸化膜12を形成し、再度多結晶シリコン膜13を形
成し、これを、エッチングすること等によって形成する
ようにしている。
2. Description of the Related Art Conventionally, when a capacitor is formed on a semiconductor substrate, for example, as shown in FIG. 4, a polycrystalline silicon film 11 is formed on a semiconductor substrate 1 and a silicon oxide film 12 is formed thereon. After that, the polycrystalline silicon film 13 is formed again, and this is formed by etching or the like.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来の半導体装置においては、図4に示すようにキャパシ
タが直方体状であって、シリコン酸化膜12の膜厚は変
えずにキャパシタの容量の増大を図る場合、キャパシタ
の容量はシリコン酸化膜12の平面積で決まることか
ら、半導体基板1上におけるキャパシタの占有面積が増
加することになり、半導体装置の微細化,高集積化の妨
げとなってしまう。そのため、占有面積を増加させるこ
となく、キャパシタの容量の増大を図ることの可能な半
導体装置及びその製造方法が望まれていた。
However, in the above-mentioned conventional semiconductor device, as shown in FIG. 4, the capacitor has a rectangular parallelepiped shape, and the capacitance of the capacitor is increased without changing the thickness of the silicon oxide film 12. In this case, since the capacitance of the capacitor is determined by the plane area of the silicon oxide film 12, the area occupied by the capacitor on the semiconductor substrate 1 increases, which hinders miniaturization and high integration of the semiconductor device. . Therefore, a semiconductor device capable of increasing the capacitance of a capacitor without increasing the occupied area and a method for manufacturing the same have been desired.

【0004】そこで、この発明は、上記従来の未解決の
問題に着目してなされたものであり、半導体基板上にお
けるキャパシタの占有面積を変えることなく、キャパシ
タの容量の増大を図ることの可能な半導体装置及びその
製造方法を提供することを目的としている。
Therefore, the present invention has been made in view of the above-mentioned conventional unsolved problem, and it is possible to increase the capacitance of a capacitor without changing the area occupied by the capacitor on a semiconductor substrate. It is an object to provide a semiconductor device and a method for manufacturing the same.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明の請求項1に係る半導体装置の製造方法は、
基板上にキャパシタが形成された半導体装置の製造方法
であって、前記基板上に電極形成用の膜を形成した後、
これをエッチングして裁頭状の錐体形の電極用核を形成
し、当該電極用核の表面全体を覆うように絶縁膜を形成
し、さらに、当該絶縁膜の表面全体を覆うように電極用
膜を形成することを特徴としている。
In order to achieve the above object, a method of manufacturing a semiconductor device according to claim 1 of the present invention comprises:
A method for manufacturing a semiconductor device in which a capacitor is formed on a substrate, comprising: forming a film for forming an electrode on the substrate;
This is etched to form a truncated cone-shaped electrode nucleus, an insulating film is formed so as to cover the entire surface of the electrode nucleus, and further, an electrode film is formed so as to cover the entire surface of the insulating film. It is characterized by forming a film.

【0006】この請求項1の発明では、基板上に電極形
成用の膜が形成された後、これが裁頭状の錐体形にエッ
チングされ、つまり、錐体形の上部が底面と平行な面で
裁断され、その上部を取り除いた形状であり上面が平坦
な形状にエッチングされ、この裁頭状の錐体形からなる
電極用核が形成される。そして、この電極用核の表面全
体を覆うように絶縁膜が形成され、さらに、電極用核及
び絶縁膜の積層構造からなる裁頭状の錐体形の表面全
体、つまり絶縁膜の上面及び傾斜面を覆うように電極用
膜が形成されて、裁頭状の錐体形のキャパシタが構成さ
れる。
According to the first aspect of the present invention, after a film for forming an electrode is formed on a substrate, it is etched into a truncated cone shape, that is, the upper portion of the cone shape is cut along a plane parallel to the bottom surface. Then, the upper surface is removed and the upper surface is etched into a flat shape, thereby forming a truncated cone-shaped electrode core. Then, an insulating film is formed so as to cover the entire surface of the electrode nucleus, and further, the entire surface of a truncated cone having a laminated structure of the electrode nucleus and the insulating film, ie, the upper surface and the inclined surface of the insulating film The electrode film is formed so as to cover the substrate, thereby forming a truncated cone-shaped capacitor.

【0007】このキャパシタの容量を変化させるには、
絶縁膜の平面積を変化させればよく、つまり、後の電極
用核となる電極形成用の膜を形成する際に、膜厚を調整
するか、或いは電極形成用の膜を裁頭状の錐体形にエッ
チングする際にレジストの形状を調整すること等によ
り、裁頭状の錐体形である電極用核の傾斜面の傾きを変
化させ、傾斜面の平面積を変化させればよい。このと
き、その底面積つまり、基板上におけるキャパシタの占
有面積は同一であるから、占有面積は同一のままキャパ
シタの容量の変更が行われることになる。
To change the capacitance of this capacitor,
The plane area of the insulating film may be changed, that is, when forming a film for forming an electrode to be a core for an electrode later, the film thickness may be adjusted or the film for forming an electrode may be formed into a truncated shape. By adjusting the shape of the resist at the time of etching into a cone shape, the inclination of the inclined surface of the electrode core having a truncated cone shape may be changed, and the plane area of the inclined surface may be changed. At this time, since the bottom area, that is, the occupied area of the capacitor on the substrate is the same, the capacitance of the capacitor is changed with the occupied area being the same.

【0008】また、本発明の請求項2に係る半導体装置
は、基板上にキャパシタが形成された半導体装置であっ
て、前記キャパシタは、裁頭状の錐体形に形成され、前
記錐体形の中心部に前記基板と接触して形成される電極
用核と、前記錐体形の外周部に形成された電極用膜と、
前記電極用核及び電極用膜間に形成されこれら電極用核
及び電極用膜間を分離する絶縁膜と、の積層構造である
ことを特徴としている。
According to a second aspect of the present invention, there is provided a semiconductor device having a capacitor formed on a substrate, wherein the capacitor is formed in a truncated cone shape, and the center of the cone shape is formed. An electrode nucleus formed in contact with the substrate in the portion, an electrode film formed on the outer periphery of the cone,
It is characterized by having a laminated structure of an insulating film formed between the electrode nucleus and the electrode film and separating the electrode nucleus and the electrode film.

【0009】この請求項2の発明では、基板上に裁頭状
の錐体形のキャパシタが形成され、このキャパシタは、
裁頭上の錐体形の中央部に基板と接触して電極用核が形
成され、前記錐体形の外周部に電極用膜が形成され、こ
れら電極用核及び電極用膜間に、これらを分離するよう
に絶縁膜が形成される。
According to the second aspect of the present invention, a truncated cone-shaped capacitor is formed on a substrate.
An electrode nucleus is formed in contact with the substrate at the center of the cone on the frustum, an electrode film is formed on the outer periphery of the cone, and these are separated between the electrode nucleus and the electrode film. Thus, an insulating film is formed.

【0010】ここで、キャパシタの容量を変化させるに
は、絶縁膜の平面積を変化させればよく、この場合、裁
頭状の錐体形に成膜された絶縁膜の傾斜面の面積を変化
させればよい。このためには、傾斜面の傾きを変化させ
ればよいから、その底面積、つまり、基板上におけるキ
ャパシタの占有面積は同一のまま、容量を変化させるこ
とが可能となる。
Here, in order to change the capacitance of the capacitor, the plane area of the insulating film may be changed. In this case, the area of the inclined surface of the insulating film formed in the shape of a truncated cone is changed. It should be done. For this purpose, the inclination of the inclined surface may be changed, so that the capacitance can be changed while keeping the bottom area, that is, the area occupied by the capacitor on the substrate.

【0011】[0011]

【実施例】以下、本発明の実施の形態を実施例を伴って
説明する。まず、図1(a)に示すように、シリコン基
板1上に、膜厚Lの多結晶シリコン膜2を形成し、この
多結晶シリコン膜2の上にレジストを塗布し下部電極形
成用の直径Rの円形のレジストパターン3を形成する。
Embodiments of the present invention will be described below with reference to embodiments. First, as shown in FIG. 1A, a polycrystalline silicon film 2 having a film thickness L is formed on a silicon substrate 1, a resist is applied on the polycrystalline silicon film 2, and a diameter for forming a lower electrode is formed. An R circular resist pattern 3 is formed.

【0012】次に、図1(b)に示すように、レジスト
パターン3をマスクにして、多結晶シリコン膜2をテー
パーエッチングし、レジストパターン3の端部に相当す
る位置から離れるにしたがって、その膜厚が薄くなるよ
うにエッチングを行い、上面の直径がR,底面の直径が
L,高さがH,傾斜面の傾斜角がθである、円錐の上部
を切断した裁頭状の円錐形の下部電極(電極用核)2a
を形成する。このテーパエッチングは、例えば、SF6
/C2 HCl2 3 の混合ガスを、10〜19/51〜
60〔SCCM〕流し、10〔mTorr〕,RF電力
180〔W〕の条件で行う。
Next, as shown in FIG. 1B, using the resist pattern 3 as a mask, the polycrystalline silicon film 2 is taper-etched, and as the distance from the position corresponding to the end of the resist pattern 3 increases, Etching is performed so that the film thickness becomes thin, and the diameter of the upper surface is R, the diameter of the bottom surface is L, the height is H, and the inclination angle of the inclined surface is θ. Lower electrode (core for electrode) 2a
To form This taper etching is performed, for example, by using SF 6
/ C 2 HCl 2 F 3 mixed gas of 10-19 / 51-
This is performed under the conditions of 60 [SCCM] flow, 10 [mTorr], and RF power of 180 [W].

【0013】次に、レジストパターン3を除去し、図1
(c)に示すように、下部電極2aの表面全体、つま
り、上部平面と傾斜面全体とに、シリコン酸化膜(絶縁
膜)4を形成する。このシリコン酸化膜4は、例えば、
1050〔℃〕で15秒間、ドライO2 雰囲気中で酸化
を行うことにより、250〔Å〕成膜する。
Next, the resist pattern 3 is removed, and FIG.
As shown in (c), a silicon oxide film (insulating film) 4 is formed on the entire surface of the lower electrode 2a, that is, on the entire upper plane and the inclined surface. This silicon oxide film 4 is, for example,
Oxidation is performed in a dry O 2 atmosphere at 1050 ° C. for 15 seconds to form a film of 250 ° C.

【0014】さらに、このシリコン酸化膜4の表面全
体、つまり、上部平面と傾斜面全面とに、上部電極とし
ての多結晶シリコン膜(電極用膜)5を形成する。この
多結晶シリコン膜5は、例えば、モノシランの減圧CV
D法により、640〔℃〕,15〔Pa〕の条件下で3
500〔Å〕成膜する。
Further, a polycrystalline silicon film (electrode film) 5 as an upper electrode is formed on the entire surface of the silicon oxide film 4, that is, on the upper flat surface and the entire inclined surface. This polycrystalline silicon film 5 is formed by, for example, a decompression CV of monosilane.
According to Method D, under conditions of 640 ° C. and 15 Pa,
500 [500] is formed.

【0015】これにより、図1(c)に示すように、多
結晶シリコンからなる下部電極2a,シリコン酸化膜
4,上部電極としての多結晶シリコン膜5の積層構造が
形成され、これはすなわち、裁頭状の円錐形のキャパシ
タ10を構成している。
Thus, as shown in FIG. 1C, a laminated structure of the lower electrode 2a made of polycrystalline silicon, the silicon oxide film 4, and the polycrystalline silicon film 5 as the upper electrode is formed. A truncated conical capacitor 10 is formed.

【0016】ここで、図1(c)に示すキャパシタ10
において、その容量を大きくする場合には、後の下部電
極2aとなる多結晶シリコン膜2を形成するときに(図
1(a))、その膜厚H′をより厚くし(H′>H)、
円形のレジストパターン3の直径Rは同一にし、後の下
部電極2aとなる裁頭状の円錐形の底面積は一定となる
ように、つまり、底面の直径がLとなるように、テーパ
エッチングを行う。
Here, the capacitor 10 shown in FIG.
In the case where the capacitance is increased, when forming the polycrystalline silicon film 2 to be the lower electrode 2a later (FIG. 1A), the film thickness H 'is increased (H'> H). ),
Tapered etching is performed so that the diameter R of the circular resist pattern 3 is the same, and the bottom area of the frustoconical shape serving as the lower electrode 2a is constant, that is, the diameter of the bottom surface is L. Do.

【0017】そして、上記と同様にして、シリコン酸化
膜4及び多結晶シリコン膜5を形成する。これにより、
図2に示すように、上記と同様に、裁頭状の錐体形のキ
ャパシタ10′が形成されるが、このとき、下部電極2
a′は、図1(b)に示す下部電極2aに比較して、上
面の直径R及び底面の直径Lは同一であるが、高さH′
はより高く(H′>H)、傾斜面の傾斜角θ′がより大
きい(θ′>θ)裁頭状の錐体形となる。よって、この
下部電極2a′の表面に成膜したシリコン酸化膜4′の
表面積は、図1(c)のシリコン酸化膜4に比較して、
より大きくなり、つまり、容量がより大きくなるが、こ
のとき、下部電極2a′の底面の直径Rは同一に形成し
ているから、この下部電極2a′上に積層したシリコン
酸化膜4′及び多結晶シリコン膜5′を形成した後の半
導体基板1上における占有面積は同一のまま、より容量
の大きなキャパシタ10′が形成されたことになる。
Then, in the same manner as above, a silicon oxide film 4 and a polycrystalline silicon film 5 are formed. This allows
As shown in FIG. 2, a truncated cone-shaped capacitor 10 'is formed in the same manner as described above.
a ′ has the same top surface diameter R and bottom surface diameter L as compared to the lower electrode 2a shown in FIG.
Is higher (H ′> H), and the inclination angle θ ′ of the inclined surface is larger (θ ′> θ), resulting in a truncated cone. Therefore, the surface area of the silicon oxide film 4 'formed on the surface of the lower electrode 2a' is smaller than that of the silicon oxide film 4 shown in FIG.
The diameter R of the bottom surface of the lower electrode 2a 'is formed to be the same, so that the silicon oxide film 4' and the silicon oxide film 4 'laminated on the lower electrode 2a' This means that the capacitor 10 'having a larger capacitance has been formed with the same occupied area on the semiconductor substrate 1 after the formation of the crystalline silicon film 5'.

【0018】したがって、下部電極2aを形成する際
に、その形状を調整することによって、半導体基板1上
における占有面積は一定であるが、異なる容量のキャパ
シタ10を形成することができ、半導体装置の微細化,
高集積化を阻害することなく、容量の増加を図ることが
できる。
Therefore, when the lower electrode 2a is formed, by adjusting its shape, the occupied area on the semiconductor substrate 1 is constant, but the capacitors 10 having different capacities can be formed. Miniaturization,
The capacity can be increased without hindering high integration.

【0019】なお、上記実施の形態においては、後の下
部電極2aとなる多結晶シリコン膜2を形成する際に、
その膜厚を調整することにより、容量の増大を図るよう
にした場合について説明したが、例えば、円形のレジス
トパターン3の直径を調整し下部電極2aの傾斜面の傾
斜角θを変化させるようにしてもよく、この場合には、
キャパシタ10の高さを変化させることなく、容量の増
大を図ることができる。
In the above embodiment, when forming the polycrystalline silicon film 2 to be the lower electrode 2a later,
Although the case where the capacitance is increased by adjusting the film thickness has been described, for example, the diameter of the circular resist pattern 3 is adjusted to change the inclination angle θ of the inclined surface of the lower electrode 2a. In this case,
The capacitance can be increased without changing the height of the capacitor 10.

【0020】また、上記実施の形態においては、円形の
レジストパターン3を形成してテーパエッチングを行う
ことにより、裁頭状の円錐形の下部電極2aを形成する
ようにした場合について説明したが、例えば、図3に示
すように、四角形のレジストパターン3を形成してテー
パエッチングを行うことによって、裁頭状の四角錐形の
下部電極2aを形成するようにしてもよく、この場合に
も、裁頭状の四角錐形の傾斜面の傾斜角を変化させるこ
とによって、シリコン酸化膜4の表面積を変更させるこ
とができるから、上記と同等の作用効果を得ることがで
きる。また、裁頭状の四角錐形に限らず、多角形のレジ
ストパターン3を形成し、裁頭状の多角錐形を形成する
ようにしてもよく、この場合にも、上記と同等の作用効
果を得ることができる。
In the above embodiment, the case where the circular resist pattern 3 is formed and the tapered etching is performed to form the frustum-shaped conical lower electrode 2a has been described. For example, as shown in FIG. 3, by forming a rectangular resist pattern 3 and performing taper etching, a truncated quadrangular pyramid-shaped lower electrode 2a may be formed. Since the surface area of the silicon oxide film 4 can be changed by changing the inclination angle of the truncated quadrangular pyramid-shaped inclined surface, the same operation and effect as described above can be obtained. Further, the present invention is not limited to the truncated quadrangular pyramid, but may be formed by forming a polygonal resist pattern 3 to form a truncated polygonal pyramid. Can be obtained.

【0021】また、上記実施の形態においては、多結晶
シリコン膜とシリコン酸化膜と多結晶シリコン膜の三層
構造からなるキャパシタを形成した場合について説明し
たが、これに限らず、例えば金属と絶縁膜と金属との三
層構造からなるキャパシタを形成する場合でも適用する
ことができる。
In the above-described embodiment, the case where a capacitor having a three-layer structure of a polycrystalline silicon film, a silicon oxide film, and a polycrystalline silicon film is described. However, the present invention is not limited to this. The present invention can be applied to a case where a capacitor having a three-layer structure of a film and a metal is formed.

【0022】[0022]

【発明の効果】以上説明したように、本発明の請求項1
に係る半導体装置の製造方法によれば、電極形成用の膜
を形成した後、これを裁頭状の錐体形にエッチングして
電極用核を形成し、この電極用核の表面全体を覆うよう
に絶縁膜を形成し、さらに、絶縁膜の表面全体を覆うよ
うに電極用膜を形成するようにしたから、電極用核を形
成する際に、底面積はそのままで裁頭状の錐体形の傾斜
面の傾斜角度を調整することにより、この電極用核の上
に成膜される絶縁膜の表面積を変化させることができ、
基板上におけるキャパシタの占有面積は一定のままキャ
パシタの容量を変更することができる。
As described above, according to the first aspect of the present invention,
According to the method for manufacturing a semiconductor device according to the above, after forming a film for forming an electrode, the film is etched into a truncated cone shape to form a core for the electrode, and covers the entire surface of the core for the electrode. Since the electrode film is formed so as to cover the entire surface of the insulating film, when forming the electrode nucleus, the truncated cone-shaped cone is formed with the bottom area as it is. By adjusting the angle of inclination of the inclined surface, the surface area of the insulating film formed on the electrode core can be changed,
The capacitance of the capacitor can be changed while keeping the area occupied by the capacitor on the substrate constant.

【0023】また、本発明の請求項2に係る半導体装置
によれば、裁頭状の錐体形にキャパシタを形成し、この
キャパシタを、前記錐体形の中央部に電極用核,前記錐
体形の外周に電極用膜を形成し、これら電極用核及び電
極用膜間に、これら電極用核及び電極用膜を分離する絶
縁膜との積層構造で形成したから、このキャパシタの裁
頭状の錐体形の底面積は一定のまま傾斜面の傾斜角を変
化させることにより絶縁膜の面積を変化させることがで
き、よって、半導体基板上における占有面積を一定のま
ま容量を変化させることができる。
Further, according to the semiconductor device of the present invention, a capacitor is formed in a truncated cone shape, and this capacitor is provided at the center of the cone shape with an electrode core and the cone shape. An electrode film was formed on the outer periphery, and between the electrode nucleus and the electrode film, a laminated structure was formed with an insulating film separating the electrode nucleus and the electrode film. The area of the insulating film can be changed by changing the inclination angle of the inclined surface while keeping the bottom area of the body shape constant, so that the capacitance can be changed while keeping the occupied area on the semiconductor substrate constant.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体装置の製造工程の一部を示
す断面図である。
FIG. 1 is a cross-sectional view showing a part of a manufacturing process of a semiconductor device according to the present invention.

【図2】本発明の動作説明に供する説明図である。FIG. 2 is an explanatory diagram for explaining the operation of the present invention;

【図3】本発明のその他の一例を示す説明図である。FIG. 3 is an explanatory diagram showing another example of the present invention.

【図4】従来の半導体装置の製造工程の一部を示す断面
図である。
FIG. 4 is a cross-sectional view showing a part of a manufacturing process of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 多結晶シリコン膜 2a 下部電極 3 レジストパターン 4 シリコン酸化膜 5 多結晶シリコン膜 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Polycrystalline silicon film 2a Lower electrode 3 Resist pattern 4 Silicon oxide film 5 Polycrystalline silicon film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上にキャパシタが形成された半導体
装置の製造方法であって、前記基板上に電極形成用の膜
を形成した後、これをエッチングして裁頭状の錐体形の
電極用核を形成し、当該電極用核の表面全体を覆うよう
に絶縁膜を形成し、さらに、当該絶縁膜の表面全体を覆
うように電極用膜を形成することを特徴とする半導体装
置の製造方法。
1. A method of manufacturing a semiconductor device in which a capacitor is formed on a substrate, wherein a film for forming an electrode is formed on the substrate and then etched to form a frustum-shaped cone-shaped electrode. Forming a nucleus, forming an insulating film so as to cover the entire surface of the electrode nucleus, and further forming an electrode film so as to cover the entire surface of the insulating film. .
【請求項2】 基板上にキャパシタが形成された半導体
装置であって、前記キャパシタは、裁頭状の錐体形に形
成され、前記錐体形の中心部に前記基板と接触して形成
される電極用核と、前記錐体形の外周部に形成された電
極用膜と、前記電極用核及び電極用膜間に形成されこれ
ら電極用核及び電極用膜間を分離する絶縁膜と、の積層
構造であることを特徴とする半導体装置。
2. A semiconductor device having a capacitor formed on a substrate, wherein the capacitor is formed in a truncated cone shape, and an electrode is formed at the center of the cone shape in contact with the substrate. Laminated structure of a core for electrode, an electrode film formed on the outer periphery of the cone, and an insulating film formed between the electrode core and the electrode film and separating the electrode core and the electrode film. A semiconductor device, characterized in that:
JP6737298A 1998-03-17 1998-03-17 Manufacture of semiconductor device and semiconductor device using the method Withdrawn JPH11265978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6737298A JPH11265978A (en) 1998-03-17 1998-03-17 Manufacture of semiconductor device and semiconductor device using the method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6737298A JPH11265978A (en) 1998-03-17 1998-03-17 Manufacture of semiconductor device and semiconductor device using the method

Publications (1)

Publication Number Publication Date
JPH11265978A true JPH11265978A (en) 1999-09-28

Family

ID=13343128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6737298A Withdrawn JPH11265978A (en) 1998-03-17 1998-03-17 Manufacture of semiconductor device and semiconductor device using the method

Country Status (1)

Country Link
JP (1) JPH11265978A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100849791B1 (en) 2007-03-12 2008-07-31 삼성전기주식회사 Printed circuit board with embedded capacitor
CN111863778A (en) * 2019-04-30 2020-10-30 芯恩(青岛)集成电路有限公司 Quantum dot array capacitor and preparation method thereof
CN111969111A (en) * 2020-08-26 2020-11-20 上海华虹宏力半导体制造有限公司 Capacitor and manufacturing method thereof
CN113270547A (en) * 2021-05-19 2021-08-17 上海华虹宏力半导体制造有限公司 PIP capacitor and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100849791B1 (en) 2007-03-12 2008-07-31 삼성전기주식회사 Printed circuit board with embedded capacitor
CN111863778A (en) * 2019-04-30 2020-10-30 芯恩(青岛)集成电路有限公司 Quantum dot array capacitor and preparation method thereof
CN111863778B (en) * 2019-04-30 2022-03-01 芯恩(青岛)集成电路有限公司 Quantum dot array capacitor and preparation method thereof
CN111969111A (en) * 2020-08-26 2020-11-20 上海华虹宏力半导体制造有限公司 Capacitor and manufacturing method thereof
CN111969111B (en) * 2020-08-26 2023-04-18 上海华虹宏力半导体制造有限公司 Capacitor and manufacturing method thereof
CN113270547A (en) * 2021-05-19 2021-08-17 上海华虹宏力半导体制造有限公司 PIP capacitor and manufacturing method thereof

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