JPH11264856A - Terminal resistor circuit provided with resistor circuit for testing and testing method of the terminal resistor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a test efficient by impressing a high voltage or low voltage in a larger resistor circuit for testing in parallel to a terminal resistor circuit and outputting different voltages between normal and failure of operation of the terminal resistor circuit from the resistor circuit for testing. SOLUTION: When testing resistor circuits A1 and B3, switch circuit C2 of a testing circuit 7 is made on-off, the switch circuit D4 is made off-on and the swich circuit E6 is made on and low voltage and high voltage are impressed in the resistor circuit 5 for testing. At this moment, if the resistor circuit A1 and B3 are normally operated, test result output terminals respectively output a high voltage and a low voltage. If it does not operate normally and is in open state, the impressed voltage of the resistor circuit 5 for testing appears on the test results output terminal and outputs low voltage. In this manner, the operation of the resistor circuits A1 and B3 is normal or not can be easily tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a termination circuit having a test resistor circuit. The LSI circuit has a large number of terminals (L
A terminating resistor circuit is provided in the vicinity of the (SI pin), and impedance matching is performed when a signal is received from the outside.

[0002] The present invention relates to a terminating resistor circuit provided with a testing resistor circuit capable of efficiently testing the terminating resistor circuit and a method of testing the terminating resistor circuit.

[0003]

2. Description of the Related Art FIG. 7 is an explanatory view of a terminating resistor circuit.
This is a signal input / output circuit of an LSI pin. In FIG. 7, 5
Reference numeral 1 denotes a P-channel transistor having a low on-resistance of about 200Ω which is a terminating resistance.

Reference numeral 52 denotes an N-channel transistor,
It has a low on-resistance of about 200Ω which is a terminating resistance. Numeral 53 denotes a buffer, which is a tri-state buffer for outputting a signal to the outside.

[0005] Reference numeral 54 denotes a buffer for inputting an external signal. A control circuit 55 includes a P-channel transistor 51 and an N-channel transistor 52.
To generate a gate control signal.

Reference numeral 56 denotes an LSI pin. 57 is an internal circuit. In the configuration of FIG. 7, when a signal is input from input / output terminal 56, control circuit 55 generates a signal for turning on both P-channel transistor 51 and N-channel transistor 52. Then, for the input signal, the N-channel transistor becomes a termination resistance of 200Ω, and the input signal passes through the buffer 54 and is input into the LSI.

When outputting a signal from input / output terminal 56 to the outside, control circuit 55 generates a signal for turning off both P-channel transistor 51 and N-channel transistor 52. Then, the tristate buffer 53 is controlled to be active, and the signal of the internal circuit is output from the input / output terminal 56 via the tristate buffer 53.

Conventionally, the only way to determine whether the terminating resistor circuits (P-channel transistor 51, N-channel transistor 52) are normal or not is to test by directly contacting a probe to the terminating resistor circuit of the LSI chip. However, since the terminals are so fine that they cannot be touched by the test probe, a relatively large probe pad for testing is provided, and the test is performed by bringing the test probe into contact therewith. The probe pad is an interface of a test control circuit built in the chip, and a test voltage is applied to the probe pad from outside the chip via a test control circuit in the LSI to test the terminating resistor circuit.

[0009]

The conventional test of the terminating resistor circuit was inefficient because the test was conducted by directly contacting the test probe with the probe pad of the terminating resistor circuit.

An object of the present invention is to provide a terminal resistor circuit provided with a test resistor circuit and a test method of the terminal resistor circuit so that the terminal resistor circuit can be efficiently tested.

[0011]

According to the present invention, there is provided a terminal resistance circuit having a terminal resistance, a test resistance circuit having a test resistance larger than the terminal resistance added in parallel with the terminal resistance,
A control circuit that applies a high voltage (H) or a low voltage (L) to the test resistor circuit, and a test resistor circuit that outputs different voltages depending on whether the terminating resistor circuit is operating normally or has failed. And a test resistor circuit for outputting.

FIG. 1 shows the basic configuration of the present invention. In FIG. 1, reference numeral 1 denotes a resistance circuit A, which is a low resistance circuit of, for example, about 200Ω.

Reference numeral 2 denotes a switch circuit C, and a resistance circuit A
Switch circuit. Reference numeral 3 denotes a resistance circuit B, which is a low resistance circuit of, for example, about 200Ω. Reference numeral 4 denotes a switch circuit D, which is a switch circuit of the resistance circuit B.

Reference numeral 5 denotes a test resistance circuit which has a higher resistance than the resistance circuits A and B, for example, a high resistance of about 30 kΩ. Reference numeral 6 denotes a switch circuit E, which is a switch circuit for the test resistor circuit 5.

Reference numeral 7 denotes a control circuit for generating a control signal for each switch circuit and the like. 8 is an internal circuit. 9 is a signal input / output terminal.

A test result output terminal 10 outputs a test result. The operation of the configuration of FIG. 1 will be described. In the configuration of FIG. 1, when testing the terminating resistor circuit, the switch circuit E (6) is turned on. When a normal operation other than the test is performed, the switch circuit E (6) is turned off.

When testing the resistance circuit B (3), the control circuit 7 generates a signal for turning off the switch circuit C (2), turning on the switch circuit D (4), and turning on the switch circuit E (6). . Then, the control circuit 7 applies a high voltage (H) to the test resistor circuit 5 with the switch circuit C (2) turned off and the switch circuit D (4) turned on.

At this time, if the resistance circuit B (3) operates normally, the output of the test result output terminal becomes low voltage (L). Alternatively, if the resistance circuit B (3) does not operate normally and is in the open state, the output of the test result output terminal becomes the low voltage (L), as the voltage applied to the test resistance circuit 5 appears.

When testing the resistance circuit A (1), the control circuit 7 generates a signal that turns on the switch circuit C (2), turns off the switch circuit D (4), and turns on the switch circuit E (6). . Then, the control circuit 7 applies a low voltage (L) to the test resistor circuit 5 with the switch circuit C (2) turned on and the switch circuit D (4) turned off.

At this time, if the resistance circuit A (1) operates normally, the output of the test result output terminal becomes a high voltage (H). Alternatively, if the resistance circuit A (1) is not operating normally and is in an open state, the output of the test result output terminal becomes a low voltage (L) as the voltage applied to the test resistance circuit 5 appears.

As described above, it is possible to easily test whether the resistance circuits A (1) and B (3) are operating normally by measuring the voltage of the test result output terminal.

[0022]

FIG. 2 shows an example of a terminating resistor circuit according to the present invention, which is an embodiment of a terminating resistor circuit incorporating a terminating test circuit.

FIG. 2 shows a peripheral circuit of the input / output terminal of the LSI. In FIG. 2, reference numeral 21 denotes a control circuit which generates a control signal for a termination resistance circuit test according to the present invention, in addition to normal signal input / output control.

Reference numeral 22 denotes a buffer, which is a tri-state buffer. The buffer 23 outputs a signal from an internal circuit (not shown) of the LSI to the outside. When outputting a signal, the EN signal is set to L to activate the buffer 22. Otherwise, the EN signal is set to H and the buffer 22
Is disabled.

Reference numeral 23 denotes a buffer, and an input / output terminal 27
(LSI pins) are transmitted to an internal circuit (not shown). Reference numeral 24 denotes a P-channel transistor having a low on-resistance of about 200Ω.

25 is an N-channel transistor,
It has a low on-resistance of about 200Ω.
26 is a termination test circuit. It is composed of a tri-state buffer, and has a resistance circuit for testing on-resistance which is higher in resistance than the terminating resistance circuits (P-channel transistor 24 and N-channel transistor 25).

Reference numeral 27 denotes an input / output terminal, which is an LSI pin. The operation of FIG. 2 will be described later. FIG. 3 is a diagram showing an example of the termination test circuit of the present invention and its operation.

FIG. 3A shows an example of a termination test circuit, which is constituted by a tri-state buffer having a high-resistance test resistor circuit. In FIG. 3A, an AND circuit 31 receives the ROT and RT and generates a control signal for the P-channel transistor 33.

An OR circuit 32 receives the ROT and RT and generates a control signal for the N-channel transistor 33. 33 is a P-channel transistor.

Numeral 34 denotes an N-channel transistor,
It has a high ON resistance of about 30 kΩ.
FIG. 3B shows the operation of the circuit of FIG.

When ROT is L and ROT is H, the P-channel transistor is on and the N-channel transistor is off. When RT is L and ROT is L, the P-channel transistor is off and the N-channel transistor is on.

When RT is H and ROT is H, the P-channel transistor is on and the N-channel transistor is off. When RT is H and ROT is L, the P-channel transistor is off and the N-channel transistor is off.

In the test mode, RT is set to L and RO
T is set to H or L so that one of the P-channel transistor 33 and the N-channel transistor 34 is turned on and the other is turned off. In the normal operation mode, R
OT is set to H to turn off the N-channel transistor 34.

FIG. 4 shows an embodiment of the control circuit of the terminating resistor circuit according to the present invention. In FIG. 4, reference numeral 41 denotes a buffer, which is generated by a main control circuit (not shown).
Is input and EN is output.

Reference numeral 42 denotes a buffer which inputs the RT generated by the main control circuit and outputs the RT. Reference numeral 43 denotes an OR circuit for inputting RT and Q output from the BSC (the flip-flop 48 of the scan chain).

Reference numeral 44 denotes an AND circuit which inputs the output of the EN and the OR circuit 43 and outputs PS. 4
Reference numeral 5 denotes an AND circuit for inputting RT and Q.

Reference numeral 46 denotes an NS OR circuit, which inputs the output of the EN circuit and the AND circuit 45 and outputs NS. Reference numeral 48 denotes a flip-flop, which constitutes a scan chain of an LSI test circuit.

Reference numeral 49 denotes a buffer for inputting the OT and outputting the OT. Reference numeral 50 denotes a buffer for inputting IT and outputting IT. The operation of the configuration of FIGS. 2 and 4 will be described with reference to FIGS.

FIG. 5 is a time chart for testing the N-channel transistor of the terminating resistor circuit of the present invention. In the description of FIG. 5, reference is made to FIG. 2 and FIG. RT is L in the test mode. At this time, EN is set to H to disable the buffer 22 so that the test result output terminal is not output from the internal circuit. In FIG. 5, before time t1, Q, PS, NS, D, and SO may be different from the illustrated logical values.

In FIG. 4, the BSC outputs the current value of SI to Q and SO by the SCK clock, and outputs the current value of D to Q and SO by the CK clock. SCK at time t1
By the (scan clock), the Q output becomes L in accordance with the L of SI (SI is set to L as an initial value for starting the test). Since Q becomes L, PS becomes H, NS becomes H, and ROT becomes H.

At this time, if the P-channel transistor 24 and the N-channel transistor 25 of the termination resistance circuit operate normally, the P-channel transistor 24 is turned off and the N-channel transistor 25 is turned on. Further, although ROT is H, the D output becomes L because the N-channel transistor 25 is on. The value of D is input to D of the BSC 48, and the SO outputs the value L of D at that time and the Q outputs the value L of D at that time by the CK clock at time t2. Then, the scan chain output of the SO of the BSC of each terminating resistor circuit is performed by the continuous SCK clock after time t3. For example, if there are 1000, 1000 SC
A 1000 SO chain output is performed by the K clock.

At this time, if the N-channel transistor 25 of the termination resistance circuit does not operate normally and is open, the D output becomes H. Therefore, the value of D is BSC
48, and is inputted by the CK clock at time t2.
The outputs of SO and Q become H. Then, SO is output to the scan chain by the SCK clock after time t3.

As described above, the test of the N-channel transistor of the termination resistor circuit can be performed based on the output result of SO. Next, a test of the P-channel transistor of the termination resistor circuit will be described with reference to FIG.

FIG. 6 is a time chart for testing the P-channel transistor of the terminating resistor circuit of the present invention. In the description of FIG. 6, reference is made to FIG. 2 and FIG. Following the test of the N-channel transistor of the termination resistor circuit of FIG. 5, the test of the P-channel transistor is performed. Continuing with FIG. 5, RT is L and EN is H.

At S4 (scan clock) at time t4, H of SI appears as a Q output, and Q becomes H (SI is set to L as an initial value for starting a test). Since Q has become H, PS becomes L, NS becomes L, and ROT becomes L. In this state, if the P-channel transistor 24 and the N-channel transistor 25 of the termination resistance circuit operate normally, the P-channel transistor 24 is turned on and the N-channel transistor 25 is turned off. Further, although ROT is L, the D output becomes H because the P-channel transistor 24 is on. The value of D is input to D of the BSC 48, and the SO outputs the value H of D at that time and the Q outputs H by the CK clock at time t5. Then, the scan chain of the SO of the BSC of each terminating resistor circuit is output by the continuous SCK clock after time t6. Then, when the scan chains of all the BSCs are output, RT is turned on at time t7,
End the test.

At this time, if the P-channel transistor 24 of the terminating resistor circuit does not operate normally and is open, the D output becomes L. Then, it is input to D, and at time t4
CK clock, the output of SO becomes L, and the output of Q also becomes L. Then, the signal is output to the scan chain of the SO output of each BSC by the subsequent SCK clock. Then, when the scan chain outputs of all the BSCs are obtained, RT is set to H at time t7 to end the test.

[0047]

According to the present invention, the termination resistor circuit can be tested only by observing the output of the LSI pin without bringing the test probe into contact with the probe terminal of the bare chip. Therefore, the test of the terminating resistor circuit can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram illustrating an example of a termination resistor circuit according to the present invention.

FIG. 3 is a diagram illustrating an example of a termination test circuit according to the present invention.

FIG. 4 is a diagram showing an embodiment of a control circuit of the terminating resistor circuit of the present invention.

FIG. 5 is a diagram showing a time chart of an embodiment of the termination test circuit of the present invention.

FIG. 6 is a diagram showing a time chart of the embodiment of the termination test circuit of the present invention.

FIG. 7 is an explanatory diagram of a conventional termination resistor circuit.

[Explanation of symbols]

 1: Resistor circuit A 2: Switch circuit C 3: Resistor circuit B 4: Switch circuit D 5: Test resistor circuit 6: Switch circuit E 7: Control circuit 8: Internal circuit

Claims (4)

[Claims] 1. A terminating resistor circuit having a terminating resistor, a testing resistor circuit added in parallel to the terminating resistor and having a testing resistor greater than the terminating resistor, and a high voltage (H ) Or low voltage (L)
And a test resistor circuit that outputs different voltages depending on whether the terminating resistor circuit is operating normally or has failed. Terminating resistor circuit provided. 2. The terminating resistance circuit is a series connection circuit of a low resistance circuit A connected to a power supply side and a low resistance circuit B connected to a ground side, and the test resistance circuit is a high resistance circuit; In the test mode, when testing the low-resistance circuit B on the ground side, the control circuit turns on the low-resistance circuit B, turns off the low-resistance circuit A, applies a high voltage to the test resistance circuit, 2. The test resistance circuit according to claim 1, wherein when the resistance circuit A is tested, the low resistance circuit A is turned on, the low resistance circuit B is turned off, and a low voltage is applied to the test resistance circuit. Terminating resistor circuit. 3. A test resistance circuit having a test resistance higher than the terminal resistance is added in parallel to a terminal circuit having a terminal resistance, and a high voltage (H) or a low voltage (L) is controlled in the test resistance circuit. A method for testing a terminating resistor circuit, characterized by observing different output voltages when applied by a circuit and when the terminating resistor circuit output by the test resistor circuit is operating normally and when it is faulty. 4. The terminating resistance circuit is a series connection circuit of a low resistance circuit A connected to a power supply side and a low resistance circuit B connected to a ground side, and the test resistance circuit is a high resistance circuit. In the mode, when testing the low-resistance circuit B on the ground side, the control circuit turns on the low-resistance circuit B, turns off the low-resistance circuit A, applies a high voltage to the test resistance circuit, 4. The termination resistor according to claim 3, wherein when testing the resistance circuit A, the control circuit turns on the low resistance circuit A, turns off the low resistance circuit B, and applies a low voltage to the test resistance circuit. Circuit test method.