JP4043201B2 - Electronic circuit unit with test connector - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic circuit unit including a test connector having an integrated circuit to which a test method called a JTAG test can be applied.
[0002]
[Prior art]
The JTAG (Joint Test Action Group) test is one of the test methods standardized by IEEE in 1990, and scans all terminals of a highly integrated integrated circuit in order to input / output test data. This is a method for testing the internal function of an integrated circuit and the function of the entire electronic circuit unit configured by mounting it on a printed circuit board. Therefore, a dedicated circuit for testing is configured in the integrated circuit.
[0003]
FIG. 5 shows an electronic circuit unit provided with a conventional test connector corresponding to such a JTAG test, and its configuration and test method will be described.
[0004]
A highly integrated integrated circuit 32 corresponding to the JTAG test is mounted on the printed wiring board 31. The integrated circuit 32 includes an internal circuit 32a having its original function, a register 32b that is a dedicated circuit for performing a JTAG test, a controller 32c, and the like. The integrated circuit 32 has a general terminal (not shown) for connecting the internal circuit 32a to the surrounding circuits, and test terminals 32d through 32d for inputting / outputting test data and control signals to / from the register 32b and the controller 32c. 32h is provided.
[0005]
Further, a test connector 33 is provided on the printed wiring board 31. The test connector 33 is provided with a data input terminal 33a, a test mode terminal 33b, a clock terminal 33c, a reset terminal 33d, and a data output terminal 33e, which are connected corresponding to the test terminals 32d to 32h of the integrated circuit 32, respectively. The
[0006]
When testing the functions of the integrated circuit 32 and the electronic circuit unit as a whole, the test connector 33 is connected to a connector (not shown) of an external test apparatus, and test data is exchanged with the test apparatus. And the test is carried out. The test method is described below.
[0007]
First, a high level reset signal TRST is input to the reset terminal 33d from the test apparatus. Then, the controller 32c is initialized and can be tested. Subsequently, the controller 32c is switched to the designated test mode by the test mode signal TMS input to the test mode terminal 33b. Thereafter, test data TDI is input to the data input terminal 33a. The test data TDI is input to the internal circuit 32a via the register 32b. Thus, a function test of the internal circuit 32a is performed.
[0008]
The test data TDO after completion of the function test of the internal circuit 32a is output to the data output terminal 33e via the register 32b and further sent to an external test apparatus. Thereafter, the reset signal TRST becomes low level, and the test ends. The test apparatus analyzes the test result based on the sent test data TDO and determines whether the function is acceptable.
[0009]
[Problems to be solved by the invention]
In the above conventional configuration, when the connector is detached from the test apparatus during the test, the reset terminal 33d is in a state of floating from the reference potential point (ground). In this state, the reset terminal 33d becomes unstable, so there is no guarantee that a normal test will be performed, and therefore the reliability of the test result is lost.
[0010]
It is an object of the present invention to end a test so as to invalidate the previous test when the test connector is disconnected during the test.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, the present invention includes a printed wiring board, an integrated circuit capable of JTG testing mounted on the printed wiring board, and a test connector attached to the printed wiring board. The circuit has a controller for controlling the JTAG test, and the test connector is provided with at least a reset terminal for inputting a reset signal for resetting the controller prior to the JTAG test. Grounded by a pull-down resistor, a cascaded two-stage inverter is connected between the reset terminal and the controller, and an inverter to which a power supply voltage is supplied from the integrated circuit is inserted. An internal circuit having the output of the next stage from the input terminal of the first stage of the inverter Between the one point and the internal circuit between the up, the level of the reset signal is interposed a reset circuit for initializing the internal circuit which varies the high and low.
[0014]
The reset circuit has an exclusive OR circuit, and the reset signal is input directly to one input terminal of the exclusive OR circuit and input to the other input terminal via an integration circuit.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an electronic circuit unit provided with the test connector of the present invention will be described with reference to the drawings. 1 shows a configuration of the embodiment, FIG. 2 shows a specific circuit of the inverter in FIG. 1, FIG. 3 shows a specific circuit of the reset circuit in FIG. 1, and FIG. 4 shows an operation waveform diagram of the reset circuit.
[0016]
In FIG. 1, a highly integrated integrated circuit 2 for a modem corresponding to the JTAG test is mounted on a printed wiring board 1. The integrated circuit 2 includes an internal circuit 2a having a function of an original modem, a register 2b that is a dedicated circuit for performing a JTAG test, a controller 2c, and the like. The integrated circuit 2 is connected to a terminal 2i for resetting the internal circuit 2a, a general terminal (not shown) for connection to a circuit (not shown) around the integrated circuit 2, and a register 2b for testing. There are provided test terminals 2e to 2g to which data is inputted and outputted and connected to the controller 2c and the controller 2c to which a control signal and the like are inputted.
[0017]
Further, a test connector 3 is attached to the end of the printed wiring board 1. The test connector 3 includes a data input terminal 3a, a test mode terminal 3b, a clock terminal 3c, a reset terminal 3d, a data output terminal 3e, and the like. The data input terminal 3a is a test terminal 2d, and the test mode terminal 3b is a test mode terminal 3b. The clock terminal 3c is connected to the test terminal 2e and the test terminal 2f on the printed circuit board 1, respectively. The reset terminal 3d is grounded by a pull-down resistor 4 and is connected to the test terminal 2g through two cascaded inverters 5 and 6. As shown in FIG. 2, the inverters 5 and 6 have switch transistors 5a and 6a, respectively. A voltage is applied to the collectors of the switch transistors 5a and 6a via pull-up resistors 5b and 6b. The voltage is supplied from the power supply voltage supplied to the internal circuit 2a.
[0018]
Further, a reset circuit 7 is interposed between the output terminal of the second-stage inverter 6 and the reset terminal 2i of the internal circuit 2a. The reset circuit 7 is connected between the input terminal of the first stage inverter (that is, the reset terminal 3d of the connector 3) and the reset terminal 2i of the internal circuit 2a, or the output terminal of the first stage inverter 5 and the reset terminal 2i of the internal circuit 2a. You may insert between. As shown in FIG. 3, the reset circuit 7 includes an exclusive OR circuit 7a and an integration circuit 7b composed of a resistor and a capacitor. A reset signal is input directly from the inverter 6 to one input terminal, The input is input via an integration circuit 7b. Therefore, a reset signal shown in FIG. 4A is input to one input terminal, and an integrated B reset signal is input to the other input terminal. Then, a reset signal indicated by C is output. Accordingly, a reset signal is output every time the output of the inverter 6 changes to a high level and a low level.
[0019]
When testing the functions of the integrated circuit 2 and the electronic circuit unit as a whole, signals are exchanged with the test apparatus while the test connector 3 is connected to a connector (not shown) of an external test apparatus. A crack test is conducted. The test method is described below.
[0020]
First, a high level reset signal TRST is input to the reset terminal 3d from the test apparatus. Then, since the reset signal input to the controller 2c also goes high, the controller 2c is initialized. At the same time, another reset signal output from the reset circuit 7 is input to the internal circuit 2a, and the internal circuit 2a is initialized.
[0021]
Subsequently, the controller 2c switches to the designated test mode by the test mode signal TMS input to the test mode terminal 3b. Thereafter, test data TDI is input to the data input terminal 3a. Test data TDI is input to the internal circuit 2a via the register 2b. Thereby, a function test of the internal circuit 2a is performed. The entire electronic circuit unit is also tested.
In the case of performing a test with different contents, a different test mode signal is input to the test mode terminal 3b and the test is performed in the same manner.
[0022]
In the above configuration, when the test connector 3 is disconnected during the test, the reset terminal 3d becomes the reference potential point (low level) by the connected pull-down resistor 4 and therefore becomes low level without becoming unstable. At this point, the controller 2c ends the test state. Accordingly, erroneous test data is not output.
Further, since a voltage from the power supply voltage supplied to the integrated circuit 2a is applied to the inverters 5 and 6, a voltage higher than the power supply voltage is not applied to the test terminal 2g, and a high voltage is applied from the test apparatus. Even if the reset signal is input, the controller 2c is normally reset.
[0023]
The test data TDO after completion of the function test of the internal circuit 2a is output to the data output terminal 3e via the register 2b and further sent to an external test apparatus. Thereafter, the reset signal TRST becomes low level, and the test ends. At this time, the internal circuit 2a is also initialized by the reset signal output from the reset circuit 7. Therefore, the internal circuit 2a is initialized at the start of the test, and the integrated circuit 2 is in a state where normal operation is possible after the test is completed.
[0024]
【The invention's effect】
As described above, the present invention includes an integrated circuit capable of JTG testing mounted on a printed wiring board and a test connector attached to the printed wiring board, and the integrated circuit has a controller for controlling the JTAG test. The test connector is provided with at least a reset terminal from which a reset signal for resetting the controller prior to the JTAG test is input from the outside, the reset terminal is grounded by a pull-down resistor, and between the reset terminal and the controller. Is a cascaded two-stage inverter with an inverter supplied with power supply voltage from the integrated circuit, the integrated circuit having an internal circuit having the original function, and the input terminal of the first stage of the inverter Between any point from the output terminal of the next stage to the internal circuit and the internal circuit. Since the level of the reset signal is interposed a reset circuit for initializing the internal circuit which varies the high and low, if accidentally test connector is detached from the test device during the test, reset terminal connected Since the reference potential point (low level) is set by the pulled-down pull-down resistor, the level becomes low level without becoming unstable, and the controller ends the test state at that time. Accordingly, erroneous test data is not output. Furthermore, no voltage higher than the power supply voltage is applied to the controller, and the controller is normally reset even when a high voltage reset signal is input from the test apparatus. Furthermore, the internal circuit is initialized at the start of the test, and the integrated circuit is in a state where normal operation is possible after the end of the test.
[0027]
In addition, the reset circuit has an exclusive OR circuit, and the reset signal is input directly to one input terminal of the exclusive OR circuit and input to the other input terminal via an integration circuit, so the configuration is simple. The reset signal can be output at the start and end of the test.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an electronic circuit unit including a test connector of the present invention.
FIG. 2 is a circuit diagram of an inverter used in an electronic circuit unit provided with the test connector of the present invention.
FIG. 3 is a circuit diagram of a reset circuit used in an electronic circuit unit including the test connector of the present invention.
FIG. 4 is an operation waveform diagram of a reset circuit in an electronic circuit unit including the test connector of the present invention.
FIG. 5 is a configuration diagram of an electronic circuit unit including a conventional test connector.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Integrated circuit 2a Internal circuit 2b Register 2c Controller 2d, 2e, 2f, 2g, 2h, 2i Test terminal 3 Test connector 3a Data input terminal 3b Test mode terminal 3c Clock terminal 3d Reset terminal 3e Data output terminal 4 Pull-down resistor 5 Inverter 5a Switch transistor 5b Pull-up resistor 6 Inverter 6a Switch transistor 6b Pull-up resistor 7 Reset circuit 7a Exclusive OR circuit 7b Integration circuit

Claims (2)

A printed wiring board; an integrated circuit capable of JTAG testing mounted on the printed wiring board; and a test connector attached to the printed wiring board. The integrated circuit includes a controller for controlling the JTAG test. The test connector includes at least a reset terminal to which a reset signal for resetting the controller prior to the JTAG test is input from the outside, the reset terminal is grounded by a pull-down resistor, and the reset terminal and the controller And a cascaded two-stage inverter with an inverter supplied with a power supply voltage from the integrated circuit, the integrated circuit having an internal circuit having the original function, and the first stage of the inverter Any point between the input end of the output and the output end of the next stage Between the parts circuit, an electronic circuit having a test connector, characterized in that the level of the reset signal is interposed a reset circuit for initializing the internal circuit which varies the high and low unit.   The reset circuit has an exclusive OR circuit, and the reset signal is directly input to one input terminal of the exclusive OR circuit and input to the other input terminal via an integration circuit. An electronic circuit unit comprising the test connector according to claim 1.

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