JPH11262037A - System for displaying obp fault in package group - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly and precisely cope with when a fault has occurred by identifying the fault cause of OBP by means of the states of respective holding means for holding detecting means to detect the change points of output stop display signals by which respective on-board power sources OBP expresses change from a normality into an abnormality in accordance with respective packages. SOLUTION: A corresponding output stop detecting part 4-2 detects an output stop signal which is outputted by OBP 2-2 of the package 1-2, for example, after the occurrence of the fault and generates a detection output. The detection output is held by the corresponding holding part 5-2 and also an exclusive control part 6, to which the output is supplied inhibits the input of the output stop signal to the other output stop detecting parts. In addition, when all the OBP, are restored and the all the output stop to be signals input are gone, a restoration detecting circuit 7 resets all the holding parts 5-1 to 5-n. As a result, the respective holding parts specify OBP, where the fault has occurred and measures at the time of the fault occurs is easily and quickly executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an OBP (On-Board-P
The present invention relates to an OBP failure display method for an apparatus constituted by a plurality of packages equipped with an OBP.

An electronic circuit such as a control circuit of an exchange is called a plurality of packages (or PWCBs).
ircuit boards), and an OBP (power supply) is mounted on each PWCB of the group. In that configuration, all the PWCB group P
If the WCB is not installed, the OBP cannot start unless the OBP fails. Similarly, if a failure occurs in one of the PWCBs in the group, all the OBPs are activated.
The BP stops, and it becomes difficult to identify which OBP has a fault. Therefore, PWCB
When a group is composed of many PWCBs, it takes time to identify the OBP in which a failure has occurred, and improvement is desired.

[0003]

2. Description of the Related Art FIG. The conventional example 1 is an example of a centralized power supply system. 80 is a PWCB with a power supply, and 81 is each PWC with an electronic circuit.
B. PWCB80 is -48 by the internal power supply circuit.
A 5 V or 3.3 V voltage used in an electronic circuit is generated from a V input power supply, and is supplied to each of the plurality of PWCBs 82 as a power supply.

FIG. 6 is an explanatory diagram of the second conventional example. In the case of the centralized power supply system of the prior art example 1, the PWCB
Since it is necessary to supply a plurality of types of power supplies from the above, the conventional example 2 is improved. In the case of the second conventional example, the OBP is mounted on each of the PWCBs of the group in which the electronic circuits constituting the control unit and the like of the exchange are mounted. In this configuration, each PWCB that constitutes a group
As a condition for starting the OBP, there is provided a wiring to which a ground potential (ground) is supplied through a path that connects each PWCB in series in order. That is, each PWC in FIG.
B1 to B3 connect the ground potential G to the terminal P of the first PWCB1.
1 propagates to the terminal G2 of the next PWCB2 via the line of the wiring board, and further passes through the line of the wiring board to the next PWC.
It is supplied to the terminal G3 of B3. Thus, each PWCB1
OB are detected by detecting the ground potential.
P can be activated.

[0005]

In the above conventional configuration, the OBP cannot be started unless all PWCBs are mounted. This is a function for the purpose of protecting the signal transmission / reception circuit between the PWCBs if some power is not supplied in the PWCB group.

[0006] Similarly to this function, a failure of OBP or OBP
Even if the output of an OBP of a certain PWCB is stopped due to a load failure of the BP, all the OBs in the PWCB group are output.
It has a function to stop P. Further, as the function of the OBP, it cannot be determined whether the output has been stopped due to its own failure or the output has been stopped due to a stop request from the outside. Therefore, the OBP simply outputs an output stop display signal (PD: Power Down). . Actually, in terms of the system, the PD signal is periodically monitored by the firmware of another system of the PWCB provided in duplicate, and a failure process is performed when the PD signal is generated.

[0007] The OB of a PWCB in the PWCB group
When the output of P stops (OBP's own failure or output failure by the overload protection function due to a load failure), the PD signal is first output from the OBP of the PWCB in question, and then the OBP of all PWCBs To stop the output of all PWCBs, after a certain period of time elapses after a failure occurs,
The PD signal from P is output and the OBP of any PWCB
You will not know if a failure has occurred.

[0008] PD output of the first OBP and other PWCB
Since the time difference between the PD output from the OBP and the PBP is several hundred μs, it is necessary to perform periodic monitoring (the number of cycles m
In ms), it is difficult to specify the OBP that occurred first. If the number of PWCBs in the PWCB group is small or the PWCB can be easily replaced, there is no problem. However, if the number of PWCB groups is large or the replacement of the PWCB is not easy, it takes time to identify the failed PWCB. There was a problem of cost.

According to the present invention, there is provided an apparatus constituted by a plurality of PWCBs equipped with OBPs which can specify which OBP in a PWCB (package) group has a failure and can easily cope with the failure. It is an object of the present invention to provide an OBP failure indication method.

[0010]

FIG. 1 is a diagram showing the principle configuration of the present invention. In the figure, 1 is a package group, 1-
1-1-n are packages (PWCB), 2-1-2-n
Is an on-board power supply (OBP), 3 is an output stop monitoring circuit,
4-1 to 4-n are output stop detection units, 5-1 to 5-n are holding units for holding output stop detection outputs, 6 is an exclusive control unit, 7
Is a recovery detection circuit.

The internal circuits of the plurality of packages 1-1 to 1-n are respectively driven by board-mounted power supplies 2-1 to 2-n, and all of the board-mounted power supplies 2-1 to 2-n are connected in order. Thus, the power supply for each board is driven for the first time. When the drive is started and an output stop (PD) signal is generated due to a failure in one package, for example, the board mounted power supply 2-2 of the package 1-2, the signal is input to the output stop monitoring circuit 3 and the corresponding output stop is performed. The detection unit 4-2 generates a detection output. This detection output is held in the corresponding holding unit 5-2 and is supplied to the exclusive control unit 6. When one detection output is input, the exclusive control unit 6 detects an output that inhibits (suppresses) input of an output stop signal to each of the other output stop detection units 4-1 and 4-3 to 4-n. Supply to the department. As a result, only the output stop detecting unit 4-1 to which the output stop signal is input first generates an output, and only one corresponding holding unit 5-2 holds the output.

The output of each of the holding units 5-1 to 5-n is referred to as a status display signal for repairing a failure or the like, and it is possible to detect one board-mounted power supply whose output is stopped first. In addition, all output stop signals are input to the recovery detection circuit 7, and even if output stop occurs once, when all the on-board power supplies are recovered (recovered) thereafter, all output stop signals are lost (normal state). ) Is generated, and all the holding units 5-1 to 5-n are output by the output.
Reset.

[0013]

FIG. 2 shows the overall configuration of the embodiment.
In the figure, the same circuits as those in FIG.
1-6 are packages (PW
CB1 to PWCB6), 2-1 to 2-6 are OBPs (board power supplies) in each package, and 3 is an output stop (PD) monitoring circuit (or control circuit).

The terminals a and b of the packages 1-1 to 1-6 are connected in order, and the terminal a of the package 1 is connected to the ground (G), so that the packages are normally connected. Then, the ground potential is supplied to the terminals a and b of all the packages. This ground potential is connected to terminal b and terminal c in package 1-6,
It is returned to each terminal c of the packages 1-5 to 1-1 in order. Therefore, each OBP 2 of the packages 1-1 to 1-6 is
When the ground potential is supplied to -1 to 2-6, all the packages are normally connected, so that the OBP is driven. The terminal d of each package is opened if it is normal, and a ground potential is generated at the time of abnormality (alarm). When a ground potential is supplied to this terminal d, OB
P stops operation. Thus, each OBP2-1 to 2-
6 generates an output stop (PD) signal when the operation stops due to a failure or the like, respectively, and the output stop signal is supplied to the PD monitoring circuit 3.

FIG. 3 shows an internal configuration of the PD monitoring circuit 3, and FIG. 4 shows an example of operation waveforms of main circuits of the PD monitoring circuit. In FIG. 3, the same parts as those in FIG.
4-6 are output stop detecting units, 5-1-5-6 are holding units formed of flip-flop circuits, 6 'is a NOR circuit (indicated by NOR) corresponding to the exclusive control unit 6 in FIG. 7 '
Is an AND circuit corresponding to the recovery detection circuit of FIG. 1, and 8 is a display register in which the outputs of the holding units 5-1 to 5-6 and the output of the AND circuit 7 'are set.

FIG. 3 shows only the internal configuration of the output stop detecting section 4-1 as a representative, and the other output stop detecting sections 4-2 to 4-
6 has the same configuration, and the internal configuration is not shown. 4
Two flip-flop circuits (represented by FF1 to FF4)
And an OR circuit 1 (represented by OR1) and an AND circuit 1 (AN
D1) and an inverter (INV). The output of the OR circuit 1 (OR1) is supplied to the data input terminal D of the flip-flop circuit (FF1), and the OR circuit 1 (O1)
One input of R1) is OBP2-1 of package 1-1.
, And a mask PD (displayed by MPD) signal is input to the other input.
The output stop signal PD1 is set to the ground potential at the time of abnormality,
Power supply Vcc is input via pull-up resistor R because it is open during normal operation. The signal of the mask PD (MPD) is a mask signal for preventing the corresponding output stop detection unit from performing a detection operation as abnormal when a configuration in which some packages in the package group are not mounted is adopted. (“L” level in this example) is input.
Each of the flip-flop circuits FF1 to FF4 has 16M
Hz clock signal (Clock) is applied to a clock terminal (c).
k) to be driven.

The holding units 5-1 to 5-6 are respectively
A flip-flop circuit 5 (represented by FF5) with a reset terminal (represented by RST) and an AND circuit 2 (represented by AND2) are provided. One input of an AND circuit 2 (AND2) is supplied with a signal of a power supply (Vcc) level via a pull-up resistor, and the other is supplied with an output of a NOR circuit 6 and a PD.
In the initial state where no signal is detected, each of the holding units 5-1 to 5-
6 receives “0” (low level) from the terminal Q of each flip-flop circuit 5 (FF5), so that the NOR circuit 6 outputs “1” (high level).

The AND circuit 7 'receives the outputs of the terminals Q of the flip-flop circuits 3 (FF3) of all the output stop detecting units 4-1 to 4-6, and outputs the outputs of the terminals Q of all the FF3 to "1". "" (All PD signals are in a normal state), "1" is generated, and the flip-flop circuits 5 (FF5) of the holding units 5-1 to 5-6 are reset. Further, the output of the AND circuit 7 'is supplied to the display register 8 and displayed on behalf of the state of the output stop detecting units 4-1 to 4-6 ("0" in the case of even one output stop state, If normal, "1" is displayed).

The operation waveforms shown in FIG. 4 include a case where a PD (output stop) signal changes from a normal state to a state indicating an abnormality (low level to a high level) with respect to a clock signal, and The waveforms of the respective parts from to for a subsequent change from abnormal to normal (change from high level to low level) are shown.

Is a terminal Q of the flip-flop circuit FF1.
, The output of the terminal Q of the flip-flop circuit FF2, the output of the terminal QN (the opposite polarity to the terminal Q) of the flip-flop circuit FF3, and the output of AND (AND1). Further, indicates the output of the AND circuit (AND2) of the holding units 5-1 to 5-6, indicates the output of the flip-flop circuit 5 (FF5) constituting the holding unit, and indicates the output of the NOR circuit 6.

The operation of the configuration shown in FIG. 3 will be described with reference to an example of operation waveforms shown in FIG. In this description, it is assumed that the PD1 signal is input to the output stop detection unit 4-1 in FIG. When the PD signal shown in FIG. 4 changes from a normal state to an abnormal state (change from a low level to a high level), it is input to an output stop detection unit (4-1 in FIG. 3), and the OR circuit 1
It is set to the flip-flop circuit 1 (FF1) in synchronization with the clock via (OR1) (FIG. 4). The terminal Q of the flip-flop circuit 1 (FF1)
Is set to the flip-flop circuit 2 (FF2) by the next clock input (FIG. 4). The output is further transmitted to the flip-flop circuit 3 (FF3) by the next clock to set it to the set state. On the other hand, the output terminal Q of the flip-flop circuit 3 (FF3)
N generates the waveform shown in FIG.
From (AND1), a high-level output as shown in FIG. 4 is generated. When this output is generated, a signal output from the inverter (INV) indicating the falling of the clock (FIG. 4)
Is supplied to the clock terminal of the flip-flop circuit 4 (FF4), so that the flip-flop circuit 4 (FF4) is set in synchronization with this.

The output of the output terminal QN of the flip-flop circuit 4 (FF4) is supplied to the clock terminal of the flip-flop circuit 5 (FF5) constituting the holding unit 5-1. At this time, the AND circuit 2 (AND2) Noah circuit 6 to
Since the output from the NOR circuit (NOR) is at a high level (FIG. 4), a pulse-like output is generated from the AND circuit 2 (AND2) (FIG. 4), and the flip-flop circuit 5 (FF)
5) is input to the data terminal and set, and the output terminal Q
, A high level output is generated as shown in FIG.
When this signal is input, the output of the NOR circuit (NOR) becomes low level as shown in FIG. The low level signal of the NOR circuit (NOR) is supplied to the other holding units 5-2.
To the respective AND circuits 2 (AND2) to 5-6, and the respective flip-flop circuits 5 (FF5)
Is set as a set.

The holding state of each of the holding units 5-1 to 5-6 and the state of the AND circuit 7 'are set in a display register 8, and the contents thereof are read by a processing unit (not shown) and displayed to a maintenance person by a display unit or the like. Is displayed, the package in which the failure has occurred can be identified, so that the package in which the failure has occurred can be identified. Thus, when the faulty package is repaired by replacing it with a normal one, the PD signal returns from the abnormal state to the normal state. As a result, each of the flip-flop circuits 1 to 4 (F
F1 to FF4) are sequentially reset (FF in FIG. 4).
1, the waveforms up to the timing when the FF2 is reset are shown in FIG. Thereby, the flip-flop circuit 3
When (FF3) is reset, the inputs of the AND circuit 7 'all go high, and the outputs of all the
-1 to 5-6 and supplied to each flip-flop circuit 5
(FF5) is reset. As a result, the NOR circuit 6 outputs a low level (“0”), and the holding units 5-1 to 5
The prohibition of the AND circuit 2 (AND2) of -6 is released.

[0024]

According to the present invention, a package including an OBP is provided.
Since it is possible to specify and hold which OBP in the group has a failure, it is possible to quickly and accurately cope with the failure. In addition, when the stop of the output from the package is released in the state display of the OBP output stop, it is automatically cleared and the state can be accurately displayed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram illustrating an overall configuration of an embodiment.

FIG. 3 is a diagram showing an internal configuration of a PD monitoring circuit 3.

FIG. 4 is a diagram showing an example of operation waveforms of main circuits of the PD monitoring circuit.

FIG. 5 is an explanatory diagram of Conventional Example 1.

FIG. 6 is an explanatory diagram of Conventional Example 2.

[Explanation of symbols]

 1 Package Group 1-1 to 1-n Package (PWCB) 2-1 to 2-n Board-mounted Power Supply (OBP) 3 Output Stop Monitoring Circuit 4-1 to 4-n Output Stop Detector 5-1 to 5-n Holding unit 6 Exclusive control unit 7 Recovery detection circuit

Claims (4)

[Claims] An OB having an output stop display function.
A group is composed of multiple packages with P
In an OBP failure display method of a package group having a configuration in which output of one OBP in a group is stopped by stopping output of one OBP, each OBP indicates a change from normal to abnormal corresponding to each package. A package, comprising: detecting means for detecting a change point of an output stop display signal; and holding means for holding the output of each of the detecting means, wherein the state of the holding means makes it possible to identify the cause of the OBP failure. A group OBP failure display method. 2. The method according to claim 1, wherein when each of the holding means holds a change point detection output from a normal state to an abnormal state, another OB is output.
An OBP failure display method for a package group, comprising means for prohibiting holding of a change detection output from normal to abnormal from P. 3. The OB according to claim 1, wherein
Recovery means for receiving the output of each holding means corresponding to P and detecting that all the holding means have generated a signal indicating normality, and resetting all the holding means by the output of the recovery detection means; An OBP failure display method for a package group. 4. The apparatus according to claim 1, wherein when a part of the packages in the package group is not arranged, a mask signal is supplied to the detecting means provided corresponding to the package. An OBP failure display method for a package group.