JPH11261552A - Clock switch device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To comply with a network fitted to the network construction oven a wide range rather than a mesh network by comparing respective pieces of received clock priority information and respective pieces of clock repeating stage number information based on a clock priority setting value and an outer clock input monitoring signal and mediating them. SOLUTION: A repeater means 15 updates clock priority information to the highest value in a clock priority setting value and first to n-th reception clock priority information, updates and repeats clock repeating stage number information to a value becoming a master node when the clock priority setting value is the highest and to a value obtained by increasing the number of reception clock repeating stages by only one when it is low so as to execute repeating. When the clock priority setting value of a self-station is the highest and an outer clock is not inputted, a mediation means 11 selects the clock in a self-node and selects an outer clock when the outer clock is inputted. When clock priority from the respective transmission lines is similar, information on the number of clock repeater stages is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock switching device, and more particularly to a clock switching device for determining a clock source in a device at each communication node forming a network employing a network synchronization system. is there.

[0002]

2. Description of the Related Art A network adopting a subordinate synchronization system based on a network synchronization system is composed of one master node and a plurality of other slave nodes, and the master node is supplied with a clock generated by its own node or externally. A clock is transmitted to the transmission line, and each slave node establishes clock synchronization within the network or with an external network by subordinately synchronizing with the clock extracted from the transmission line, and then normal data is transmitted at each communication node. Transmission and reception.

FIG. 13 is a diagram showing the principle configuration of a clock switching device according to the prior art. In the figure, the clock switching device includes a unit 31 for separating clock priority information received from a first transmission line, a unit 32 for extracting a clock from the first transmission line, and a clock priority received from a second transmission line. A means 33 for separating information, a means 34 for extracting a clock from the second transmission path, a means 35 for monitoring an external clock input, and a means 36 for presetting the priority for becoming a master node as a clock priority. It has.

[0004] This clock switching device further comprises means 36
, The external clock input monitoring signal output from the external clock input monitoring means 35 and the first and second received clock priority information respectively supplied from the separating means 31 and 32 are compared. A means 37 for performing arbitration is provided.

[0005] The arbitration means 37, when [clock priority setting value> first and second reception clock priority],
Arbitration is performed so that the internal clock of the own node (or the external clock if an external clock is input) is used as the internal clock source, and [clock priority setting value <first reception clock priority> second reception clock priority ], The first transmission line clock is set, and if [clock priority setting value <first reception clock priority <second reception clock priority], the second transmission line clock is set to [clock priority]. Degree setting value <first reception clock priority = second reception clock priority>
Means for arbitrating the first transmission line clock or the second transmission line clock as the internal clock source;

The clock switching device further includes a means 38 for generating a clock in the own node, and first and second transmission line clocks, an external clock, and a clock generation means extracted by the clock extraction means 32 and 34, respectively. Means 39 for selecting any of the internal clocks generated at 38 based on the arbitration result of the adjusting means 37; and generating an internal clock from the clock selected by the means 39 as a source. Means 40.

The clock switching device further comprises a clock priority information relay means 41, which relay means 41 sets the clock priority set value set by the setting means 36 and the first and second clock priority information separated by the separation means 31 and 33, respectively. Second
Of the received clock priority information is updated to the highest priority value, and the sequence number indicating the validity of the clock priority information is rewritten (if the clock priority setting value is the highest, it is rewritten. Relay each time). In this case, the same clock priority is relayed to the output side transmission line.

The relay means 41 is connected to the first and second transmission path clock priority information multiplexing means 42 and 43. The multiplexing means 42 multiplexes the clock priority information on the first transmission path output. Then, the clock priority information is multiplexed on the second transmission path output. The multiplexing operation in this case is performed based on the internal clock from the internal clock generation means 40.

With such a configuration, the node having the highest priority is configured as a master node and the other nodes are configured as slave nodes in accordance with the clock priority assigned to each communication node. Even when various failures such as disconnection and transmission path disconnection occur, network synchronization is always established by automatically switching the master node and automatically switching the subordinate system in the slave node.

[0010]

However, in such a conventional clock switching device, the means for monitoring the detachment of the master node (monitoring the sequence number) and the means for selecting the subordinate system in the slave node are networked. This is achieved by limiting the configuration to a duplex ring (first and second transmission paths), wherein the transmission path connected to each communication node is a multi-route of two or more paths, and furthermore, the input / output of the transmission path It was not possible to cope with a network configuration configured in a mesh shape in which the system was not fixed.

Therefore, the present invention employs a slave synchronization method in which one master node and a plurality of slave nodes are arranged in a mesh, and each slave node sequentially synchronizes with the clock of the master node via a transmission line. In the clock switching device provided at each node in the network,
An in-device clock that can be adapted to a network form other than a duplex ring, particularly a network suitable for constructing a wider network such as a mesh network, that is, a communication node having two or more transmission paths to connect. It is an object to provide a source clock switching device.

[0012]

FIG. 1 shows in principle the configuration of a clock switching apparatus according to the present invention for achieving the above object. The clock priority information and the clock priority information received from each transmission line are shown in FIG. Means for separating received clock priority information from the first transmission line input, means for separating received clock relay number information from the first transmission line input, Means 5 for separating received clock priority information from the input, means 6 for separating received clock relay stage number information from the nth transmission path input,
It has.

Although the first to n-th parts are omitted for simplification of the drawing, they are provided with the same separating means as described above. As means for extracting a clock received from each transmission path, means 4 for extracting a clock from the first transmission path input, and means 8 for extracting a clock from the n-th transmission path input
And

Further, a means 9 for monitoring an external clock input, a means 10 for presetting a priority for becoming a master node as a clock priority, a clock priority set value, an external clock input monitoring signal and a first Reception clock priority information, first reception clock relay stage number information,
Means 11 for comparing each of the n-th received clock priority and the n-th received clock relay stage information and performing arbitration as shown in FIG. 2; means 12 for generating a clock in the own node; Means 13 for selecting any one of a first transmission line clock, an n-th transmission line clock, an external clock, and a clock in the own node based on the output of the clock 11; And means 14 for generating.

Further, the clock switching device includes a relay unit 15. The relay unit 15 includes a clock priority setting value, a first reception clock priority information, and an n-th reception clock for the clock priority information. The priority information is updated to the highest value, and the clock relay stage number information is set to a value that becomes the master node when the clock priority setting value is the highest, and to a value obtained by incrementing the received clock relay stage information by one when the clock priority setting value is low. Update and relay. The relay means 15 includes a means 16 for multiplexing the clock priority information and the clock relay stage number information on the first transmission path output,
It is connected to a unit 17 for multiplexing the clock priority information and the clock relay stage number information to the transmission path output. These multiplexing units 16 and 17 perform a multiplexing operation based on the internal clock. The same clock priority information and clock relay stage number information are separately received.

That is, according to the present invention, the arbitration means 11
As shown in the clock switching arbitration principle diagram (1) of FIG. 2, when the clock priority setting value of the own station is the highest and there is no external clock input, the clock in the own node is selected (Claim 2, 4) If there is an external clock input, the external clock is selected (items 1 and 3). Furthermore, when there is no external clock input and the clock priority set value of the own station is low, the clock priority from the transmission line is considered and the clock of the transmission line with the highest priority is selected (sections 5 and 6).

In the above, when the clock priority from each transmission path is the same, the clock cannot be selected.
Therefore, in such a case, the information of the number of clock relay stages is further used to select the transmission line clock with the smallest number of clock relay stages (items 7 and 8).

By providing an upper limit value for the number of relay stages in this way, it is possible to detect the separation of the master node, and if the clock priority information has the same value in a plurality of routes, the separation means In consideration of the additional information on the number of clock relay stages obtained from 2, 6 and 6, based on the information on the number of clock relay stages, a route having the least number of relay nodes in each section between the master node and the slave node is determined. It acts so as to select, and it is possible to select a route with less clock jitter generated by relaying the communication node.

In the present invention, as means for separating the reception counter clock priority information from each transmission path input, means 3 for separating reception counter clock priority information from the first transmission path input as shown in FIG. Means 7 for separating the reception counter clock priority information from the nth transmission path input.

Then, in this case, the arbitration means 11
The arbitration as shown in FIG. 3 is performed by adding the opposite clock priority information and the n-th opposite clock priority information. Also,
Accordingly, the multiplexing unit 16 multiplexes and outputs the clock priority set value as it is to the transmission counter priority information on the first transmission line output, and the multiplexing unit 17 outputs the clock priority set value on the n-th transmission line output. It is multiplexed and output as it is as transmission priority information.

That is, in the arbitration principle of FIG. 2, when the number of clock relay stages from each transmission line becomes the same (item 9), the first or n-th transmission line clock is selected in the illustrated example. , Either can not be determined.

Therefore, in the selection of the subordinate system in the slave node, if the clock priority information and the clock relay stage number information have the same value in a plurality of routes, the clock switching arbitration principle (2) in FIG. As shown, by taking into account the opposing priority information, it works to select the route with the highest clock priority setting value in the adjacent communication node, and reconstructs the network, performs maintenance, or generates a fault. In some cases, it is possible to reduce the number of clock switching state transition steps.

[0023]

FIG. 4 shows an embodiment of each communication node applied to the clock switching device according to the present invention. In the network of this embodiment, a plurality of these communication nodes are connected in a mesh by two to four transmission lines, and data between the communication nodes is transmitted in a frame having an overhead shown in FIG. ing.

This communication node includes a 1-system transmission line interface unit 21, a 2-system transmission line interface unit 22, a 3-system transmission line interface unit 23, a 4-system transmission line interface unit 24, a clock generation unit 25, and a clock arbitration unit 26.
It is composed of

The 1-system transmission line interface unit 21 connects the 1-system transmission line with the communication node, detects frame synchronization and extracts the transmission line clock for the received data frame input from the 1-system transmission line, and Multiplexes and separates overhead (including clock relay stage number information and opposite clock priority information) for data frames.

The second transmission line interface unit 22 connects the second transmission line to the communication node, detects the frame synchronization and extracts the transmission line clock of the received data frame input from the second transmission line, Multiplexes and separates overhead (including clock relay stage number information and opposite clock priority information) for data frames.

The third transmission line interface unit 23 connects the third transmission line to the communication node, detects frame synchronization and extracts the transmission line clock of the received data frame input from the transmission line, (Including clock relay stage number information and counter clock priority information).

The fourth-system transmission line interface unit 24 connects the fourth-system transmission line to the communication node, detects the frame synchronization and extracts the transmission line clock of the received data frame input from the transmission line, (Including clock relay stage number information and counter clock priority information).

The interface units 21 to 2
4 corresponds to the means 1 to 8, 16 and 17 shown in FIG.

The clock arbitration unit 25 corresponds to the means 10, 11, 15 shown in FIG. 1, and the register 251 indicates the priority (clock priority) for the communication node to become the master node by the clock priority number. In the arbitration circuit 252, the clock priority number in the self-node which configures the clock priority number as a lower value, the external clock valid signal (disconnection detection signal) as a higher value, and reception overhead from each transmission path Free-run (PLO free-running) clock, external clock, 1 based on information and synchronization detection signal
Arbitration for selecting any one of the system transmission line clock, the system two transmission line clock, the system three transmission line clock, and the system four transmission line clock as a clock source in the apparatus, and overhead according to the arbitration result Relay information.

The clock generator 26 corresponds to the means 9, 12 to 14 shown in FIG.
At 261, any one of an external clock, a system 1 transmission line clock, a system 2 transmission line clock, a system 3 transmission line clock, and a system 4 transmission line clock, based on the in-device clock source switching signal from the clock arbitration unit 25. Select one clock,
After being converted to the PLO reference frequency by the frequency dividing circuit 262, the PL
Input to O263. The PLO 263 generates the internal clock by subordinate to the reference clock or by self-running. Further, the presence / absence of a clock is monitored by the external clock disconnection detection circuit 264 to generate an external clock valid signal.

FIG. 5 is a diagram showing an overhead area transmitted between communication nodes. The overhead area includes three areas a to c, where area a is clock priority information, area b is clock relay stage number information, and area c indicates opposing clock priority information. The clock priority information of the area a is compared with the information received from each transmission line and the clock priority information in the own node, and the higher priority value is written and relayed.

The information on the number of clock relay stages in the area b is information for incrementing the value every time the slave node is relayed starting from the master node. An upper limit is set on the value, and the received clock priority exceeds the upper limit. If so, the clock priority information received at the same time is regarded as invalid. As the counter clock priority information of the area c, the clock priority information in the own node is directly written and relayed. When each piece of information is received, it is considered valid only when the frame synchronization signal is normal.

As shown in FIG. 6, the internal clock source options of the communication node include a free-running clock (own node), a system 1 transmission line clock, a system 2 transmission line clock, and a system 3 transmission line clock. It can be represented as six state transitions of the four-system transmission line clock and the external clock.

As shown in FIG. 7 below, ● 1 system frame synchronization detection signal ● 2 system frame synchronization detection signal ● 3 system frame synchronization detection signal ● 4 system frame synchronization detection signal Arbitration is performed by giving 18 parameters, and among the six states shown in FIG. , The state of the free-running clock and the external clock indicate that the communication node operates as a master node, and the states of the 1st system transmission line clock to the 4th system transmission line clock indicate that the communication node operates as a slave node. .

The operation of such an embodiment is described by assuming that in the configuration example where nine communication nodes A to I are connected, the clock priority numbers are changed from node A to B to C to D to E to F to G to H to I.
Clock switching operation when sequentially assigned to
One case will be described below with reference to FIGS.

Case in which all nodes are normal (FIG. 8) In this case, first, although node A has two transmission lines of the first system and the second system, since no external clock is input, the node A 251 has the highest clock priority and is the master node of the free-run clock. Also, since the number of clock relay stages is “0”,
Clock information "1-0-1" to which the opposite clock priority "1" as seen from the adjacent nodes B and D is added to the overhead by the multiplexing unit of the 1-system and 2-system transmission line interface units 21 and 22 so as to be adjacent. Send to nodes B and D.

At the node B, since the clock priority is "1", the arbitration circuit 252 controls the selector 261 to select the third-system transmission line connected to the master node A (<> for the selected transmission line). At the same time, the multiplexing unit as the relay means 15 in the node B commonly increments the number of clock relay stages by “1” for the 1st to 3rd transmission lines and generates clock information having the opposite clock priority “2”. "1-1-2" is transmitted. In this case, the clock information “1-1-3” is similarly transmitted to the node D except for the opposite clock priority.

At the node E, the clock information from the node B is "1-1-2" and the clock information from the node D is "1-1-3". It is not possible to determine which should be selected only by the number of stages b. Therefore, by taking into account the opposite clock priority as described above, the opposite clock priority from the node B is “2” and that from the node D is “3”, so that the clock from the node B has priority. And the system 1 transmission line is selected instead of the system 4 transmission line.

By applying such an operation to each node, the clock of the node A is applied to all the other nodes B to I.
Is provided in the form of a blind by the route of the selected transmission line indicated by <>.

In the case where a single failure has occurred in the transmission line (FIG. 9), in this case, the node B indicates that the third transmission line is in a failure (indicated by a cross) state.
, The clock of the master node A cannot be directly input. This is the same for the node E to which the clock is input from the node B.

Therefore, first, it is optimal to input the clock from the node D, not the node B, but from the node D this time through the four-system transmission line. The node B selects either the clock from the node C connected to the first transmission line or the clock from the node E connected to the second transmission line.

In this case, since the node E is clearly farther from the master node A than the node C, the number of clock relay stages in the node clock information is also reduced, and as a result, the system 2 transmission line is selected. Finally, in the case of this example, the selection of the transmission line clock of only the nodes E, B and F differs from the example of FIG.

A case where a double fault has occurred in the transmission line (FIG. 1)
0) In this case, in addition to the failure of FIG. 9, a failure state has occurred between the nodes D and G. However, from the example of FIG. 9, only the node D interferes with the clock selection. It turns out that it is. In addition, since the node G can input the clock only from the node H, the two-system transmission line on the node H side is selected as shown in the figure.

A case where a master node failure has occurred (FIG. 1)
1) In this case, since the clock of the node A in each of the above examples cannot be used, the node B having the next lowest clock priority setting value becomes the master node in the free-run state, and this master node A transmission line clock is selected from B in the same manner as described above. The difference from the example of FIG. 8 is that the node D selects the system 2 transmission line and selects the clock from the node E.

The external clock supplied to the master node
In this case, the node A cannot function as a master node because the clock loss detection circuit 264 detects an external clock loss state. Then, the node I to which the external clock is normally input is now the master node, and the clock is supplied in the opposite direction from that in FIG.

[0047]

As described above, according to the clock switching apparatus according to the present invention, the clock priority indicated by the overhead is the highest among the clocks extracted from the transmission line and the clocks generated by the own node at each node. A high clock is selected as a clock source in the device, and clock relay stage number information indicating the number of nodes relayed from the master node and preferably counterclock priority are added to the overhead, and the clock relay stage number information and the counterclock priority are added. Since the clock priority is positioned as lower-order information of the clock priority information and the clock is selected, the number of transmission paths connected to the communication nodes is not limited, and the mesh network as well as the dual ring network is used. Is also adaptable, so that the industrial use range is expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle configuration of a clock switching device according to the present invention.

FIG. 2 is a principle diagram (1) of clock switching arbitration by the clock switching device according to the present invention.

FIG. 3 is a principle diagram (2) of clock switching arbitration by the clock switching device according to the present invention.

FIG. 4 is a block diagram showing an embodiment configuration of each communication node in the clock switching device according to the present invention.

FIG. 5 is a configuration diagram of an overhead area in the embodiment of the present invention.

FIG. 6 is a clock switching state transition diagram in the embodiment of the present invention.

FIG. 7 is a diagram showing a clock switching arbitration embodiment according to the embodiment of the present invention.

FIG. 8 is a network diagram showing a clock selection state when all communication nodes are normal.

FIG. 9 is a network diagram illustrating a clock selection state when a single failure occurs in a transmission line.

FIG. 10 is a network diagram illustrating a clock selection state when a double fault occurs in a transmission line.

FIG. 11 is a network diagram showing a clock selection state when a master node has left a transmission line due to a failure.

FIG. 12 is a network diagram showing a clock selection state when a failure occurs in an external clock supplied to a master node.

FIG. 13 is a block diagram showing a principle configuration of a clock switching device according to a conventional technique.

[Explanation of symbols]

 1,5 Clock priority information separating means 2,6 Clock relay stage number information separating means 3,7 Counter clock priority information separating means 4,8 Clock extracting means 9 External clock input monitoring means 10 Clock priority setting means 11 Arbitration means 12 Clock generating means 13 Clock selecting means 14 In-device clock generating means 15 Relay means 16, 17 Multiplexing means 21-24 Transmission line interface unit 25 Clock arbitration unit 26 Clock generation unit In the drawings, the same reference numerals indicate the same or corresponding parts.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hidetoshi Amari 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Naoki Sase 3--22, Hakata-ekimae, Hakata-ku, Fukuoka-shi, Fukuoka No. 8 Inside Fujitsu Kyushu Digital Technology Co., Ltd. (72) Inventor Go Tsuyoshi Matsumoto 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (2)

[Claims] 1. A network in which a master node and a plurality of slave nodes are arranged in a mesh form, and each slave node employs a subordinate synchronization method in which each slave node sequentially synchronizes with a clock of the master node via a transmission line. In the clock switching device provided in the node, means for separating clock priority information and clock relay stage number information received from each transmission path, means for extracting a clock received from each transmission path, and monitoring an external clock input Means for preliminarily setting a priority order to become a master node as a clock priority; and, based on the clock priority set value and an external clock input monitoring signal, the received clock priority information and the clocks. Means for arbitrating by comparing the relay stage number information with each other, means for generating a clock in the own node, Means for selecting any one of the received clock, the external clock, and the internal clock according to the output of the arbitration means; means for generating an internal clock based on the selected clock; output of the arbitration means According to the clock priority information,
The received clock priority information and the clock priority setting value are updated to the highest priority value, and the clock relay stage number information is updated so that the clock priority setting value is the highest priority value. If the value is not the highest priority value, the received clock relay stage number information is updated to a value that is incremented by one, and the value is relayed to each transmission path. Means for multiplexing the clock priority information and the clock relay stage number information in a communication frame to each transmission path based on the internal clock. 2. The arbitration element according to claim 1, further comprising: means for separating opposing clock priority information received from each transmission path, wherein said arbitration means adds the received opposing clock priority information to each other as an arbitration element. And arbitrates the clock selecting means and the relay means, and the multiplexing means
A clock switching apparatus characterized in that a clock priority set value is multiplexed as it is as transmission opposite priority information in a communication frame of each transmission path as it is.