JPH11261112A - Led assembly - Google Patents
Led assemblyInfo
- Publication number
- JPH11261112A JPH11261112A JP813999A JP813999A JPH11261112A JP H11261112 A JPH11261112 A JP H11261112A JP 813999 A JP813999 A JP 813999A JP 813999 A JP813999 A JP 813999A JP H11261112 A JPH11261112 A JP H11261112A
- Authority
- JP
- Japan
- Prior art keywords
- led
- die
- epoxy
- layer
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/56—Materials, e.g. epoxy or silicone resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/641—Heat extraction or cooling elements characterized by the materials
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、発光ダイオードに
関し、より詳細には、発光ダイオードのダイ（die）の
パッケージング（ packaging）に関する。FIELD OF THE INVENTION The present invention relates to light emitting diodes and, more particularly, to the packaging of a light emitting diode die.
【０００２】[0002]
【従来の技術】現在の高輝度の発光ダイオード（ light
emitting diode,ＬＥＤ）は、可視スペクトルの範囲全
体にわたる光を放出し、その効率は現存する光源と同等
またはそれを上回っている。これら高輝度のＬＥＤは本
来、固体であるため、その信頼性は白熱および蛍光照明
技術と比較するとかなり改善されている。商業用ＬＥＤ
は、１００，０００時間を超過して連続で動作した場
合、出力の低下が最初の値の５０％未満であると推定さ
れている。加えて、故障する前にＬＥＤの取替え予防保
全日にユーザがＬＥＤを取替えることによって、突発的
な故障の発生率が大幅に減少している。2. Description of the Related Art Current high brightness light emitting diodes (light)
An emitting diode (LED) emits light over the entire range of the visible spectrum, and its efficiency is equal to or better than existing light sources. Because these high-brightness LEDs are inherently solid, their reliability is significantly improved when compared to incandescent and fluorescent lighting technologies. Commercial LED
Has been estimated to have less than 50% of its initial value when operating continuously for more than 100,000 hours. In addition, the rate at which catastrophic failures occur is greatly reduced by the user replacing the LEDs on a preventive maintenance date for LED replacement before failure.
【０００３】[0003]
【発明が解決しようとする課題】青紫から緑までのスペ
クトル範囲の光を放出する高輝度のＬＥＤは、ＡｌＩｎ
ＧａＮ材料系を使用して開発されている。これら発光器
の市場における用途は、劣化の性能（ performance）に
極めて敏感であり、したがってＬＥＤの劣化は、高輝度
のＬＥＤの開発を成功させるための重要なパラメータの
一つとなる。現在の商業用のＡｌＩｎＧａＮを用いたＬ
ＥＤ（以後、「ＡｌＩｎＧａＮ・ＬＥＤ」という。）は
過大な劣化レベルを有し、ＬＥＤを備えた装置の有効な
寿命が高輝度の青色ＬＥＤランプのパッケージの場合、
約３５００時間であることがわかっている。このような
信頼性低下の原因は、一部は、放出光の内部吸収により
ＬＥＤの光出力が減少するダイ取付け用エポキシ（ die
-attach epoxy ）の劣化によるものである。A high-brightness LED that emits light in the spectral range from violet to green is known as AlIn.
Developed using GaN material system. The market applications of these light emitters are very sensitive to degradation performance, and thus LED degradation is one of the key parameters for successful development of high brightness LEDs. L using current commercial AlInGaN
ED (hereinafter referred to as “AlInGaN LED”) has an excessive degradation level, and the effective life of the device including the LED is high in the case of a blue LED lamp package.
It has been found to be about 3500 hours. The cause of such a decrease in reliability is, in part, due to the die-attach epoxy, which reduces the light output of the LED due to internal absorption of the emitted light.
-attach epoxy).
【０００４】図５は、発光ダイオードを示す図である。
図５に示すように、現在の商業用の高輝度のＡｌＩｎＧ
ａＮ・ＬＥＤはすべて、透明な、電気絶縁性のサファイ
ア基板を使用して生産されている。ＬＥＤ構造のエピタ
キシァル（ epitaxial）成長のために基板にサファイア
を選択するのは、主に二つの理由による。第１に、サフ
ァイアは、熱的および化学的に強く、エピタキシャル成
長中に生ずる高温に耐えることができると共に、成長に
使用するアンモニア・ガスの腐食環境にも耐えることが
できる。第２に、サファイアは、青紫から緑までのスペ
クトル範囲の光に対して透明であり、このため透明基板
のＬＥＤの成長が可能であり、高効率のＬＥＤの製造が
可能になる。FIG. 5 is a diagram showing a light emitting diode.
As shown in FIG. 5, current commercial high brightness AlInG
All aN LEDs are produced using transparent, electrically insulating sapphire substrates. The choice of sapphire for the substrate for epitaxial growth of the LED structure is mainly for two reasons. First, sapphire is thermally and chemically strong and can withstand the high temperatures that occur during epitaxial growth, as well as withstand the corrosive environment of the ammonia gas used for growth. Second, sapphire is transparent to light in the blue-violet to green spectral range, which allows for the growth of LEDs on transparent substrates and allows for the production of highly efficient LEDs.
【０００５】図６は、従来のパッケージに取付けられた
発光ダイオードを示しており、ＬＥＤチップを普通のＬ
ＥＤランプのパッケージに取付けるプロセスを示してい
る。ＡｌＩｎＧａＮ・ＬＥＤのダイは、ダイ取付け用の
材料を用いて金属のリードフレーム（ leadframe）に物
理的に接続される。ダイ取付け用の材料は普通、エポキ
シ樹脂であり、透明であるか、または電気を伝導し且つ
熱伝導性を向上させる高密度の金属のフレーク（ flak
e）で充填されている。ＬＥＤのダイおよびリードフレ
ームは次に、構造を完全にし、光学的な性能を向上さ
せ、ＬＥＤのダイを周囲環境からシールするために、透
明な剛い材料の中に入れられる。このようなＡｌＩｎＧ
ａＮ・ＬＥＤのダイを備えた構成では、透明なダイ取付
け用エポキシは、普通、ＬＥＤランプの全光出力を極大
にするために使用される。ＬＥＤランプのパッケージに
は、図６に示したパッケージとは異なる多数のパッケー
ジの形式が存在する。それらのパッケージの形式には、
限定されないが、ＬＥＤのダイがセラミック基板または
プリント回路基板に直接取付けられるものもある。ＬＥ
Ｄチップのパッケージに取付ける同様なプロセスが、Ｌ
ＥＤチップをリードフレームまたは基板に取付けるため
に使用される。FIG. 6 shows a light emitting diode mounted in a conventional package, in which an LED chip is connected to a conventional L.
Fig. 4 shows a process of mounting the ED lamp on a package. The AlInGaN LED die is physically connected to a metal leadframe using die attach materials. The material for the die attach is usually an epoxy resin and is either transparent or a dense metal flake that conducts electricity and improves thermal conductivity.
e) is filled. The LED die and leadframe are then encased in a clear, rigid material to complete the structure, improve optical performance, and seal the LED die from the surrounding environment. Such AlInG
In configurations with an aN LED die, a transparent die attach epoxy is commonly used to maximize the total light output of the LED lamp. There are many types of LED lamp packages different from the package shown in FIG. The format of those packages is
In some cases, but not limited to, the LED die is mounted directly on a ceramic or printed circuit board. LE
A similar process for mounting on a D-chip package is
Used to attach ED chips to lead frames or substrates.
【０００６】本発明は、ＬＥＤのダイを金属のリードフ
レームに取付けるために使用されるダイ取付け用エポキ
シの材料の劣化を減少させることにより、ＬＥＤランプ
のパッケージにおける信頼性を改善するＬＥＤ組立品を
提供することを目的とする。The present invention provides an LED assembly that improves the reliability of the LED lamp package by reducing the degradation of the die attach epoxy material used to attach the LED die to the metal lead frame. The purpose is to provide.
【０００７】[0007]
【課題を解決するための手段】不透明材料がＬＥＤのダ
イの透明基板とダイ取付け用エポキシとの間に挿入さ
れ、ＬＥＤの動作中におけるダイ取付け用の材料による
光吸収の増大に関連したＬＥＤの劣化を減少させてい
る。不透明層の使用により熱抵抗を減らす金属が充填し
たダイ取付け用の材料の使用が可能になるが、光の吸収
は増大する。また、ＬＥＤのダイとダイ取付け用エポキ
シとの間に挿入される不透明層として金属を使用するこ
とにより、ＬＥＤランプの全体としての熱抵抗を更に減
らすことができる。熱抵抗が高くなるとＬＥＤランプの
パッケージの動作温度が高くなる。ＬＥＤの動作温度が
増大するにつれてＬＥＤの光出力が減少し、ＬＥＤの劣
化の割合が増大する。ＬＥＤチップから放出される光に
対する反射率を高くするように不透明金属層を選択すれ
ば、ＬＥＤランプのパッケージの全光出力を向上させる
ことができる。透明基板と不透明層との間に任意の薄い
障壁層を挿入して接着を促進することができる。SUMMARY OF THE INVENTION An opaque material is interposed between the transparent substrate of the LED die and the die attach epoxy to enhance the light absorption of the LED associated with the die attach material during operation of the LED. Deterioration is reduced. The use of an opaque layer allows the use of metal-filled die attach materials that reduce thermal resistance, but increases light absorption. Also, by using metal as the opaque layer inserted between the LED die and the die attach epoxy, the overall thermal resistance of the LED lamp can be further reduced. The higher the thermal resistance, the higher the operating temperature of the LED lamp package. As the operating temperature of the LED increases, the light output of the LED decreases and the rate of degradation of the LED increases. If the opaque metal layer is selected so as to increase the reflectance for light emitted from the LED chip, the total light output of the LED lamp package can be improved. An optional thin barrier layer can be inserted between the transparent substrate and the opaque layer to promote adhesion.
【０００８】[0008]
【発明の実施の形態】本発明は、ＡｌＩｎＧａＮ材料系
から作られるＬＥＤランプのパッケージにおける信頼性
を、ＬＥＤのダイを金属のリードフレームに取付けるた
めに使用されるエポキシ系（ epoxy system ）、すなわ
ち、ダイ取付け用エポキシの材料の劣化問題を処理する
ことにより改善することができる。図１は、本発明の一
実施形態の発光ダイオードを示している。任意の障壁層
１０を基板１２（たとえば、サファイア）の裏面に直接
堆積させ、続いて厚い不透明層１４を堆積させる。ＬＥ
Ｄのダイ１６をダイ取付け用エポキシ２０により金属の
リードフレーム１８に取付ける。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the reliability of an LED lamp package made from the AlInGaN material system, and to the reliability of the epoxy system used to attach the LED die to the metal lead frame. This can be improved by addressing the degradation problem of the die attach epoxy material. FIG. 1 shows a light emitting diode according to one embodiment of the present invention. An optional barrier layer 10 is deposited directly on the backside of the substrate 12 (eg, sapphire), followed by a thick opaque layer 14. LE
The die 16 of D is mounted on the metal lead frame 18 by the die mounting epoxy 20.
【０００９】不透明材料の障壁層１０および不透明層１
４がＬＥＤのダイ１６とダイ取付け用エポキシ２０との
間に挟まれている。不透明材料の障壁層１０および不透
明層１４は、ＬＥＤの動作中においてダイ取付け用の材
料による光吸収の増大に関連するダイ取付け用エポキシ
の劣化を極小にする障壁として動作する。Opaque material barrier layer 10 and opaque layer 1
4 is sandwiched between the LED die 16 and the die attach epoxy 20. Opaque material barrier layer 10 and opaque layer 14 act as barriers to minimize degradation of the die attach epoxy associated with increased light absorption by the die attach material during LED operation.
【００１０】金属で充填したダイ取付け用エポキシ２０
を使用し、不透明層１４として金属を使用することによ
り、ＬＥＤのダイおよびパッケージの全体としての熱抵
抗を減らすことができる。また、ＬＥＤチップから放出
される光に対して高い反射率を有する不透明層１４を選
択することにより、ＬＥＤランプのパッケージの全体と
しての光出力を、更に向上させることができる。図２
は、サファイア基板に堆積した１００ｎｍの厚さを有す
る様々な金属層の反射率に対する波長（色）を示すグラ
フである。多数の金属が高い反射率を有するが、好適な
実施形態では、青紫から緑までのスペクトル範囲にある
光に対して最大の反射率を備えている銀またはアルミニ
ウム層を使用している。不透明金属層の厚さの下限は、
ダイ取付け用の材料内に伝えられる光の割合によって決
まる。反射光の割合は、１から吸収され透過した光の割
合を差し引くことにより決定される。図３は、サファイ
ア基板に堆積した波長４７０ｎｍにおける様々な金属層
の厚さに対する反射率を示すグラフである。最大の反射
率を有する二つの金属、すなわち、銀およびアルミニウ
ムについては、厚さの下限は、光の半分が減衰する厚さ
を示す約２０ｎｍのところである。Die mounting epoxy 20 filled with metal
And using metal as the opaque layer 14 can reduce the overall thermal resistance of the LED die and package. Further, by selecting the opaque layer 14 having a high reflectivity for light emitted from the LED chip, the light output of the LED package as a whole can be further improved. FIG.
Is a graph showing wavelength (color) versus reflectance for various metal layers having a thickness of 100 nm deposited on a sapphire substrate. Although many metals have high reflectivity, the preferred embodiment uses a silver or aluminum layer that has the highest reflectivity for light in the blue-violet to green spectral range. The lower limit of the thickness of the opaque metal layer is
Determined by the percentage of light transmitted into the die attach material. The ratio of reflected light is determined by subtracting the ratio of absorbed and transmitted light from one. FIG. 3 is a graph showing the reflectivity for various metal layer thicknesses at a wavelength of 470 nm deposited on a sapphire substrate. For the two metals with the highest reflectivity, silver and aluminum, the lower thickness limit is about 20 nm, which is the thickness at which half of the light is attenuated.
【００１１】しかしながら、サファイアのようなセラミ
ック材料の表面に直接堆積した金属を使用した場合、し
ばしは接着の問題が生じる。透明基板への不透明層の接
着は、ダイの取付けおよびワイヤ接続（ wire bonding
）のような製造工程で問題になる。ダイを取付ける工
程では、ＬＥＤチップは粘着テープから外され、ダイ取
付け用エポキシによってリードフレームに取付けられ
る。ワイヤ接続の工程では、電気接続がＬＥＤチップに
対して行なわれる。したがって、不透明層の材料は、ダ
イ取付けおよびワイヤ接続の工程中に材料を透明基板に
残留させる接着性を備えていなければならない。加え
て、透明基板への不透明層の接着は、ＬＥＤのダイとパ
ッケージとの間の熱膨張係数の差が故障に至る応力の原
因となる可能性があるため、ＬＥＤの信頼性にとって重
要である。However, the use of metal deposited directly on the surface of a ceramic material such as sapphire often causes adhesion problems. Adhesion of the opaque layer to the transparent substrate is achieved by attaching the die and wire bonding.
) Is a problem in the manufacturing process. In the step of attaching the die, the LED chip is detached from the adhesive tape and attached to the lead frame by die attaching epoxy. In the step of wire connection, electrical connection is made to the LED chip. Therefore, the material of the opaque layer must have an adhesive property that allows the material to remain on the transparent substrate during the die attach and wire connection steps. In addition, adhesion of the opaque layer to the transparent substrate is important for LED reliability as differences in the coefficient of thermal expansion between the LED die and the package can cause stress leading to failure. .
【００１２】この問題に対する一つの解法手段は、任意
の障壁層、すなわち第２の材料の薄い層を透明基板と不
透明金属層との間に挿入して接着を促進することであ
る。この障壁層の材料は、放出光の吸収を極小にするよ
うに選定される。最適な候補としては、チタンまたは窒
化チタン、およびアルミニウムがある。障壁層の厚さ
は、不透明層の全体としての反射率を減らすことなく接
着が最適になるように選定される。厚さの下限は、接着
の特性により決まり、１原子層（ atomic layer ）、ま
たは約０．３ｎｍ程に薄くすることができる。One solution to this problem is to insert an optional barrier layer, a thin layer of a second material, between the transparent substrate and the opaque metal layer to promote adhesion. The material of this barrier layer is chosen to minimize absorption of the emitted light. The best candidates include titanium or titanium nitride, and aluminum. The thickness of the barrier layer is selected so that adhesion is optimal without reducing the overall reflectivity of the opaque layer. The lower limit of the thickness is determined by the properties of the bond and can be as thin as one atomic layer or about 0.3 nm.
【００１３】図４（Ａ）および（Ｂ）は、適切な接着を
維持しながら不透明層の反射率を最適にする別の解決手
段のパターンを示している。図４（Ａ）は、接着層を部
分的に覆う層のパターンの一例を示し、図４（Ｂ）は、
図４（Ａ）に示したパターンを取り入れた概略断面図を
示したものである。接着に対して最適化される層は、低
い反射率を有する材料の部分的な被覆、および最大の反
射率を有する材料の部分的な被覆を生ずるようにパター
ン化される。このようなプロセスを発展させることによ
り適切な接着を有し極大の反射率を得ることができる。FIGS. 4A and 4B illustrate another solution pattern for optimizing the reflectivity of the opaque layer while maintaining proper adhesion. FIG. 4A shows an example of a pattern of a layer partially covering the adhesive layer, and FIG.
FIG. 5 is a schematic cross-sectional view incorporating the pattern shown in FIG. The layer that is optimized for adhesion is patterned to produce a partial coverage of the material with low reflectivity and a partial coverage of the material with maximum reflectivity. By developing such a process, it is possible to obtain a maximum reflectance with proper adhesion.
【００１４】本発明を、リードフレームに関して説明し
たが、他のパッケージング技術、たとえば、セラミック
基板、またはプリント回路基板に拡張できる。当業者
は、組立品を仕上げる前にそれによりパッケージが劣化
する原因を減らすＬＥＤを製作することになる。Although the invention has been described with reference to a lead frame, it can be extended to other packaging techniques, for example, ceramic substrates or printed circuit boards. Those skilled in the art will produce LEDs prior to finishing the assembly thereby reducing the causes of package degradation.
【００１５】以下に本発明の実施の形態を要約する。The embodiments of the present invention will be summarized below.
【００１６】１．透明基板（１２）を有する発光ダイオ
ード（ＬＥＤ）（１６）と、前記透明基板上の不透明層
（１４）と、前記不透明層上のダイ取付け用エポキシ
（２０）の層と、前記ダイ取付け用エポキシの層に取付
けられたリードフレームと、を備え、前記不透明層が前
記ダイ取付け用エポキシの劣化を減少させるように動作
するＬＥＤ組立品。1. A light emitting diode (LED) (16) having a transparent substrate (12), an opaque layer (14) on the transparent substrate, a layer of die attach epoxy (20) on the opaque layer, and the die attach epoxy And a lead frame attached to the die assembly, wherein the opaque layer operates to reduce degradation of the die attach epoxy.
【００１７】２．前記ダイ取付け用エポキシは、当該Ｌ
ＥＤ組立品の熱抵抗を減少させるように動作する金属が
充填したエポキシである上記１に記載のＬＥＤ組立品。2. The die-attaching epoxy is the L
The LED assembly of claim 1, wherein the LED assembly is a metal-filled epoxy that operates to reduce the thermal resistance of the ED assembly.
【００１８】３．前記不透明層は金属である上記２に記
載のＬＥＤ組立品。3. The LED assembly of claim 2, wherein the opaque layer is metal.
【００１９】４．前記金属は、前記ＬＥＤのダイから放
出される光の波長に対して最大の反射率を有するように
選択される上記３に記載のＬＥＤ組立品。4. 4. The LED assembly of claim 3, wherein the metal is selected to have a maximum reflectivity for a wavelength of light emitted from the LED die.
【００２０】５．前記金属は、銀、銀合金、アルミニウ
ム、およびアルミニウム合金を含むグループから選択さ
れる上記４に記載のＬＥＤ組立品。[5] 5. The LED assembly of claim 4, wherein said metal is selected from the group comprising silver, silver alloys, aluminum, and aluminum alloys.
【００２１】６．前記透明基板と前記金属層との間に挿
入された障壁層（１０）を備え、この障壁層が前記透明
基板を部分的に覆って前記透明基板への前記金属の接着
を向上させた上記４に記載のＬＥＤ組立品。6. A barrier layer (10) interposed between said transparent substrate and said metal layer, said barrier layer partially covering said transparent substrate to improve the adhesion of said metal to said transparent substrate. An LED assembly according to item 1.
【００２２】７．前記障壁層（１０）は、接着を最適化
するよう選択される上記６に記載のＬＥＤ組立品。7. 7. The LED assembly according to claim 6, wherein said barrier layer (10) is selected to optimize adhesion.
【００２３】８．前記障壁層（１０）は金属である上記
７に記載のＬＥＤ組立品。8. The LED assembly according to claim 7, wherein said barrier layer (10) is metal.
【００２４】９．前記障壁層（１０）は、反射率を最適
化するよう選択される上記８に記載のＬＥＤ組立品。9. The LED assembly of claim 8, wherein the barrier layer (10) is selected to optimize reflectivity.
【００２５】１０．前記障壁層（１０）は、チタン、窒
化チタン、およびアルミニウムを含むグループから選択
される上記７に記載のＬＥＤ組立品。10. The LED assembly according to claim 7, wherein said barrier layer (10) is selected from the group comprising titanium, titanium nitride, and aluminum.
【００２６】[0026]
【発明の効果】本発明によれば、ＬＥＤのダイを金属の
リードフレームに取付けるために使用されるダイ取付け
用エポキシの材料の劣化を減少させることにより、ＬＥ
Ｄランプのパッケージにおける信頼性を改善することが
できる。In accordance with the present invention, LE is reduced by reducing the degradation of the die attach epoxy material used to attach the LED die to the metal lead frame.
The reliability in the package of the D lamp can be improved.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の一実施形態の発光ダイオードを示す図
である。FIG. 1 is a diagram showing a light emitting diode according to one embodiment of the present invention.
【図２】サファイア基板に堆積した１００ｎｍの厚さを
有する様々な金属層の反射率に対する波長（色）を示す
グラフである。FIG. 2 is a graph showing wavelength (color) versus reflectance for various metal layers having a thickness of 100 nm deposited on a sapphire substrate.
【図３】サファイア基板に堆積した波長４７０ｎｍにお
ける様々な金属層の厚さに対する反射率を示すグラフで
ある。FIG. 3 is a graph showing the reflectance for various metal layer thicknesses at a wavelength of 470 nm deposited on a sapphire substrate.
【図４】適切な接着を維持しながら不透明層の反射率を
最適にする別の解決手段のパターンを示す図である。FIG. 4 illustrates another solution pattern that optimizes the reflectivity of the opaque layer while maintaining proper adhesion.
【図５】発光ダイオードを示す図である。FIG. 5 is a diagram showing a light emitting diode.
【図６】従来のパッケージに取付けられた発光ダイオー
ドを示す図である。FIG. 6 is a view showing a light emitting diode mounted on a conventional package.
１０ 障壁層 １２ 基板 １４ 不透明層 １６ ＬＥＤのダイ ２０ ダイ取付け用エポキシ DESCRIPTION OF SYMBOLS 10 Barrier layer 12 Substrate 14 Opaque layer 16 LED die 20 Die mounting epoxy
フロントページの続き (72)発明者 ポール・エス・マーティン アメリカ合衆国 カリフォルニア，プレザ ントン，フェアオークス・ドライブ 7665 (72)発明者 サージ・エル・ルダツ アメリカ合衆国 カリフォルニア，サニー ヴェイル，サンセット・アベニュー 382 (72)発明者 ウイリアム・アール・イムラー アメリカ合衆国 カリフォルニア，オーク ランド，ウィスコンシン・ストリート 3327Continued on the front page (72) Inventor Paul Es Martin United States of America, Fair Oaks Drive, Prestonton, California 7665 (72) Inventor Surge El Rudatsu United States of America California, Sunny Vale, Sunset Avenue 382 (72) Inventor William William Imler 3327 Wisconsin Street, Oakland, California, United States
Claims (1)
（１６）と、 前記透明基板上の不透明層（１４）と、 前記不透明層上のダイ取付け用エポキシ（２０）の層
と、 前記ダイ取付け用エポキシの層に取付けられたリードフ
レームと、 を備え、前記不透明層が前記ダイ取付け用エポキシの劣
化を減少させるように動作することを特徴とするＬＥＤ
組立品。1. A light emitting diode (16) having a transparent substrate (12); an opaque layer (14) on the transparent substrate; a layer of die attach epoxy (20) on the opaque layer; A lead frame attached to a layer of epoxy for mounting, the opaque layer operable to reduce degradation of the epoxy for die mounting.
Assemblies.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US1616398A | 1998-01-30 | 1998-01-30 | |
| US09/016-163 | 1998-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11261112A true JPH11261112A (en) | 1999-09-24 |
Family
ID=21775739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP813999A Pending JPH11261112A (en) | 1998-01-30 | 1999-01-14 | Led assembly |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH11261112A (en) |
| GB (1) | GB2333899A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861281B2 (en) | 2000-05-23 | 2005-03-01 | Toyoda Gosei Co., Ltd. | Group III nitride compound semiconductor light-emitting device and method for producing the same |
| US6960485B2 (en) | 2000-03-31 | 2005-11-01 | Toyoda Gosei Co., Ltd. | Light-emitting device using a group III nitride compound semiconductor and a method of manufacture |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4005457A (en) * | 1975-07-10 | 1977-01-25 | Semimetals, Inc. | Semiconductor assembly, method of manufacturing same, and bonding agent therefor |
-
1999
- 1999-01-14 JP JP813999A patent/JPH11261112A/en active Pending
- 1999-01-26 GB GB9901716A patent/GB2333899A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6960485B2 (en) | 2000-03-31 | 2005-11-01 | Toyoda Gosei Co., Ltd. | Light-emitting device using a group III nitride compound semiconductor and a method of manufacture |
| US6861281B2 (en) | 2000-05-23 | 2005-03-01 | Toyoda Gosei Co., Ltd. | Group III nitride compound semiconductor light-emitting device and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2333899A (en) | 1999-08-04 |
| GB9901716D0 (en) | 1999-03-17 |
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