JPH11260934A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce transistors mixedly with ease which are different from each other in threshold voltage, by providing both first and second MOS transistors in the same well, and by using gate electrodes made of materials having different work functions. SOLUTION: An N-type well region 102, a P-type well region 103, and an element a isolation region 104 are formed in a P-type silicon substrate 101. An oxide film 105 and an N-type polycrystalline silicon film 106 are formed such that they cover the whole substrate 101. The polycrystalline silicon film 106 is anisotropically etched by using a photoresist 107 to form an N-type polycrystalline silicon gate electrode 108. A tungsten film 109 and an oxide film 110 are formed and then the oxide film 110 and the tungsten film 109 are anisotropically etched by using a photoresist 111 to form a tungsten gate electrode 112. By the concurrent use of the N-type silicon gate electrode 108 and the tungsten gate electrode 112, transistors can be manufactured which are different from each other about 0.3 V in threshold voltage even if the concentration of the substrate is the same.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including transistors having different threshold voltage levels obtained by using gate electrodes made of materials having different work functions. And a method for producing the same.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for semiconductor integrated circuits to have lower power consumption in addition to the demand for higher speed. Among them, reduction of the gate length of an element, particularly a transistor, is the most suitable means for realizing high speed, and this has led to mass production of fine transistors formed according to the 0.25 μm rule. . On the other hand, regarding the realization of low power consumption,
The reduction of the power supply voltage is the most suitable means, and the power supply voltage has shifted from the 5V system to the 3V system for transistors having the 0.5 μm rule or later.

However, the reduction of the power supply voltage as described above
A reduction in the driving capability of the transistor causes a reduction in the gate length, and a reduction in the gate length increases a leakage current due to a short channel effect or the like. Thus, the above-mentioned demand for high speed and the demand for low power consumption are in a trade-off relationship, and how to make these two contradictory demands compatible with each other, including portable devices, is considered. This is the biggest issue in the development of multimedia LSIs in the future.

[0004] For the purpose of solving the above problems, a method of combining several types of transistors having different threshold voltages is disclosed in, for example, Japanese Patent Application Laid-Open No. H5-210976. For example, Japanese Patent Application Laid-Open No. 6-53496 proposes a method of controlling a threshold voltage to a plurality of levels by controlling a substrate potential.

FIGS. 13 (a) to 13 (e) show, for example,
FIG. 3 is a cross-sectional view of a manufacturing process for forming a semiconductor device configured by combining a plurality of transistors having different threshold voltages as disclosed in JP-A-210976 when using a conventional technique.

[0006] Specifically, first, in FIG.
An N-type well region 802, a P-type well region 803, and an element isolation region 804 are formed in a P-type semiconductor substrate 801 respectively. Next, in FIG. 13B, impurities are implanted into an arbitrary active region in the N-type well region 802 by using a photoresist 805 formed to have a predetermined pattern as a mask, and An impurity diffusion region 806 having an impurity concentration different from other portions of the well region 802 is formed. Further, in FIG. 13C, after removing the photoresist 805, a new photoresist 807 having a different pattern is formed, and using this as a mask, an arbitrary active region in the P-type well region 803 is formed. To the impurity diffusion region 80 having an impurity concentration different from that of other portions of the P-type well region 803.
8 is formed. Subsequently, after removing the photoresist 807, the insulating film 809, the N-type polycrystalline silicon film 810,
And an oxide film 811 are sequentially formed, and a photoresist 812 having a predetermined shape is formed thereon. And
By patterning using the photoresist 812 as a mask, a gate electrode having a predetermined shape is formed as shown in FIG. Thereafter, as shown in FIG. 13E, after forming a P-type source / drain diffusion region 813 and an N-type source / drain diffusion region 814, the interlayer film 8 is formed.
And a metal wiring 816 connected to the P-type and N-type source / drain diffusion regions 813 and 814 through through holes formed in predetermined portions of the interlayer film 815.
Is formed, and the manufacturing process is completed.

In the semiconductor device thus formed, two types of transistors, a transistor having a channel region formed by an impurity diffusion region 806 and a transistor having no channel region, are formed in an N-type well region 802. Have been. Similarly, two types of transistors are formed in the P-type well region 803: a transistor in which the channel region is formed by the impurity diffusion region 808 and a transistor in which the channel region is not formed. One of the two types of transistors has a lower threshold voltage (for example, 0.3 V).
V) and the other is a higher threshold voltage (eg, 0.8 V)
The impurity concentration of the N-type well region 802 and the P-type well region 803 and the impurity diffusion region 806
And 808 are controlled.

By providing a plurality of transistors having different threshold voltages as described above, in the semiconductor device described with reference to FIG. 13, when the circuit is stopped (standby), the circuit having a higher threshold is turned off to turn off the circuit. Power consumption, while the circuit operates,
High-speed operation can be obtained by operating a transistor having a low threshold voltage and a high driving capability while always turning on a transistor having a high threshold voltage. That is, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 5-210976, the threshold voltage is controlled by performing an additional impurity implantation process (forming an additional impurity diffusion region at a predetermined location).

On the other hand, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 6-53496, the threshold voltage of the transistor is changed by changing the substrate potential by applying a predetermined level of the substrate bias voltage. However, the operation principle is substantially the same as the operation principle of the semiconductor device disclosed in Japanese Patent Application Laid-Open No. H5-210976.

As described above, in each of the prior arts described above, a transistor having a low threshold value and a high drive capability is used during circuit operation, and a transistor having a high threshold value and a small leak current is used during circuit stop (standby). Cut the path. This makes it possible to achieve both high speed and low power consumption.

[0011]

However, any of the above-mentioned prior arts presents undesirable problems.

That is, the conventional manufacturing method disclosed in Japanese Patent Application Laid-Open No. H5-210976 has a problem that the ion implantation step is increased because the additional impurity diffusion regions 806 and 808 are formed. doing. However, such an increase in the number of steps causes undesired problems such as an increase in time and cost required for manufacturing.

In this case, what is required is doping of a shallow portion of the substrate with impurities. However, according to the study by the present inventors, such a shallow channel doping (low energy implantation) causes the following problems.

That is, generally, in the ion implantation process for controlling the threshold voltage, a thin protective oxide film is formed on the implantation surface for the purpose of avoiding the occurrence of damage to the photoresist and the occurrence of channeling of the implanted ions. On the other hand, a resist ashing step and a cleaning step are performed along with the execution of the implantation step. When the above-described ashing and cleaning are repeated along with the repetition of the implantation processing, the protective oxide film gradually becomes thinner. Further, since the protective oxide film is damaged at the time of implantation, the etching rate is increased and the etching is unevenly performed. As a result, in the subsequent subsequent implantation step, the thickness of the protective oxide film greatly varies within the wafer surface.

FIG. 12 is a graph showing the relationship between the thickness (horizontal axis) of the protective oxide film and the threshold voltage Vt (vertical axis) in the N-channel transistor. Specifically, the gate length Lg = 0.5 μm and the thickness of the gate oxide film Tox = 7 nm
BF ₂ ions for controlling the threshold voltage were implanted under the conditions of an acceleration voltage of 30 keV and a dose of 3 × 10 ¹² cm ^{−2, and} an acceleration voltage of 50 keV and a dose of 2 × 10 ¹² cm ^-2
In this case, data is shown for each of the cases.

Accordingly, low energy implantation necessary for performing shallow channel doping which is particularly required for forming a fine transistor (accelerating voltage 30 keV in FIG. 12)
In this case, the threshold voltage shows a large variation (dependence on film thickness). Further, the dependence of such a threshold voltage on the thickness of the protective oxide film increases as the shallow channel doping is formed.

In order to solve this problem, it is necessary to re-form a protective oxide film each time prior to each implantation process. However, in practice, the number of steps is greatly increased. is not.

On the other hand, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 6-53496, it is necessary to provide a contact for applying a necessary substrate bias voltage to all transistors to be controlled through the substrate potential. In addition, it is necessary to provide a generating circuit for generating a predetermined substrate bias voltage. For these reasons, the area occupied by the circuit increases, making it difficult to reduce the overall size of the semiconductor device. have.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has the following objects. (1) The use of a gate electrode made of a material having a different work function makes it possible to achieve a different threshold voltage. It is to provide a semiconductor device in which transistors can be easily mixed, and (2) to provide a method for manufacturing such a semiconductor device.

[0020]

According to the present invention, there is provided a semiconductor device comprising:
A first MOS transistor having a polycrystalline silicon gate electrode formed from polycrystalline silicon;
A second MOS transistor having a metal gate electrode formed of more than one type of metal, wherein both the first and second MOS transistors are provided in the same well, whereby The above object is achieved.

In one embodiment, the impurity concentration of the channel region of the first MOS transistor is equal to the second M transistor.
The impurity concentration of the channel region of the OS transistor is set to a level different from that of the impurity concentration.

The first and second MOS transistors can be formed on a substrate having an SOI structure.

[0023] The metal gate electrode of the second MOS transistor may be formed of at least one material selected from the group consisting of tungsten, tungsten silicide, molybdenum, molybdenum silicide, titanium, and titanium silicide.

Alternatively, the metal gate electrode of the second MOS transistor has a multilayer structure including a first layer made of titanium nitride or tungsten nitride and a second layer made of tungsten, molybdenum, or titanium. You may have.

In one case, the metal gate electrode of the second MOS transistor is formed of tungsten or tungsten silicide, and the polycrystalline silicon gate electrode of the first MOS transistor is formed of polycrystalline silicon. It has a multilayer structure including one layer and a second layer made of tungsten or tungsten silicide.

In another case, the metal gate electrode of the second MOS transistor is formed of molybdenum or molybdenum silicide, and the polysilicon gate electrode of the first MOS transistor is formed of polysilicon. It has a multilayer structure including a first layer and a second layer made of molybdenum or molybdenum silicide.

In still another case, the metal gate electrode of the second MOS transistor is formed of titanium or titanium silicide, and the polysilicon gate electrode of the first MOS transistor is formed of polysilicon. And a second layer made of titanium or titanium silicide.

According to another aspect of the present invention, there is provided a semiconductor device having a first MOS transistor having a gate electrode formed of polycrystalline silicon of a first conductivity type, and a gate formed of polycrystalline silicon of a second conductivity type. Second M with electrode
And an OS transistor, wherein both the first and second MOS transistors are provided in the same well, thereby achieving the above object.

In one embodiment, the impurity concentration of the channel region of the first MOS transistor is equal to the second M transistor.
The impurity concentration of the channel region of the OS transistor is set to a level different from that of the impurity concentration.

In a method of manufacturing a semiconductor device according to the present invention, a step of forming an element isolation region in a semiconductor substrate, a step of forming a first insulating film and a polycrystalline silicon film on the semiconductor substrate,
Patterning the first insulating film and the polycrystalline silicon film into a predetermined shape to form a gate electrode of a first MOS transistor; and forming a metal film so as to cover the semiconductor substrate. Is patterned into a predetermined shape,
Forming the gate electrode of the second MOS transistor, thereby achieving the object described above.

In one embodiment, the step of forming the gate electrode of the second MOS transistor includes the step of forming the first MOS transistor.
Removing the first insulating film at a portion other than the gate electrode of the transistor, and forming a second insulating film;
Wherein the metal film is formed on the second insulating film,
When the metal film is patterned into a predetermined shape, the second insulating film is also patterned into the same shape.

[0032] The first insulating film and the second insulating film may be formed of the same material and have substantially the same thickness.

Alternatively, the first insulating film and the second insulating film can be formed from different materials. Further, the first insulating film and the second insulating film may have different thicknesses.

According to another method of manufacturing a semiconductor device of the present invention, a step of forming an element isolation region in a semiconductor substrate, a step of forming an insulating film and a polycrystalline silicon film on the semiconductor substrate, Patterning the film into a predetermined shape, depositing a metal film, patterning the polycrystalline silicon film and the metal film into a predetermined shape, and forming a gate electrode. Thereby, the above-mentioned object is achieved.

In the method of manufacturing a semiconductor device according to the present invention as described above, the metal film is made of at least one material selected from the group consisting of tungsten, tungsten silicide, molybdenum, molybdenum silicide, titanium, and titanium silicide. Can be formed.

Alternatively, the metal film comprises a first layer made of titanium nitride or tungsten nitride;
Second made of tungsten, molybdenum or titanium
Layer.

According to still another method of manufacturing a semiconductor device of the present invention, a step of forming an element isolation region in a semiconductor substrate and a step of forming an insulating film and a first conductivity type polycrystalline silicon film on the semiconductor substrate Changing the conductivity type of a predetermined region of the polycrystalline silicon film to a second conductivity type opposite to the first conductivity type; and polycrystalline silicon of the first conductivity type and the second conductivity type. Patterning the film into a predetermined shape to form a gate electrode.
The above objective is accomplished.

According to still another method of manufacturing a semiconductor device of the present invention, there are provided a step of forming an element isolation region in a semiconductor substrate, a step of forming an insulating film and an undoped polycrystalline silicon film on the semiconductor substrate, Setting the conductivity type of the first region of the polycrystalline silicon film to the first conductivity type; and setting the conductivity type of a second region of the polycrystalline silicon film different from the first region to the first conductivity type. Setting a second conductivity type opposite to the first conductivity type; patterning the first and second regions of the polycrystalline silicon film into a predetermined shape to form a gate electrode; Which achieves the above-mentioned object.

In the method of manufacturing a semiconductor device according to the present invention having various features as described above, a plurality of MOS devices are provided.
A transistor can be formed. In that case, multiple MO
Impurity doping may be performed on at least one channel region of the S transistor to change a work function of the channel region.

According to the semiconductor device of the present invention having the above-described features and the method of manufacturing the same, in the transistors of the same conductivity type, the N-type polysilicon gate electrode and the P-type
Transistors having different threshold voltages can be easily formed in one semiconductor device by using a combination of a polycrystalline silicon gate electrode or a combination of a polycrystalline silicon gate electrode and a metal gate electrode.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to some embodiments of the present invention and a method for manufacturing the same will be described with reference to the accompanying drawings.

(First Embodiment) FIGS. 1 (a) to 1 (f)
FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

First, referring to FIG. 1A, a predetermined portion of a P-type silicon
A mold well region 102, a P-type well region 103, and an element isolation region 104 are formed.

Next, in FIG. 1 (b), the thickness of the substrate 101, which functions as a gate oxide film, is, for example, about 6 so as to cover the entire surface of the substrate 101 on which these regions are formed.
An oxide film 105 of nm is formed by using a dry oxidation method or a wet oxidation method. Thereafter, the thickness is for example about 20
A 0 nm N-type polycrystalline silicon film 106 is formed on the oxide film 105 by using, for example, a vapor deposition method.

Subsequently, as shown in FIG. 1C, after a photoresist 107 having a predetermined pattern is formed on the N-type polysilicon film 106, the photoresist 107 is used as a mask to form a polysilicon. The film 106 is anisotropically etched using, for example, an RIE dry etching method to form an N-type polysilicon gate electrode 1 having a predetermined pattern.
08 is formed.

Further, as shown in FIG. 1D, after removing the photoresist 107, a tungsten film 109 having a thickness of, for example, It is formed so as to cover the upper surface of the structure formed above including the crystalline silicon electrode 108. Further, an oxide film 110 having a thickness of, for example, about 100 nm is formed thereon. The tungsten film 10
Instead of 9, another metal film such as a molybdenum film or a titanium film, a metal compound film such as titanium nitride, or a multilayer film obtained by combining them may be used.

Then, as shown in FIG. 1E, a new photoresist 111 having a predetermined pattern is
On the oxide film 1 using this as a mask.
10 and the tungsten film 109 are anisotropically etched using, for example, an RIE dry etching method to form a tungsten gate electrode (metal gate electrode) 11 having a predetermined pattern.
Form 2

Finally, as shown in FIG. 1F, after forming a P-type source / drain diffusion region 113 and an N-type source / drain diffusion region 114, an interlayer film 115 is deposited. A metal wiring 116 connected to the P-type and N-type source / drain diffusion regions 113 and 114 through the through holes formed at
The manufacturing process is completed.

The operation of the semiconductor device according to the present embodiment configured as described above will be described in the case of an N-channel transistor.

In this semiconductor device, typically, N
The work function of the polycrystalline silicon gate electrode 108 is about 4.
3 eV, while the work function of the tungsten gate electrode 112 is about 4.6 V. FIG. 7 shows a measurement example of the sub-threshold characteristic obtained in this case. That is, FIG. 7 is a graph showing how the drain current Id (vertical axis) changes with respect to the gate applied voltage Vg (horizontal axis). The black circle plot (n + Poly-Si) shows the N-type polycrystalline silicon gate. The white circle plot (W) is data regarding the electrode 108 and the data regarding the tungsten gate electrode 112.

As shown in FIG. 7, there is a difference of about 0.3 V between the data of the N-type polysilicon gate electrode 108 and the data of the tungsten gate electrode 112 in the linear portion. Therefore, by utilizing this point, a transistor having a threshold voltage difference of about 0.3 V even when the substrate concentration is the same can be formed by using the N-type polysilicon gate electrode 108 and the tungsten gate electrode 112 together. You can see that it can be done. Specifically, for example, when the threshold voltage of the transistor having the N-type polysilicon gate electrode 108 is set to about 0.5 V, the threshold voltage of the transistor having the tungsten gate electrode 112 is about 0.8 V. Such transistors have sufficiently low off-leakage current (typically about 100 fA / μm
Therefore, it can be used as a cut-off transistor when the circuit is stopped or as a cut-pass transistor when the circuit is operating.

Although the effects of the present invention have been described above by taking an N-channel transistor as an example, the same effects can be obtained with a P-channel transistor as with an N-channel transistor.

As described above, according to the present embodiment, a semiconductor device in which transistors having different threshold voltages coexist can be used by using both a polysilicon gate electrode and a metal gate electrode without increasing the number of impurity implantation steps. Can be easily formed.

(Second Embodiment) FIGS. 2A to 2F
FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

First, referring to FIG. 2A, a predetermined portion of a P-type silicon
A type well region 202, a P type well region 203, and an element isolation region 204 are formed.

Next, in FIG. 2B, the thickness of the gate insulating film, which functions as a gate oxide film, is about 6 so as to cover the entire surface of the substrate 201 where these regions are formed.
An oxide film 205 of nm is formed by using a dry oxidation method or a wet oxidation method. Thereafter, the thickness is for example about 20
A 0 nm N-type polycrystalline silicon film 206 is formed on the oxide film 205 by using, for example, a vapor growth method.

Subsequently, as shown in FIG. 2C, after a photoresist 207 having a predetermined pattern is formed on the N-type polysilicon film 206, the polysilicon 207 is formed using the photoresist 207 as a mask. The film 206 is anisotropically etched using, for example, an RIE dry etching method to form an N-type polysilicon gate electrode 2 having a predetermined pattern.
08 is formed. In this etching, the oxide film 2
05 is also patterned into a shape corresponding to the N-type polysilicon gate electrode 208.

Further, as shown in FIG. 2D, after removing the photoresist 207, a new oxide film 209 having a thickness of about 6 nm, for example, which functions as a gate oxide film, is replaced with an N-type polycrystal. Dry oxidation method so as to cover the upper surface of the structure formed above including the silicon electrode 208;
It is formed by a wet oxidation method or a vapor growth method.
Then, using a vapor phase growth method or a high temperature sputtering method,
A tungsten film 210 having a thickness of about 200 nm, for example,
It is formed on the oxide film 209. Further, an oxide film 211 having a thickness of, for example, about 100 nm is formed thereon. Note that, instead of the tungsten film 210, another metal film such as a molybdenum film or a titanium film, a metal compound film such as a titanium nitride, or a multilayer film obtained by combining them may be used.

Then, as shown in FIG. 2E, a new photoresist 212 having a predetermined pattern is
On the oxide film 2 using the mask as a mask.
11 and the tungsten film 210 are anisotropically etched using, for example, an RIE dry etching method to form a tungsten gate electrode (metal gate electrode) 21 having a predetermined pattern.
Form 3

Finally, as shown in FIG. 2F, after forming a P-type source / drain diffusion region 214 and an N-type source / drain diffusion region 215, an interlayer film 216 is deposited. A metal wiring 217 connected to the P-type and N-type source / drain diffusion regions 214 and 215 through the through holes formed at
The manufacturing process is completed.

The operation of the semiconductor device according to the present embodiment configured as described above will be described in the case of an N-channel transistor.

Also in this semiconductor device, typically,
The work function of the N-type polysilicon gate electrode 208 is about 4.3 eV, while the work function of the tungsten gate electrode
The work function of 3 is about 4.6V. The sub-threshold characteristics obtained in this case are the same as those shown in FIG. 7 referred to in the first embodiment, and the N-type polysilicon gate electrode 208 and the tungsten gate electrode 213 are provided.
By using together, a transistor having a difference in threshold voltage of about 0.3 V can be formed even when the substrate concentration is the same. Specifically, for example, the threshold voltage of the transistor having the N-type polysilicon gate electrode 208 is set to about 0.5
When set to V, the threshold voltage of the transistor having the tungsten gate electrode 213 is about 0.8 V. Such a transistor has sufficiently small off-leak current (typically about 100 fA / μm or less), and thus can be used as a cut-off transistor when the circuit is stopped or a cut-pass transistor when the circuit is operating.

In the method of manufacturing a semiconductor device according to the present embodiment, the gate oxide film 205 under the N-type polysilicon gate electrode 208 and the tungsten gate electrode 21
3 and the gate oxide film 209 under the third step are formed in another process.
For this purpose, for example, in one of the gate electrodes, another insulating film composed of a nitride film or the like is used as the gate insulating film instead of the gate oxide film, or the thickness of the gate oxide film (insulating film) is reduced. By making the transistors different, the control range of the threshold voltage of the formed transistor can be widened. Further, FIG.
In (e), the selectivity at the time of etching the tungsten film 210 can be increased by the action of the gate oxide film 209 covering the semiconductor device. As a result, the etching residue of tungsten can be completely removed.

Although the effects of the present invention have been described with reference to an N-channel transistor as an example, the same effect can be obtained with a P-channel transistor as with an N-channel transistor.

As described above, according to the present embodiment, a semiconductor device in which transistors having different threshold voltages coexist can be used by using both a polysilicon gate electrode and a metal gate electrode without increasing the number of impurity implantation steps. Can be easily formed. Further, by using two types of gate insulating films, the control range of the threshold voltage can be increased.

(Third Embodiment) FIGS. 3A to 3F
FIG. 10 is a process sectional view illustrating the method for manufacturing the semiconductor device in the third embodiment of the present invention.

First, referring to FIG. 3A, a predetermined portion of a P-type silicon substrate
A type well region 302, a P-type well region 303, and an element isolation region 304 are formed.

Next, as shown in FIG. 3B, the thickness of the substrate 301, which functions as a gate oxide film, is about 6 so as to cover the entire surface of the substrate 301 on which these regions are formed.
An oxide film 305 of nm is formed by using a dry oxidation method or a wet oxidation method. Thereafter, the thickness is for example about 20
A 0 nm N-type polycrystalline silicon film 306 is formed on the oxide film 305 by using, for example, a vapor deposition method.

Subsequently, as shown in FIG. 3C, a photoresist 307 having a pattern covering only a portion where an active region is to be located in a transistor having a polycrystalline silicon gate electrode to be finally formed is formed. It is formed on the N-type polycrystalline silicon film 306. Thereafter, using the photoresist 307 as a mask, the polycrystalline silicon film 306 is anisotropically etched using, for example, RIE dry etching.

Further, as shown in FIG. 3D, after removing the photoresist 307, a tungsten film 308 having a thickness of, for example, about 200 nm was patterned by a vapor phase growth method or a high-temperature sputtering method. It is formed so as to cover the upper surface of the structure formed above including the N-type polycrystalline silicon electrode 306. Further, an oxide film 309 having a thickness of, for example, about 100 nm is formed thereon. In addition,
Instead of the tungsten film 308, another metal film such as a molybdenum film or a titanium film, a metal compound film such as a titanium nitride, or a multilayer film combining these may be used.

Then, as shown in FIG. 3E, a new photoresist 311 having a predetermined pattern is formed on the oxide film 309.
On the oxide film 3 using the mask as a mask.
09 and the tungsten film 308 are anisotropically etched using, for example, RIE dry etching to form an N-type polycrystalline silicon gate electrode 312 and a tungsten gate electrode (metal gate electrode) 313 in a predetermined pattern.

Finally, as shown in FIG. 3F, after forming a P-type source / drain diffusion region 314 and an N-type source / drain diffusion region 315, an interlayer film 316 is deposited. Metal wiring 317 connected to the P-type and N-type source / drain diffusion regions 314 and 315 through the through holes formed at
The manufacturing process is completed.

The operation of the semiconductor device according to the present embodiment configured as described above will be described in the case of an N-channel transistor.

Also in this semiconductor device, typically,
The work function of the N-type polysilicon gate electrode 312 is about 4.3 eV, while the tungsten gate electrode 31
The work function of 3 is about 4.6V. The sub-threshold characteristics obtained in this case are the same as those shown in FIG. 7 referred to in the first embodiment, and include an N-type polysilicon gate electrode 312 and a tungsten gate electrode 313.
By using together, a transistor having a difference in threshold voltage of about 0.3 V can be formed even when the substrate concentration is the same. Specifically, for example, the threshold voltage of the transistor having the N-type polysilicon gate electrode 312 is set to about 0.5
When set to V, the threshold voltage of the transistor having the tungsten gate electrode 313 is about 0.8 V. Such a transistor has sufficiently small off-leak current (typically about 100 fA / μm or less), and thus can be used as a cut-off transistor when the circuit is stopped or a cut-pass transistor when the circuit is operating.

In the method of manufacturing a semiconductor device according to the present embodiment, the N-type polycrystalline silicon gate electrode 312 is
It has a polycide structure in which a low-resistance tungsten film is formed on a polycrystalline silicon film. In general, the parasitic resistance generated in the gate electrode suppresses the realization of high-speed operation of the transistor. However, the use of such a polycide structure in the present embodiment reduces such parasitic resistance.

Although the effects of the present invention have been described above by taking an N-channel transistor as an example, the same effects can be obtained with a P-channel transistor as with an N-channel transistor.

As described above, according to the present embodiment, by using both a polysilicon gate electrode and a metal gate electrode without increasing the number of impurity implantation steps, a semiconductor device having transistors having different threshold voltages coexist. Can be easily formed. Furthermore, by forming the polycrystalline silicon gate electrode into a polycide structure, high-speed operation of the formed device is enabled.

(Fourth Embodiment) FIGS. 4A to 4E
FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor device in the fourth embodiment of the present invention.

First, referring to FIG. 4A, a predetermined portion of a P-type silicon
A mold well region 402, a P-type well region 403, and an element isolation region 404 are formed.

Next, in FIG. 4B, the thickness serving as a gate oxide film is, for example, about 6 so as to cover the entire surface of the substrate 401 on which these regions are formed.
An oxide film 405 of nm is formed using a dry oxidation method or a wet oxidation method. Thereafter, the thickness is for example about 20
A 0-nm N-type polycrystalline silicon film 406 is formed on the oxide film 405 by using, for example, a vapor deposition method. here,
The N-type impurity concentration in the N-type polycrystalline silicon film 406 is:
Preferably, from about 1 × 10 ¹⁹ cm ⁻² to about 5 × 10 ¹⁹ cm ⁻²
Set to. Subsequently, after a photoresist 407 having a predetermined pattern is formed on the N-type polycrystalline silicon film 406,
Using the photoresist 407 as a mask, a P-type impurity is implanted into the polycrystalline silicon film 406 to form a P-type polycrystalline silicon region 408. Here, the P-type impurity concentration in P-type polycrystalline silicon region 408 is preferably set to about 1 × 10 ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ⁻² . On the other hand, in the N-type polycrystalline silicon film 406 formed first, a region not converted to the P-type polycrystalline silicon region 408 remains as the N-type polycrystalline silicon region 406.

Further, as shown in FIG. 4C, after removing the photoresist 407, an oxide film 409 is formed so as to cover the N-type polysilicon region 406 and the P-type polysilicon region 408.

Then, as shown in FIG. 4D, a new photoresist 410 having a predetermined pattern is formed on the oxide film 409.
On the oxide film 4 using this as a mask.
09, the N-type polysilicon region 406, and the P-type polysilicon region 408 are anisotropically etched using, for example, an RIE dry etching method.
A type polysilicon gate electrode 411 and a P type polysilicon gate electrode 412 are formed.

Finally, as shown in FIG. 4E, after forming a P-type source / drain diffusion region 414 and an N-type source / drain diffusion region 415, an interlayer film 416 is deposited. Metal wiring 417 connected to the P-type and N-type source / drain diffusion regions 414 and 415 through the through holes formed at
The manufacturing process is completed.

The operation of the semiconductor device according to the present embodiment configured as described above will be described in the case of an N-channel transistor.

In this semiconductor device, typically, N
The work function of the polycrystalline silicon gate electrode 411 is about 4.
3 eV, while the P-type polysilicon gate electrode 4
The work function of Twelve is about 5.3V. FIG. 8 shows a measurement example of the sub-threshold characteristic obtained in this case. FIG. 8 is a graph showing how the drain current Id (vertical axis) changes with respect to the gate applied voltage Vg (horizontal axis). The black circle plot (n + Poly-Si) shows the N-type polycrystalline silicon gate electrode 411. Data, and a white circle plot (p +
Poly-Si) is data on the P-type polycrystalline silicon gate electrode 412.

Referring to FIG. 8, data of N-type polysilicon gate electrode 411 and P-type polysilicon gate electrode 412 are shown.
There is a difference of about 1.0 V in the linear part between these data. Therefore, by taking advantage of this point, N
It can be seen that a transistor having a threshold voltage difference of about 1.0 V can be formed even when the substrate concentration is the same, by using the p-type polysilicon gate electrode 411 and the p-type polysilicon gate electrode 412 together. Specifically, for example, when the threshold voltage of the transistor having the N-type polysilicon gate electrode 411 is set to about 0.2 V,
The threshold voltage of the transistor having the P-type polysilicon gate electrode 412 is about 1.2V. Such a transistor has sufficiently small off-leak current (typically about 100 fA / μm or less), and thus can be used as a cut-off transistor when the circuit is stopped or a cut-pass transistor when the circuit is operating.

Although the effects of the present invention have been described with reference to an N-channel transistor as an example, the same effects can be obtained with a P-channel transistor as with an N-channel transistor.

As described above, according to this embodiment, the threshold voltage can be varied by using both the N-type polysilicon gate electrode and the P-type polysilicon gate electrode without increasing the impurity implantation step. A semiconductor device in which transistors coexist can be easily formed.

(Fifth Embodiment) FIGS. 5A to 5E
FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor device in the fifth embodiment of the present invention.

First, as shown in FIG. 5A, a predetermined portion of a P-type silicon substrate
A mold well region 502, a P-type well region 503, and an element isolation region 504 are formed.

Next, in FIG. 5B, the thickness of the substrate 501 on which the respective regions are formed is about 6 to function as a gate oxide film so as to cover the entire surface.
An oxide film 505 of nm is formed by using a dry oxidation method or a wet oxidation method. Thereafter, the thickness is for example about 20
An undoped polycrystalline silicon film 506 of 0 nm is formed on the oxide film 505 by using, for example, a vapor deposition method.

Next, a photoresist 5 having a predetermined pattern is formed.
07 is formed on the undoped polycrystalline silicon film 506, and then an N-type impurity is implanted into the undoped polycrystalline silicon film 506 using the photoresist 507 as a mask.
Form polycrystalline silicon region 508 is formed. Here, the N-type impurity concentration in N-type polycrystalline silicon region 508 is preferably set to about 1 × 10 ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ⁻² .

Subsequently, after removing the photoresist 507, a photoresist 509 covering the N-type polycrystalline silicon region 508 is formed as shown in FIG. Then, a P-type impurity is implanted using the photoresist 509 as a mask to form a P-type polycrystalline silicon region 510. Here, the P-type impurity concentration in P-type polysilicon region 510 is preferably about 1 × 10 ¹⁵ cm ⁻² to
Set to about 5 × 10 ¹⁵ cm ^-2 .

Further, after removing the photoresist 509, an oxide film 511 is formed so as to cover the N-type polysilicon region 508 and the P-type polysilicon region 510. Then, as shown in FIG. 5D, a new photoresist 512 having a predetermined pattern is formed on the oxide film 511, and using this as a mask, the oxide film 511 and the N
The polycrystalline silicon region 518 and the polycrystalline silicon region 510 are anisotropically etched using, for example, RIE dry etching to form a predetermined pattern of an N-type polycrystalline silicon gate electrode 513 and a P-type polycrystalline silicon region. A gate electrode 514 is formed.

Finally, as shown in FIG. 5E, after forming a P-type source / drain diffusion region 515 and an N-type source / drain diffusion region 516, an interlayer film 517 is deposited. Metal wiring 518 connected to the P-type and N-type source / drain diffusion regions 515 and 516 through the through holes formed at
The manufacturing process is completed.

The operation of the semiconductor device according to the present embodiment configured as described above will be described in the case of an N-channel transistor.

In this semiconductor device also, typically,
The work function of the N-type polysilicon gate electrode 513 is about 4.3 eV, while the work function of the P-type polysilicon gate electrode 514 is about 5.3 V. The sub-threshold characteristic obtained in this case is the same as that shown in FIG. 8 referred to in connection with the fourth embodiment, and the N-type polysilicon gate electrode 513 and the P-type polysilicon gate electrode 514 It can be seen that a transistor having a difference in threshold voltage of about 1.0 V can be formed even when the substrate concentration is the same by the combined use. Specifically, for example,
When the threshold voltage of the transistor having the N-type polysilicon gate electrode 513 is set to about 0.2 V, the threshold voltage of the transistor having the P-type polysilicon gate electrode 514 is about 1.2 V. Such transistors have sufficiently low off-leakage current (typically about 10
(0 fA / μm or less), so that it can be used as a cut-off transistor when the circuit is stopped or as a cut-pass transistor when the circuit is operating.

Further, in the method for fabricating the semiconductor device according to the present embodiment, the formation of the N-type polycrystalline silicon region and the formation of the P-type polycrystalline silicon region are performed by separate impurity implantation steps. It becomes easy to control the impurity concentration in the inside.

Although the effects of the present invention have been described with reference to an N-channel transistor as an example, the same effects can be obtained with a P-channel transistor as with an N-channel transistor.

As described above, according to this embodiment, the threshold voltage can be varied by using both the N-type polysilicon gate electrode and the P-type polysilicon gate electrode without increasing the impurity implantation step. A semiconductor device in which transistors coexist can be easily formed.

(Sixth Embodiment) FIGS. 6A to 6E
FIG. 16 is a process sectional view illustrating the method for manufacturing the semiconductor device in the sixth embodiment of the present invention.

First, referring to FIG. 6A, a predetermined portion of a P-type silicon substrate 601 is formed by using a well-known manufacturing technique.
A mold well region 602, a P-type well region 603, and an element isolation region 604 are formed. Next, after a photoresist 605 having a predetermined pattern as shown in the figure is formed, N
N-type impurities are implanted into a predetermined region in the mold well region 602 to form an N-type diffusion region 606 having an impurity concentration different from that of the N-type well region 602.

Next, after removing the photoresist 605,
A photoresist 607 having a predetermined pattern as shown in FIG. 6B is formed. Then, using the photoresist 607 as a mask, a P-type impurity is implanted into a predetermined region in the P-type well region 603 to form a P-type well region 603.
P-type diffusion region 608 having an impurity concentration different from the above is formed.

After the formation of the photoresist 607, an oxide film 609 having a thickness of about 6 nm, which functions as a gate oxide film, is formed so as to cover the substrate 601 on which the above-described regions are formed. It is formed using a dry oxidation method or a wet oxidation method. Thereafter, an N-type polycrystalline silicon film 610 having a thickness of, for example, about 200 nm is formed on the oxide film 609 by using, for example, a vapor deposition method. Here, the N-type impurity concentration in the N-type polycrystalline silicon film 610 is preferably about 1 × 10 ¹⁹ cm ⁻² to about 5 ×
Set to 10 ¹⁹ cm ^-2 .

Next, as shown in FIG. 6C, after a photoresist 611 having a predetermined pattern is formed on the N-type polysilicon film 610, the photoresist 611 is used as a mask to form the N-type polysilicon. A P-type impurity is implanted into the silicon film 610 to form a P-type polycrystalline silicon region 612. Here, the P-type impurity concentration in P-type polysilicon region 612 is preferably about 1 × 10 ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ^−2.
Set to × 10 ¹⁵ cm ^-2 .

Further, after removing the photoresist 611, an oxide film 613 is formed so as to cover the N-type polysilicon region 610 and the P-type polysilicon region 612. Then, as shown in FIG. 6D, a new photoresist 614 having a predetermined pattern is formed on the oxide film 613, and using this as a mask, the oxide film 613, N
The polycrystalline silicon region 610 and the p-type polycrystalline silicon region 612 are anisotropically etched using, for example, an RIE dry etching method to form a predetermined pattern of an n-type polycrystalline silicon gate electrode 615 and a p-type polycrystalline silicon. A gate electrode 616 is formed.

Finally, as shown in FIG. 6E, after forming a P-type source / drain diffusion region 617 and an N-type source / drain diffusion region 618, an interlayer film 619 is deposited. Forming a metal wiring 620 connected to the P-type and N-type source / drain diffusion regions 617 and 618 through the through holes formed at
The manufacturing process is completed.

The operation of the semiconductor device having the above-described structure according to the present embodiment will be described in the case of an N-channel transistor.

Also in this semiconductor device, typically,
The work function of the N-type polysilicon gate electrode 615 is about 4.3 eV, while the work function of the P-type polysilicon gate electrode 616 is about 5.3 V. The subthreshold characteristics obtained in this case are the same as those shown in FIG. 8 referred to in connection with the fourth embodiment, and the N-type polysilicon gate electrode 615 and the P-type polysilicon gate electrode 616 It can be seen that a transistor having a difference in threshold voltage of about 1.0 V can be formed even when the substrate concentration is the same by the combined use. Further, the N-type diffusion region 606 and the P-type diffusion region 60 having different impurity concentrations in the N-type well region 612 and the P-type well region 613.
By forming transistors 8 and using them as channel regions, the threshold voltages of these transistors can be set to further different levels by utilizing changes in the work function of the substrate. That is, as shown in FIG. 9, a total of four types of different sub-threshold characteristics are obtained, and by using these characteristics, transistors having a total of four types of different threshold voltages are formed in one semiconductor device. Can be.

Although the effects of the present invention have been described above by taking an N-channel transistor as an example, a P-channel transistor has the same effect as that of an N-channel transistor.

As described above, according to the present embodiment, the impurity implantation process for controlling the threshold voltage level is performed, and the N-type polysilicon gate electrode and the P-type polysilicon described in the previous embodiment are used. Through the two methods of using the gate electrode together with the gate electrode, a semiconductor device in which transistors having different types of different threshold voltages coexist can be easily formed.

In the above description of each embodiment, the present invention is applied to a normal bulk transistor that does not include a buried oxide layer. Alternatively, even when the present invention is applied to a semiconductor substrate having an SOI structure including a buried oxide layer, the same effects as those described above can be obtained.

(Seventh Embodiment) FIG. 10 is a sectional view schematically showing the structure of an N-channel transistor as a semiconductor device according to a seventh embodiment of the present invention.

More specifically, this transistor includes a channel portion 704 and a drain diffusion region in an active region near the surface of a P-type semiconductor substrate 701 provided with a buried oxide layer 702 and separated by an element isolation region 703. 705 and a source diffusion region 706 are formed. further,
On the channel portion 704, a P-type polycrystalline silicon gate electrode 708 is provided via a gate oxide film 707.

The operation of the semiconductor device (N-channel transistor) according to the present embodiment configured as described above is described below.
This will be described with reference to FIG.

FIG. 11 shows an N-channel transistor when the impurity concentration (Nb) of the channel portion 704 is about 5 × 10 ¹⁶ cm ⁻² and the thickness (Tsoi) of the buried oxide layer 702 is 100 nm. It is an example of the obtained sub-threshold characteristic.

Specifically, when a P-type polycrystalline silicon gate electrode is used and no bias voltage is applied to the substrate (ie, Vb = 0 V), as shown by a white circle plot in FIG. Type transistors exhibit very high threshold voltages. In contrast, when a P-type polycrystalline silicon gate electrode is used and a bias voltage of 2 V is applied to the substrate (that is, Vb = 0 V), as shown by a white triangle plot in FIG. Can be reduced to about 0.5V. Therefore, by utilizing this phenomenon, the substrate potential is set to 0 V when the transistor is turned off.
To increase the threshold voltage and realize characteristics with extremely low leakage current, while applying a positive substrate bias voltage when the transistor is on to lower the threshold voltage and achieve high driving capability. Can be.

Here, as shown by a black circle plot in FIG. 11, when a normal N-type polycrystalline silicon gate electrode is used, the transistor is on at a substrate potential of 0 V (Vb = 0 V), and the substrate is negative. The transistor is turned off by applying the potential of. For this reason, in the structure according to the related art, a circuit for generating the above-described negative potential and applying it to the substrate is indispensable, and as a result, there is a problem that the circuit occupation area increases. On the other hand, in the present embodiment, a positive potential is used, which is opposite to the above-described operation when the N-type polycrystalline silicon gate electrode is used in the related art, and thus a potential generating circuit is not required.

The structure shown in FIG. 10 described above has an SOI structure including a buried oxide layer 702. Alternatively, the same effect as described above can be obtained by applying the present embodiment to a normal bulk transistor that does not include a buried oxide layer. However, in the case of a bulk transistor, when the substrate potential is set to a positive potential, a positive potential difference occurs between the substrate and the source diffusion region, which may cause a leak current. However, the use of the SOI structure prevents generation of a leak current between the substrate and the source diffusion region even when a positive potential is applied to the substrate.

Although the effects of the present invention have been described above by taking an N-channel transistor as an example, the same effects can be obtained with a P-channel transistor as with an N-channel transistor.

As described above, according to the present embodiment, a polycrystalline silicon gate electrode having a conductivity type different from the conductivity type of the transistor is used, and the substrate potential is controlled by applying a positive bias voltage. , The threshold voltage of the transistor can be controlled. Further, by employing the SOI structure, generation of a leak current between the substrate and the source diffusion region can be prevented even when a positive potential is applied to the substrate.

In each of the embodiments of the present invention described above, as a constituent material of the metal gate electrode, for example, tungsten, tungsten silicide, molybdenum, molybdenum silicide, titanium, or titanium silicide may be selected. it can. Alternatively, the metal gate electrode may be formed to have a multilayer structure including a first layer made of titanium nitride or tungsten nitride and a second layer made of tungsten, molybdenum, or titanium.

Further, for example, a metal gate electrode is formed of tungsten or tungsten silicide, and a polycrystalline silicon gate electrode has a multilayer structure including a first layer of polycrystalline silicon and a second layer of tungsten or tungsten silicide. It may be formed to have. Alternatively, the metal gate electrode is formed of molybdenum or molybdenum silicide, and the polycrystalline silicon gate electrode is formed to have a multilayer structure including a first layer of polycrystalline silicon and a second layer of molybdenum or molybdenum silicide. You may. In other cases,
The metal gate electrode is formed of titanium or titanium silicide, and the polysilicon gate electrode has a multilayer structure including a first layer of polysilicon and a second layer of titanium or titanium silicide.

[0124]

As described above, according to the present invention, a semiconductor device in which transistors having different threshold voltages coexist can be easily formed without increasing the number of impurity implantation steps. Further, since the operation of the transistor, which used to be a negative substrate potential, can be controlled by using a positive substrate potential, it is not necessary to use a negative potential generation circuit that is conventionally included, and the occupied area is reduced. Can be reduced.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a graph showing sub-threshold characteristics of N-channel transistors according to the first, second, and third embodiments of the present invention.

FIG. 8 is a graph showing sub-threshold characteristics of N-channel transistors according to fourth and fifth embodiments of the present invention.

FIG. 9 is a graph showing sub-threshold characteristics of an N-channel transistor according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view illustrating a configuration of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 11 is a graph showing sub-threshold characteristics of an N-channel transistor according to a seventh embodiment of the present invention.

FIG. 12 is a graph showing a relationship between the thickness (horizontal axis) of a protective oxide film and a threshold voltage Vt (vertical axis) in an N-channel transistor.

FIG. 13 is a process sectional view illustrating the method of manufacturing the semiconductor device in the conventional technique.

[Explanation of symbols]

 101: P-type silicon substrate 102: N-type well region 103: P-type well region 104: element isolation region 105: gate oxide film 108: N-type polycrystalline silicon gate electrode 112 ... Metal (tungsten) gate electrode 113 ... P-type source / drain diffusion region 114 ... N-type source / drain diffusion region 201 ... P-type silicon substrate 202 ... N-type well region 203 ... · P-type well region 204 ··· element isolation region 205 ··· gate oxide film 208 ··· N-type polycrystalline silicon gate electrode 209 ··· gate oxide film 213 ··· metal (tungsten) gate electrode 214 ··· P-type source / drain diffusion region 215: N-type source / drain diffusion region 301: P-type silicon substrate 302: N-type wafer Region 303: P-type well region 304: Element isolation region 305: Gate oxide film 312: N-type polycrystalline silicon gate electrode 313: Metal (tungsten) gate electrode 314: P-type Source / drain diffusion region 315: N-type source / drain diffusion region 401: P-type silicon substrate 402: N-type well region 403: P-type well region 404: element isolation region 405 Gate oxide film 411: N-type polycrystalline silicon gate electrode 412: P-type polycrystalline silicon gate electrode 414: P-type source / drain diffusion region 415: N-type source / drain diffusion region 501 ..P-type silicon substrate 502 ・ ・ ・ N-type well region 503 ・ ・ ・ P-type well region 504 ・ ・ ・ Element isolation region 505 ・ ・ ・ Gate acid ... N-type polycrystalline silicon gate electrode 514... P-type polycrystalline silicon gate electrode 515... P-type source / drain diffusion region 516... N-type source / drain diffusion region 601. P-type silicon substrate 602: N-type well region 603: P-type well region 604: isolation region 606: N-type impurity diffusion region 607: P-type impurity diffusion region 609: gate Oxide film 615 ... N-type polycrystalline silicon gate electrode 616 ... P-type polycrystalline silicon gate electrode 617 ... P-type source / drain diffusion region 618 ... N-type source / drain diffusion region 701 ... P-type semiconductor substrate 702: buried oxide layer 703: element isolation region 704: channel region 705: source diffusion region 706: do In-diffusion region 707 gate oxide film 708 P-type polycrystalline silicon electrode 801 P-type silicon substrate 802 N-type well region 803 P-type well region 804 Element isolation Region 806: N-type impurity diffusion region 807: P-type impurity diffusion region 809: Gate oxide film 810: N-type polycrystalline silicon gate electrode 813: P-type source / drain diffusion region 814 ..N-type source / drain diffusion regions

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 617M 621

Claims (21)

[Claims] 1. A semiconductor device comprising: a first MOS transistor having a polycrystalline silicon gate electrode formed of polycrystalline silicon; and a second MOS transistor having a metal gate electrode formed of at least one kind of metal. A semiconductor device, wherein both the first and second MOS transistors are provided in the same well. 2. The semiconductor device according to claim 1, wherein an impurity concentration of a channel region of said first MOS transistor is set to a level different from an impurity concentration of a channel region of said second MOS transistor. 3. The semiconductor device according to claim 1, wherein said first and second MOS transistors are formed on a substrate having an SOI structure.
Alternatively, the semiconductor device according to 2. 4. The metal gate electrode of the second MOS transistor is formed of at least one material selected from the group consisting of tungsten, tungsten silicide, molybdenum, molybdenum silicide, titanium, and titanium silicide. Claims 1 to 3
The semiconductor device according to any one of the above. 5. A multilayer structure in which the metal gate electrode of the second MOS transistor includes a first layer made of titanium nitride or tungsten nitride and a second layer made of tungsten, molybdenum, or titanium. The semiconductor device according to any one of claims 1 to 3, comprising: 6. The first MOS transistor, wherein the metal gate electrode of the second MOS transistor is formed of tungsten or tungsten silicide, and wherein the polycrystalline silicon gate electrode of the first MOS transistor is formed of a first layer of polycrystalline silicon. 4. The semiconductor device according to claim 1, wherein the semiconductor device has a multilayer structure including tungsten or a second layer made of tungsten silicide. 7. The first MOS transistor, wherein the metal gate electrode of the second MOS transistor is formed of molybdenum or molybdenum silicide, and wherein the polycrystalline silicon gate electrode of the first MOS transistor is formed of a first layer of polycrystalline silicon. 4. The semiconductor device according to claim 1, wherein the semiconductor device has a multilayer structure including molybdenum or a second layer made of molybdenum silicide. 8. The first MOS transistor, wherein the metal gate electrode of the second MOS transistor is formed of titanium or titanium silicide, and the polycrystalline silicon gate electrode of the first MOS transistor is formed of a first layer of polycrystalline silicon. 4. The semiconductor device according to claim 1, having a multilayer structure including a second layer made of titanium or titanium silicide. 5. 9. A first MOS transistor having a gate electrode formed of polycrystalline silicon of a first conductivity type, a second MOS transistor having a gate electrode formed of polycrystalline silicon of a second conductivity type, and , And
A semiconductor device in which both the first and second MOS transistors are provided in the same well. 10. The semiconductor device according to claim 9, wherein an impurity concentration of a channel region of said first MOS transistor is set to a level different from an impurity concentration of a channel region of said second MOS transistor. 11. A step of forming an element isolation region in a semiconductor substrate, forming a first insulating film and a polycrystalline silicon film on the semiconductor substrate, and forming the first insulating film and the polycrystalline silicon film on a predetermined surface. Forming a gate electrode of a first MOS transistor by forming a metal film so as to cover the semiconductor substrate; patterning the metal film into a predetermined shape to form a second MOS transistor; Forming a gate electrode of a transistor. 12. The step of forming a gate electrode of the second MOS transistor, the step of removing the first insulating film other than the gate electrode of the first MOS transistor; Forming the metal film on the second insulating film, and patterning the second insulating film into the same shape when patterning the metal film into a predetermined shape. Item 12. The method for manufacturing a semiconductor device according to item 11. 13. The method according to claim 12, wherein the first insulating film and the second insulating film are formed of the same material and have substantially the same thickness. 14. The method according to claim 12, wherein the first insulating film and the second insulating film are formed from different materials. 15. The method according to claim 12, wherein the first insulating film and the second insulating film have different thicknesses. 16. A step of forming an element isolation region in a semiconductor substrate, a step of forming an insulating film and a polycrystalline silicon film on the semiconductor substrate, and a step of patterning the polycrystalline silicon film into a predetermined shape. A method of manufacturing a semiconductor device, comprising: depositing a metal film; and patterning the polycrystalline silicon film and the metal film into a predetermined shape to form a gate electrode. 17. The semiconductor device according to claim 11, wherein the metal film is formed of at least one material selected from the group consisting of tungsten, tungsten silicide, molybdenum, molybdenum silicide, titanium, and titanium silicide. A method for manufacturing a semiconductor device according to any one of the above. 18. The metal film according to claim 11, wherein the metal film is a multilayer film including a first layer made of titanium nitride or tungsten nitride, and a second layer made of tungsten, molybdenum, or titanium. A method for manufacturing a semiconductor device according to any one of the above. 19. A step of forming an element isolation region in a semiconductor substrate, a step of forming an insulating film and a first conductivity type polycrystalline silicon film on the semiconductor substrate, and a predetermined region of the polycrystalline silicon film. Changing the conductivity type of the first conductivity type to a second conductivity type opposite to the first conductivity type; and patterning the polycrystalline silicon films of the first conductivity type and the second conductivity type into a predetermined shape to form a gate. A method of manufacturing a semiconductor device, comprising: forming an electrode. 20. A step of forming an element isolation region in a semiconductor substrate, a step of forming an insulating film and an undoped polycrystalline silicon film on the semiconductor substrate, and a method of forming a conductive film in a first region of the polycrystalline silicon film. Setting the mold to a first conductivity type; and changing a conductivity type of a second region of the polycrystalline silicon film different from the first region to a second conductivity type opposite to the first conductivity type. Setting a conductivity type; patterning the first and second regions of the polycrystalline silicon film into a predetermined shape to form a gate electrode;
A method for manufacturing a semiconductor device, comprising: 21. The semiconductor device according to claim 11, wherein a plurality of MOS transistors are formed, and at least one channel region of the plurality of MOS transistors is subjected to an impurity doping process to change a work function of the channel region. A method for manufacturing a semiconductor device according to any one of the above.