JPH11243164A - Semiconductor plastic package and surface mounting method thereof - Google Patents

Semiconductor plastic package and surface mounting method thereof

Info

Publication number
JPH11243164A
JPH11243164A JP10042533A JP4253398A JPH11243164A JP H11243164 A JPH11243164 A JP H11243164A JP 10042533 A JP10042533 A JP 10042533A JP 4253398 A JP4253398 A JP 4253398A JP H11243164 A JPH11243164 A JP H11243164A
Authority
JP
Japan
Prior art keywords
package
package body
wiring board
main body
semiconductor plastic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10042533A
Other languages
Japanese (ja)
Inventor
Satoru Sakamoto
悟 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10042533A priority Critical patent/JPH11243164A/en
Publication of JPH11243164A publication Critical patent/JPH11243164A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Mounting Components In General For Electric Apparatus (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor plastic package and a surface-mounting method thereof, wherein the semiconductor plastic package can be enhanced in temporary fixing strength to a wiring board without spoiling assembling properties. SOLUTION: Recesses 13 are provided at least to a part of a base 11a of a package main body 11, an adhesive agent 14 is applied to the part where the recesses 13 are provided, the contacting surface of the package main body 11 with the adhesive agent 14 can be improved in area, and by having the package main body 11 fixed temporarily to a wiring board 12, the package main body 11 can be improved in adhesive strength with respect to the wiring board 12. The base 11a of the package main body 11 is kept high in flatness by its part other than the recesses 13, so that the package main body 11 will not produce nonconformities a process or sure mounting properties will not be spoiled.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、表面実装の際にパ
ッケージ本体と配線基板との間に接着剤を介在させてパ
ッケージ本体を配線基板上へ仮止めするようにした半導
体プラスチックパッケージ及びその表面実装方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor plastic package in which an adhesive is interposed between a package main body and a wiring board during surface mounting to temporarily fix the package main body on the wiring board and a surface thereof. Regarding implementation method.

【0002】[0002]

【従来の技術】従来より、半導体プラスチックパッケー
ジを配線基板へ実装するのに、配線基板のランド部に形
成される貫通孔にリード部を挿入し半田付けする挿入実
装と、配線基板のランド部にリード部先端を載置し半田
付けする表面実装とがある。表面実装は、挿入実装に比
べて実装密度が高く、スペース効率及び信号遅延時間の
短縮に有効な実装形態として知られている。
2. Description of the Related Art Conventionally, in mounting a semiconductor plastic package on a wiring board, a lead portion is inserted into a through hole formed in a land portion of the wiring board and soldered. There is surface mounting in which the tip of the lead portion is placed and soldered. The surface mounting has a higher mounting density than the insertion mounting, and is known as a mounting form effective for space efficiency and reduction of signal delay time.

【0003】半導体プラスチックパッケージの表面実装
方法は、配線基板のランド部にスクリーン印刷技術等を
用いて予め所定量の半田ペーストを塗布しておき、当該
ランド部にプラスチックパッケージのリード部を載置し
た後、半田を溶融させることによりランド部とリード部
とを半田付けする技術である。そこで、配線基板の両面
にプラスチックパッケージを実装する両面実装では、配
線基板の下面に位置するプラスチックパッケージの半田
付け前における配線基板からの脱落を防止するために、
パッケージ本体底面と配線基板との間を接着剤で固定
し、配線基板に対するプラスチックパッケージの仮止め
を行うのが通常である。
In a surface mounting method for a semiconductor plastic package, a predetermined amount of solder paste is applied in advance to a land portion of a wiring board using a screen printing technique or the like, and a lead portion of the plastic package is mounted on the land portion. Then, this technique is to solder the land and the lead by melting the solder. Therefore, in the double-sided mounting in which the plastic package is mounted on both sides of the wiring board, in order to prevent the plastic package located on the lower surface of the wiring board from falling off the wiring board before soldering,
Usually, the bottom of the package body and the wiring board are fixed with an adhesive, and the plastic package is temporarily fixed to the wiring board.

【0004】[0004]

【発明が解決しようとする課題】ところが、このプラス
チックパッケージと配線基板との間の仮止めの強度不足
が問題となっている。従来一般のプラスチックパッケー
ジでは、接着剤が塗布される面であるパッケージ本体底
面は平面で、当該パッケージの反り・ふくらみがあった
場合やモールド材への離型剤等による油脂分の付着等が
原因で、仮止め強度が不十分なものとなる。
However, there is a problem of insufficient strength of the temporary fixing between the plastic package and the wiring board. With conventional general plastic packages, the bottom surface of the package body, which is the surface to which the adhesive is applied, is a flat surface. Therefore, the temporary fixing strength becomes insufficient.

【0005】特開平4−370960号公報には、図4
に示すようにパッケージ本体1の底面1aに配線基板2
へ向かって突出する隆起部3をリード部5と略同等の長
さで形成し、パッケージ本体1と接着剤4との接触面積
を増大させて配線基板2への仮止め強度の向上を図って
いる。
Japanese Patent Laid-Open Publication No. Hei 4-370960 discloses FIG.
As shown in FIG.
The protruding portion 3 protruding toward the lead portion 5 is formed with a length substantially equal to that of the lead portion 5, and the contact area between the package body 1 and the adhesive 4 is increased to improve the temporary fixing strength to the wiring board 2. I have.

【0006】しかしながら、パッケージ本体底面1aに
隆起部3を設ける構成は、組み立て上の種々の問題を伴
うことになる。すなわち、第1に、何らかの理由により
隆起部3の一部が破損・欠落すると、その欠けらがダス
ト発生の原因となり、プロセス上大きな問題となる、第
2に、ICトレイ、キャリアテープ、搬送面等におい
て、パッケージ本体底面1aが平面でないとその位置決
めが困難となり高精度の加工ができない、第3に、プラ
スチックパッケージに規定されたスタンドオフという寸
法(配線基板2上からパッケージ本体底面1aまでの距
離)を確保することができず、場合によっては、実装時
に隆起部3によってリード部5とランド部6との接触が
阻害されて、正確な実装を行うことができない、等とい
う問題がある。
However, the configuration in which the raised portion 3 is provided on the package body bottom surface 1a involves various problems in assembling. That is, firstly, if a part of the raised portion 3 is damaged or dropped for some reason, the chipped portion causes dust and becomes a serious problem in the process. Second, the IC tray, carrier tape, transport surface And the like, if the package main body bottom surface 1a is not flat, it is difficult to position the package main body and high-precision processing cannot be performed. ) Cannot be ensured, and in some cases, there is a problem that contact between the lead portion 5 and the land portion 6 is hindered by the raised portion 3 during mounting, and accurate mounting cannot be performed.

【0007】本発明は、上述の問題に鑑みてなされ、組
立性を損なうことなく、配線基板との仮止め強度を高め
ることができる半導体プラスチックパッケージ及びその
表面実装方法を提供することを課題とする。
The present invention has been made in view of the above problems, and has as its object to provide a semiconductor plastic package and a surface mounting method thereof capable of increasing the strength of temporary fixing to a wiring board without impairing the assemblability. .

【0008】[0008]

【課題を解決するための手段】本発明は、パッケージ本
体の底面の少なくとも一部に複数の凹所を形成し、これ
ら凹所が形成される部分に接着剤を塗布しパッケージ本
体と接着剤との間の接触面積を大きくして配線基板との
仮止めを行うことにより、接着強度を高め、配線基板に
対するパッケージ本体の仮止め強度の向上を図る。ま
た、パッケージ本体の底面は上記凹所以外の面で平面度
が維持されるので、プロセス上の不都合が生じたり確実
な実装性が損なわれることはない。
According to the present invention, a plurality of recesses are formed in at least a part of a bottom surface of a package body, and an adhesive is applied to a portion where these recesses are formed to form a package body and an adhesive. The temporary contact with the wiring board is performed by increasing the contact area between them, thereby increasing the adhesive strength and improving the temporary fixing strength of the package body to the wiring board. In addition, since the flatness of the bottom surface of the package body is maintained at a surface other than the above-mentioned concave portion, there is no inconvenience in the process and the reliable mountability is not impaired.

【0009】[0009]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0010】図1は、本発明の実施の形態による半導体
プラスチックパッケージを示している。パッケージ本体
11はエポキシ系樹脂材料から成形され、内部に半導体
装置を有している。パッケージ本体11の側周部から突
出するリード部15は、パッケージ本体11の内部で半
導体装置の電極部とワイヤボンディングされ、当該リー
ド部15を介して図示しない配線基板上のランド部に半
導体装置を電気的に接続する。
FIG. 1 shows a semiconductor plastic package according to an embodiment of the present invention. The package body 11 is molded from an epoxy resin material and has a semiconductor device inside. A lead portion 15 protruding from a side peripheral portion of the package body 11 is wire-bonded to an electrode portion of the semiconductor device inside the package body 11, and the semiconductor device is connected to a land portion on a wiring board (not shown) via the lead portion 15. Make an electrical connection.

【0011】パッケージ本体11の底面11aの中心付
近には、図2に明示するように例えば直径0.1mm程
度の円形の凹所13が複数形成されている。凹所13
は、パッケージ本体11の底面成形用金型の金型成形面
の一部に凸部を設けることによって、容易に形成するこ
とができる。なお、凹所13の大きさ及び個数は適宜設
定可能で、パッケージ本体11の大きさや重さを勘案し
て決定される。また、凹所13の形成領域はパッケージ
本体11の底面11aの中心部付近だけにとどまらず、
底面11a全域に形成するようにしてもよい。
In the vicinity of the center of the bottom surface 11a of the package body 11, a plurality of circular recesses 13 having a diameter of, for example, about 0.1 mm are formed as shown in FIG. Recess 13
Can be easily formed by providing a projection on a part of the molding surface of the bottom molding die of the package body 11. The size and number of the recesses 13 can be set as appropriate, and are determined in consideration of the size and weight of the package body 11. Further, the formation area of the recess 13 is not limited to the vicinity of the center of the bottom surface 11 a of the package body 11,
It may be formed on the entire bottom surface 11a.

【0012】そこで、図3に示すようにパッケージ本体
11を接着剤(エポキシ系接着剤)14を仮止め剤とし
て用いて配線基板12に仮止めする際に、凹所13が形
成される部位を接着剤14の塗布面とすれば凹所13の
内部に接着剤が侵入してパッケージ本体11の底面11
aと接着剤14との間の接触面積が拡大することによっ
て投錨効果(アンカー効果)が高まり、パッケージ本体
11と接着剤14との接着強度の向上が図られる。これ
により、配線基板12からのパッケージ本体11の脱落
を防止することができる。また、微細なゴミ等が配線基
板12上にあっても、これを凹所13内に格納する機会
を与えて実装不良のリスクの低減を図ることができる。
Therefore, as shown in FIG. 3, when the package body 11 is temporarily fixed to the wiring board 12 using an adhesive (epoxy adhesive) 14 as a temporary fixing agent, a portion where the recess 13 is formed is formed. If the adhesive 14 is to be applied, the adhesive enters the recess 13 and the bottom surface 11 of the package body 11 is formed.
The anchoring effect (anchor effect) is increased by increasing the contact area between a and the adhesive 14, and the bonding strength between the package body 11 and the adhesive 14 is improved. Thereby, it is possible to prevent the package body 11 from falling off from the wiring board 12. Further, even if fine dust and the like are present on the wiring board 12, an opportunity to store the dust and the like in the recess 13 can be given to reduce the risk of mounting failure.

【0013】さらに、本実施の形態によれば、パッケー
ジ本体11の底面11aに凹所13を形成しているの
で、当該底面11aは凹所13以外の面で平面度を維持
することができ、これによりICトレイ、キャリアテー
プ、搬送面等におけるプラスチックパッケージの位置決
め精度が損なわれることはなく、また、配線基板12と
パッケージ本体底面11aとの間の距離(スタンドオ
フ)を従来と何ら変更せずに配線基板12への実装を可
能とし、確実な実装を行うことができる。
Further, according to the present embodiment, since the recess 13 is formed on the bottom surface 11a of the package body 11, the bottom surface 11a can maintain the flatness on a surface other than the recess 13. Thereby, the positioning accuracy of the plastic package on the IC tray, the carrier tape, the transfer surface, and the like is not impaired, and the distance (stand-off) between the wiring board 12 and the package body bottom surface 11a is not changed at all. The mounting on the wiring board 12 can be performed in a short time, and reliable mounting can be performed.

【0014】以上、本発明の実施の形態について説明し
たが、勿論、本発明はこれに限定されることなく、本発
明の技術的思想に基づいて種々の変更が可能である。
Although the embodiments of the present invention have been described above, the present invention is, of course, not limited thereto, and various modifications can be made based on the technical concept of the present invention.

【0015】例えば以上の実施の形態では、QFP(Q
uad Flatpack Package)タイプの
半導体プラスチックパッケージを例にして説明したが、
これだけに限らず、SOP(Small Outlin
e Package)やQFJ(Quad Flatp
ack J−leaded package)タイプな
どの他の表面実装型プラスチックパッケージについて、
本発明は適用可能である。
For example, in the above embodiment, QFP (Q
(Ud Flatpackage Package) type semiconductor plastic package has been described as an example.
Not limited to this, SOP (Small Outlin)
e Package) or QFJ (Quad Flatp)
For other surface mount plastic packages such as ack J-leaded package) type,
The present invention is applicable.

【0016】また、以上の実施の形態では、凹所13の
形状を円形としたが、これだけに限られず、方形状ある
いはランダムな形状等、種々の形状に形成しても同様な
効果を得ることが可能である。
In the above embodiment, the shape of the recess 13 is circular. However, the present invention is not limited to this, and the same effect can be obtained by forming the recess 13 into various shapes such as a square shape or a random shape. Is possible.

【0017】[0017]

【発明の効果】以上述べたように、本発明の半導体プラ
スチックパッケージ及びその表面実装方法によれば、パ
ッケージ本体の底面の少なくとも一部に複数の凹所を形
成したので、これら凹所が形成される部分に接着剤を塗
布して配線基板との仮止めを行うことにより、パッケー
ジ本体と接着剤との間の接触面積を大きくして、配線基
板に対するパッケージ本体の仮止め強度を向上させるこ
とができる。また、パッケージ本体の底面は凹所以外の
面で平面度を維持することができるので、プロセス上で
の不都合が生じたり実装の確実性が損なわれることはな
い。
As described above, according to the semiconductor plastic package and the surface mounting method of the present invention, since a plurality of recesses are formed in at least a part of the bottom surface of the package body, these recesses are formed. By applying an adhesive to the portion to be temporarily fixed to the wiring board, the contact area between the package body and the adhesive can be increased, and the temporary fixing strength of the package body to the wiring board can be improved. it can. In addition, since the bottom surface of the package body can maintain the flatness on the surface other than the concave portion, there is no inconvenience in the process and the reliability of the mounting is not impaired.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態における半導体プラスチッ
クパッケージの底面を示す斜視図である。
FIG. 1 is a perspective view showing a bottom surface of a semiconductor plastic package according to an embodiment of the present invention.

【図2】図1におけるA部の拡大図である。FIG. 2 is an enlarged view of a portion A in FIG.

【図3】同作用を示す断面図である。FIG. 3 is a sectional view showing the same operation.

【図4】従来の半導体プラスチックパッケージの実装形
態を示す断面図である。
FIG. 4 is a cross-sectional view showing a mounting form of a conventional semiconductor plastic package.

【符号の説明】[Explanation of symbols]

11………パッケージ本体、11a………底面、12…
……配線基板、13………凹所、14………接着剤、1
5………リード部。
11 Package body, 11a Bottom surface, 12
…… Wiring board, 13 …… Recess, 14 …… Adhesive, 1
5 ... Lead part.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 FI H05K 7/12 H05K 7/12 M ──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. 6 Identification code FI H05K 7/12 H05K 7/12 M

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 内部に半導体装置を有するパッケージ本
体と、このパッケージ本体の側周部から突出し前記パッ
ケージ本体の底面と対向して配置される配線基板上に表
面実装されるリード部とを備えた半導体プラスチックパ
ッケージにおいて、 前記パッケージ本体の底面の少なくとも一部に複数の凹
所を形成したことを特徴とする半導体プラスチックパッ
ケージ。
A package body having a semiconductor device therein; and a lead portion projecting from a side peripheral portion of the package body and being surface-mounted on a wiring board arranged to face a bottom surface of the package body. A semiconductor plastic package, wherein a plurality of recesses are formed in at least a part of a bottom surface of the package body.
【請求項2】 前記複数の凹所は、前記パッケージ本体
の底面成形用金型の金型成形面の少なくとも一部に設け
られる複数の凸部により形成されることを特徴とする請
求項1に記載の半導体プラスチックパッケージ。
2. The method according to claim 1, wherein the plurality of recesses are formed by a plurality of protrusions provided on at least a part of a mold forming surface of a mold for forming a bottom surface of the package body. Semiconductor plastic package as described.
【請求項3】 内部に半導体装置を有するパッケージ本
体と、このパッケージ本体の側周部から突出し前記パッ
ケージ本体の底面と対向して配置される配線基板上に表
面実装されるリード部とを備え、前記底面と前記配線基
板上との間に接着剤を介在させて前記パッケージ本体を
前記配線基板に仮止めする半導体プラスチックパッケー
ジの表面実装方法において、 前記底面の前記接着剤が塗布される部分に複数の凹所を
形成しておくことを特徴とする半導体プラスチックパッ
ケージの表面実装方法。
3. A package body having a semiconductor device therein, and a lead portion projecting from a side peripheral portion of the package body and being surface-mounted on a wiring board disposed to face a bottom surface of the package body, In a surface mounting method of a semiconductor plastic package, wherein an adhesive is interposed between the bottom surface and the wiring substrate to temporarily fix the package body to the wiring substrate, a plurality of portions of the bottom surface to which the adhesive is applied are provided. A surface mounting method for a semiconductor plastic package, wherein a recess is formed in advance.
JP10042533A 1998-02-24 1998-02-24 Semiconductor plastic package and surface mounting method thereof Pending JPH11243164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10042533A JPH11243164A (en) 1998-02-24 1998-02-24 Semiconductor plastic package and surface mounting method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10042533A JPH11243164A (en) 1998-02-24 1998-02-24 Semiconductor plastic package and surface mounting method thereof

Publications (1)

Publication Number Publication Date
JPH11243164A true JPH11243164A (en) 1999-09-07

Family

ID=12638728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10042533A Pending JPH11243164A (en) 1998-02-24 1998-02-24 Semiconductor plastic package and surface mounting method thereof

Country Status (1)

Country Link
JP (1) JPH11243164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036517A (en) * 1998-06-09 2000-02-02 Stmicroelectronics Inc Street decrease for flip chip package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000036517A (en) * 1998-06-09 2000-02-02 Stmicroelectronics Inc Street decrease for flip chip package
JP4610031B2 (en) * 1998-06-09 2011-01-12 エスティーマイクロエレクトロニクス,インコーポレイテッド Stress reduction for flip chip packages

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