JPH11233764A - Insulated gate type bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise a dielectric strength with a difference compensation of a gate voltage transfer time by a method wherein a CR time constant, that is, the product of a capacitance value per unit area of an insulation film of each cell multiplied by a resistance value of each gate electrode, of a cell far from a gate pad is set equal to or smaller than that of a cell near the gate pad. SOLUTION: For example, an a-dimension of an insulation film of a cell 13 near a gate pad 11 is larger than that of a cell 14 far from the gate pad 11 (A<B). Here, when a voltage is applied to the gate pad 11, the voltage is conducted to each cell through a gate wiring 12. At this time, the gate voltage of the cell 13 near the gate pad is conducted quicker than that of the cell 14 far from the gate pad. However, the cell 13 needs longer time for charging the insulation film, because capacitance of the insulation film of the cell 13 is larger than that of the cell 14. Meanwhile the cell 14 has small capacitance and so the short charging time for the insulation film, a time from an application of the gate voltage till a starting of current can be compensated between the cell 13 and the cell 14, and current unbalance can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate transistor (hereinafter referred to as IGBT).

[0002]

2. Description of the Related Art In recent years, IGBTs have rapidly spread as switching devices due to their high speed and high output characteristics. As shown in FIG. 1, the structure is such that an n ⁺ layer is formed on a p ⁺ substrate, an n ⁻ layer is further formed thereon, and ap ⁺ layer is selectively formed on the surface of the n ⁻ layer. An n-layer is selectively formed on the surface in the p-layer region. An insulating film is formed on the surface of the p-layer sandwiched between the n ⁻ layer and the n-layer as a channel region, and a gate electrode is further formed on the insulating film.
The structure has an emitter electrode commonly connected to the layer and the n-layer, and a collector electrode connected to the p ⁺ silicon substrate.

[0003] As shown in FIG. 2, the IGBT chip includes a conduction region, a gate pad, and a gate wiring. The conduction region is formed by integrating the IGBT unit cells shown in FIG. When a positive voltage is applied to the gate pad with a positive voltage applied to the collector electrode of the IGBT and an emitter electrode grounded, a voltage is applied to the gate electrode. When the gate voltage exceeds the threshold voltage, the voltage is sandwiched between the p layer and the n layer. A channel is formed in the region, and electrons flow into the n ⁻ layer through the channel. Then, holes proportional to the electron current are injected from the p ⁺ silicon substrate into the n ⁻ layer by the electron current, the conductivity of the n ⁻ layer is modulated, the resistance is reduced, and a low on-voltage of the IGBT is realized.

In recent years, the output of IGBTs has been increased by miniaturizing the cell size and reducing the thickness of the gate oxide film to improve the performance.

[0005]

The above-mentioned conventional IGB
In T, the basic cells shown in FIG. 1 are arranged in order, and at the corner of the gate pad or the outermost cell of the chip, the horizontal length of the thickest portion of the insulating film is changed only for the purpose of size adjustment. The dimensions were constant elsewhere.

The voltage applied to the gate pad is transmitted to the gate electrode of each cell through the gate wiring. Here, comparing the cells closer to the gate pad and the cells farther from the gate pad or the same cell closer to the gate pad and farther from the gate pad, the cell closer to the gate pad and closer to the gate pad in the same cell have a higher gate voltage. The current is transmitted quickly, and the current flows quickly when the switch is on, and the current is interrupted quickly when the switch is off.

[0007] Due to the difference in the gate voltage transmission time, current imbalance may occur and the IGBT may be destroyed by current concentration.

An object of the present invention is to provide an IGBT having a high breakdown strength by correcting a difference in gate voltage transmission time in order to solve this problem in the IGBT.

[0009]

To achieve the above object, the present invention provides a first region of a first conductivity type having a high impurity concentration, and a second region having a high impurity concentration formed on the first region. A second region of the conductivity type, a third region of the second conductivity type having a lower impurity concentration than the second region formed on the second region, and a first conductivity type selectively formed on the surface of the third region. The fourth area of
A fifth region of the second conductivity type selectively formed on the surface of the fourth region, and an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel. In an insulated gate bipolar transistor having a gate electrode provided on the insulating film, the cell per unit area of the insulating film of each cell and the CR time constant obtained by multiplying the resistance of the gate electrode by a cell far from the gate pad are gated. This is equivalent to or smaller than the cell close to the pad.

The transmission time of the gate voltage is determined by the CR time constant multiplied by the capacitance of the insulating film per unit area and the resistance of the gate electrode. Increasing the lateral length of the thickest portion of the insulating film in the insulating film increases the capacitance of the entire insulating film.
Conversely, when the lateral length of the thickest portion of the insulating film is reduced, the capacitance of the entire insulating film is reduced. Here, when the lateral length of the thickest portion of the insulating film of the cell far from the gate pad is equal to or smaller than the lateral length of the thickest portion of the insulating film of the cell closer to the gate pad than that cell. The time for charging the insulating film is shortened, and the time from when the gate voltage is applied to when the current starts to flow is shortened, and the transmission time of the gate voltage can be corrected. Further, even if the horizontal length of the thickest portion of the insulating film in the same cell becomes smaller as it is farther from the gate pad, the vertical length of the thickest portion of the insulating film in the cell further farther from the gate pad is made longer than that cell. Even if the vertical length of the thickest portion of the insulating film in the same cell is equal to or greater than the vertical length of the thickest portion of the insulating film of the closer cell, even if the vertical length of the thickest portion of the insulating film in the same cell is farther from the gate pad, Similar effects can be obtained.

Similarly, the resistance increases as the horizontal distance of the gate electrode increases, and the resistance can be increased even if the thickness in the vertical direction is reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing embodiments.

FIGS. 3 to 10 show the shape and cross-sectional structure of the gate pad and each cell of the IGBT chip. In FIG. 3, the cell 13 closer to the gate pad 11 has a larger a-size of the insulating film than the cell 14 farther (A <
B). Here, when a voltage is applied to the gate pad 11, the voltage is transmitted to each cell through the gate wiring 12. At this time, the gate voltage is transmitted earlier in the cell 13 closer to the gate pad than in the cell 14 farther from the gate pad. However, since the capacity of the insulating film of the cell 13 is larger than that of the cell 14, it takes time to charge the insulating film. On the other hand, since the capacity of the cell 13 is small, the charging time of the insulating film is short, and thus the gate voltage is applied. The time until the current starts to flow can be corrected between the cell 13 and the cell 14, and the current imbalance can be eliminated. Similarly, in FIG. 4, in the same cell 15, the dimension a of the insulating film is larger near the gate pad (A <B). It is clear that the same effect can be obtained with this structure.

Further, in FIG. 5, the cell 13 near the gate pad 11 has a smaller d-size of the insulating film than the cell 14 far from it (A> B). Comparing the capacities of the cell 13 and the cell 14, it can be seen that the cell 13 having a smaller d dimension is larger, and this structure can also eliminate the current imbalance.

Similarly, in FIG. 6, in the same cell 15, the d dimension of the insulating film is larger near the gate pad (A> B). It is clear that the same effect can be obtained with this structure.

FIG. 7 shows that the cell 13 near the gate pad 11 has a longer overall length of the gate electrode in the lateral direction than the cell 14 far from it (A + B <C). Here, the gate pad 11
When a voltage is applied to the cell, the voltage is transmitted to each cell through the gate wiring 12. At this time, the gate voltage is transmitted earlier in the cell 13 closer to the gate pad than in the cell 14 farther from the gate pad. However, since the resistance of the gate electrode of the cell 13 is larger than that of the cell 14, it takes time to transmit the voltage. On the other hand, since the resistance of the gate electrode of the cell 13 is small, the time of transmitting the voltage is short. The time until the flow starts can be corrected between the cell 13 and the cell 14, and the imbalance of the current can be eliminated. Similarly, in FIG. 8, the overall length of the gate electrode in the same cell 15 closer to the gate pad is longer in the horizontal direction (A +
B <C). This structure can be obtained by forming a slit in the gate electrode, and it is clear that the same effect as above can be obtained. FIG. 9 shows cell 1 near gate pad 11.
In No. 3, the vertical thickness of the gate electrode is smaller than that of the far cell 14 (A> B). If the gate electrode is thin, the resistance of the gate electrode increases, and a desired effect can be obtained. Similarly, in FIG. 10, the vertical thickness of the gate electrode in the same cell 15 near the gate pad is smaller (A>
B). Also in this structure, the resistance of the gate electrode is increased, and the same effect can be obtained.

[0017]

As can be seen from the above description, according to the present invention, the CR time constant obtained by multiplying the capacitance of the insulating film per unit area and the gate resistance is set so that a cell far from the gate pad is equal to or smaller than a cell close to the gate pad. An IGBT with a large breakdown voltage can be eliminated by reducing the size and increasing the distance from the gate pad closer to the gate pad than the distance farther from the gate pad in the same cell.
Can be obtained.

[Brief description of the drawings]

FIG. 1 is a general sectional view of an IGBT of the present invention.

FIG. 2 is an IGBT chip.

FIG. 3 is an IGBT chip and a cross-sectional view thereof.

FIG. 4 is an IGBT chip and a cross-sectional view thereof.

FIG. 5 is an IGBT chip and a cross-sectional view thereof.

FIG. 6 is an IGBT chip and a cross-sectional view thereof.

FIG. 7 is an IGBT chip and a cross-sectional view thereof.

FIG. 8 is an IGBT chip and a cross-sectional view thereof.

FIG. 9 is an IGBT chip and a cross-sectional view thereof.

FIG. 10 is an IGBT chip and a cross-sectional view thereof.

[Explanation of symbols]

1 ... p ⁺ substrate, 2 ... n ⁺ layer, 3 ... n ^- layer, 4 ... p layer, 5
... N layer, 6 insulating film, 7 gate electrode, 8 emitter electrode, 9 collector electrode, 10 conductive region, 11 gate pad, 12 gate wiring, 13 cell close to gate pad, 14 gate Cells far from the pad, 15 ... cells.

Claims (9)

[Claims] A first region of a first conductivity type having a high impurity concentration, a second region of a second conductivity type having a high impurity concentration formed on the first region, and a first region formed on the second region of the first conductivity type. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. In the insulated gate bipolar transistor having, the CR time constant obtained by multiplying the capacitance per unit area of the insulating film and the resistance of the gate electrode is such that a cell far from the gate pad is equal to or smaller than a cell near the gate pad. Gate type bipolar transistor. 2. A first region of a first conductivity type having a high impurity concentration, a second region of a second conductivity type having a high impurity concentration formed on the first region, and a second region formed on the second region of a high impurity concentration. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. An insulated gate bipolar transistor, comprising: a cell having a thickest portion of an insulating film in a lateral direction in each cell, wherein a cell far from the gate pad is equal to or smaller than a cell near the gate pad. Bipolar transistor. 3. A first region of a first conductivity type having a high impurity concentration, a second region of a second conductivity type having a high impurity concentration formed on the first region, and a second region formed on the second region of the first conductivity type. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. 1. An insulated gate bipolar transistor comprising: an insulating gate type bipolar transistor, wherein the lateral length of the thickest portion of the insulating film in the same cell decreases as the distance from the gate pad increases. 4. A first region of a first conductivity type having a high impurity concentration, a second region of a second conductivity type having a high impurity concentration formed on the first region, and a first region formed on the second region. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. In the insulated gate bipolar transistor having the thickest portion of the insulating film of each cell, the cell in the vertical direction is far from the gate pad, and the cell is equal to or larger than the cell near the gate pad. Bipolar transistor. 5. A first region of a first conductivity type with a high impurity concentration, a second region of a second conductivity type with a high impurity concentration formed on the first region, and a second region formed on the second region of a high impurity concentration. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. The insulated gate bipolar transistor having the same cell, wherein the vertical length of the thickest portion of the insulating film in the same cell increases as the distance from the gate pad increases. 6. A first region of a first conductivity type having a high impurity concentration, a second region of a second conductivity type having a high impurity concentration formed on the first region, and a first region formed on the second region. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. An insulated gate bipolar transistor having an insulated gate bipolar transistor, wherein a cell having a total length in the lateral direction of a gate electrode in each cell is equal to or smaller than a cell near the gate pad. . 7. A first region of a first conductivity type having a high impurity concentration, a second region of a second conductivity type having a high impurity concentration formed on the first region, and a first region formed on the second region. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. An insulated gate type bipolar transistor comprising: an insulated gate type bipolar transistor, wherein the overall length of a gate electrode in the same cell in the lateral direction is smaller as being farther from the gate pad. 8. A first region of a first conductivity type having a high impurity concentration, a second region of a second conductivity type having a high impurity concentration formed on the first region, and a first region formed on the second region. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. An insulated gate bipolar transistor comprising: an insulated gate bipolar transistor, wherein in each cell, a cell in which a gate electrode has a vertical thickness far from a gate pad is equal to or thicker than a cell near a gate pad. 9. A first region of a first conductivity type with a high impurity concentration, a second region of a second conductivity type with a high impurity concentration formed on the first region, and a second region formed on the second region of a high impurity concentration. A third region of the second conductivity type having a lower impurity concentration than the two regions, a fourth region of the first conductivity type selectively formed on the surface of the third region, and selectively formed on the surface of the fourth region. A fifth region of the second conductivity type, an insulating film provided on the third region such that a portion sandwiched between the third region and the fifth region becomes a channel, and a gate electrode provided on the insulating film. 1. An insulated gate bipolar transistor, comprising: the same cell, wherein the distance in the lateral direction of the gate electrode in the same cell increases as the distance from the gate pad increases.