JPH11233488A - Surface machining method - Google Patents

Surface machining method

Info

Publication number
JPH11233488A
JPH11233488A JP10030865A JP3086598A JPH11233488A JP H11233488 A JPH11233488 A JP H11233488A JP 10030865 A JP10030865 A JP 10030865A JP 3086598 A JP3086598 A JP 3086598A JP H11233488 A JPH11233488 A JP H11233488A
Authority
JP
Japan
Prior art keywords
steps
etching
plasma
sample
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10030865A
Other languages
Japanese (ja)
Other versions
JP4061691B2 (en
Inventor
Tetsuo Ono
哲郎 小野
Hiroshi Miyazaki
博史 宮崎
Ryoji Hamazaki
良二 浜崎
Tokuo Kure
得男 久礼
Takafumi Tokunaga
尚文 徳永
Masayuki Kojima
雅之 児島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP03086598A priority Critical patent/JP4061691B2/en
Publication of JPH11233488A publication Critical patent/JPH11233488A/en
Application granted granted Critical
Publication of JP4061691B2 publication Critical patent/JP4061691B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress the drop of the etching speed of polycrystalline silicon and an etching remainder, and to hold a high selection ratio against an oxide film when etching a semiconductor through the use of a plasma. SOLUTION: In a surface machining by using a plasma, a processing from the start to the end is divided into a plurality of steps. The steps are divided into a first half whose speed ratio with a base substance terminating machining is comparatively small but machining speed is large, and a latter half whose machining speed ratio is comparatively large. High frequency voltage is repetitively applied in on/off periods with at least one of he steps in the latter half.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は表面加工方法に係
り、特にプラズマを用いて半導体素子等が形成される試
料の表面をエッチングするのに好適な表面加工方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface processing method, and more particularly to a surface processing method suitable for etching the surface of a sample on which a semiconductor element or the like is formed using plasma.

【0002】[0002]

【従来の技術】半導体素子のエッチングに広く用いられ
ている装置は、プラズマを利用する装置である。ここで
はそのうちの一つであるECR(電子サイクロトロン共鳴)
方式と呼ばれる装置を例に取り従来技術を説明する。こ
の方式では、外部より磁場を印加した真空容器中でマイ
クロ波によりプラズマを発生する。磁場によりプラズマ
中の電子にはローレンツ力が働くために、電子は磁力線
の回りを回転運動する(サイクロトロン運動)。この回
転の周波数とマイクロ波の周波数を同じにすると共鳴が
生じ、効率良くプラズマを発生できる。試料に入射する
イオンを加速するために、試料には高周波電圧が印加さ
れる。プラズマとなるガスには塩素やフッ素などのハロ
ゲンガスが用いられる。
2. Description of the Related Art An apparatus widely used for etching a semiconductor element is an apparatus utilizing plasma. Here, one of them, ECR (Electron Cyclotron Resonance)
The prior art will be described using an apparatus called a system as an example. In this method, plasma is generated by microwaves in a vacuum vessel to which a magnetic field is externally applied. Since Lorentz force acts on electrons in the plasma due to the magnetic field, the electrons rotate around the lines of magnetic force (cyclotron motion). When the frequency of the rotation is equal to the frequency of the microwave, resonance occurs, and plasma can be generated efficiently. A high frequency voltage is applied to the sample to accelerate ions incident on the sample. A halogen gas such as chlorine or fluorine is used as a gas to be plasma.

【0003】このような装置の高精度化を図るために、
特開平6-151360号公報に記載の技術が知られている。本
技術は、試料に印加する高周波電圧のオン−オフを間欠
的に制御することにより、エッチングしたい物質である
Siと下地酸化膜との選択比を高くしている。
In order to improve the accuracy of such a device,
The technique described in JP-A-6-151360 is known. This technology is a substance to be etched by intermittently controlling on-off of a high-frequency voltage applied to a sample.
The selectivity between Si and the underlying oxide film is increased.

【0004】[0004]

【発明が解決しようとする課題】近年の半導体素子の微
細化に伴い、MOS(metal oxide semiconductor)トランジ
スタではゲート酸化膜の厚さが薄くなり、256M以降のメ
モリ素子では6nm以下になる。このようにゲート酸化膜
の薄膜化が進むと素子のエッチング工程では、これまで
以上の選択比が必要になる。しかし、選択比を高くする
と一般には加工速度が遅くなりかつエッチ残りも生じ易
くなるという問題がある。
With the recent miniaturization of semiconductor devices, the thickness of a gate oxide film is reduced in a metal oxide semiconductor (MOS) transistor, and is reduced to 6 nm or less in a memory device of 256M or later. As the gate oxide film becomes thinner in this manner, a higher selectivity is required in the element etching process. However, when the selection ratio is increased, there is a problem that the processing speed is generally slow and an etch residue is liable to occur.

【0005】本発明の目的は、プラズマを用いた半導体
のエッチングにおいて、多結晶シリコンのエッチ速度の
低下とエッチ残りの発生を抑え、かつ高い対酸化膜選択
比を保つことのできる表面加工方法を提供することにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a surface processing method capable of suppressing a decrease in the etching rate of polycrystalline silicon and the occurrence of an unetched residue, and maintaining a high selectivity with respect to an oxide film in etching a semiconductor using plasma. To provide.

【0006】[0006]

【課題を解決するための手段】上記目的は、表面加工に
おいて、表面加工開始から終了までを複数のステップに
分けて、かつそれらのステップを加工を終了させる下地
物質との加工速度比が比較的小さい前半と、比較的大き
い後半の2つに分け、少なくとも後半のステップの一つ
で、高周波電圧をオンとオフの期間に分け繰り返し試料
に印加することにより、達成される。
SUMMARY OF THE INVENTION It is an object of the present invention to divide a surface process into a plurality of steps from the start to the end of the surface processing, and the processing speed ratio between the base material and the base material which ends the processing is relatively small. This is achieved by dividing the device into two parts, a small first half and a relatively large second half, and applying the high-frequency voltage to the sample repeatedly in at least one of the second half steps during the ON and OFF periods.

【0007】[0007]

【発明の実施の形態】〔実施例1〕以下、本発明の実施
例を図により説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings.

【0008】図1(a)は本発明を適用するプラズマエッ
チング装置の全体構成図である。マイクロ波電源101
から導波管102と導入窓103を介して真空容器10
4内にマイクロ波が導入される。導入窓103の材質は
石英、セラミックなど電磁波を透過する物質である。真
空容器104の回りには電磁石105が設置されてお
り、磁場強度はマイクロ波の周波数と電子のサイクロト
ロン周波数が同じになるように設定されて、たとえば周
波数が2.45GHzならば磁場強度は875Gaussである。この
磁場強度で高密度のプラズマ106が発生する。試料1
07は試料台108の上に設置される。試料に入射する
イオンを加速するために、高周波電源109が試料台1
08に接続されている。高周波電源の周波数に特に制限
はないが、通常では周波数は200kHzから20MHzの
範囲が実用的である。高周波電源109の電圧波形11
0は図1(b)のように、オンとオフの期間を繰り返し制
御できるようになっている。
FIG. 1A is an overall configuration diagram of a plasma etching apparatus to which the present invention is applied. Microwave power supply 101
From the vacuum vessel 10 through the waveguide 102 and the introduction window 103
A microwave is introduced into 4. The material of the introduction window 103 is a material that transmits electromagnetic waves, such as quartz or ceramic. An electromagnet 105 is provided around the vacuum vessel 104, and the magnetic field strength is set so that the microwave frequency and the electron cyclotron frequency are the same. For example, if the frequency is 2.45 GHz, the magnetic field strength is 875 Gauss . The high-density plasma 106 is generated by this magnetic field intensity. Sample 1
07 is set on the sample stage 108. In order to accelerate ions incident on the sample, the high-frequency power supply 109
08. There is no particular limitation on the frequency of the high-frequency power supply, but usually the frequency is practically in the range of 200 kHz to 20 MHz. Voltage waveform 11 of high frequency power supply 109
0 is such that the ON and OFF periods can be repeatedly controlled as shown in FIG.

【0009】図2には、図1の装置を用いて半導体表面
のラインとスペースからなる微細パタンを2つのステッ
プに分けてエッチングした場合の断面形状の時間変化を
示す。エッチングした素子の構造は、シリコン基板20
1上のゲート酸化膜202の厚さが4nm、多結晶シリコ
ン層203の厚さ300nm、レジスト204の厚さが1
μmでスペースの幅は0.35μmである。図2(a)は初期状
態、(b)はステップ1終了後、(c)はステップ2終了後を
それぞれ示す。ステップ1では、まず多結晶シリコン2
03をエッチングする。ステップ1は加工の主要部分を
占め、以後メインエッチと呼ぶ。エッチングのガスはCl
2(75 sccm)と酸素(5 sccm)で圧力を0.4Paとした。マイ
クロ波電源101の出力を400Wとした。高周波電源
109の周波数は、この場合、800k Hzである。この
ステップでは多結晶シリコンを高速かつエッチ残りがな
いようにエッチングすることが目的なので、高周波電源
109の出力は連続で80Wにしている。多結晶シリコン
のエッチ速度は高周波の電力と共に増加する。また、エ
ッチ残りは多結晶シリコン上の自然酸化膜などエッチン
グしにくい異物がマスクとなって、その下の部分がエッ
チ残りとなる。このような異物も高周波の電力を上げる
と除去される。 従って、加工速度を上げてエッチ残り
が出ないようにするためには、ある程度大きい高周波電
力が必要となる。しかし高周波電力が大きいと下地酸化
膜との選択比が低くなるために、このままエッチングを
進めると下地酸化膜がエッチングされて、素子の不良に
つながる。これを防ぐためには、ある段階で選択比が高
い条件に切り替えてやれば良い。ここではステップ2で
高周波電圧の振幅は変えずにオンオフ制御した。オンオ
フの繰り返し周波数は1kHzとした。このように、メイン
エッチ後の比較的選択比が高いエッチングを以後オーバ
エッチと呼ぶ。ステップ2で高周波電源をオンオフ制御
することにより、図2(c)に示すように、エッチ残りな
くかつ下地酸化膜を十分残して加工が可能になる。
FIG. 2 shows a change over time in the cross-sectional shape when a fine pattern consisting of lines and spaces on a semiconductor surface is etched in two steps using the apparatus of FIG. The structure of the etched element is a silicon substrate 20
1 has a thickness of 4 nm, a polycrystalline silicon layer 203 has a thickness of 300 nm, and a resist 204 has a thickness of 1 nm.
In μm, the width of the space is 0.35 μm. 2A shows the initial state, FIG. 2B shows the state after step 1, and FIG. 2C shows the state after step 2. In step 1, first, polycrystalline silicon 2
03 is etched. Step 1 occupies a major part of the processing and is hereafter referred to as the main etch. Etching gas is Cl
The pressure was 0.4 Pa with 2 (75 sccm) and oxygen (5 sccm). The output of the microwave power supply 101 was 400 W. The frequency of the high-frequency power supply 109 is 800 kHz in this case. In this step, the output of the high-frequency power supply 109 is continuously set to 80 W because the purpose is to etch the polycrystalline silicon at high speed so that no etching remains. The etch rate of polycrystalline silicon increases with high frequency power. In addition, foreign matter that is difficult to etch, such as a natural oxide film on polycrystalline silicon, is used as a mask for the remaining etch, and the portion below the remaining etch residue. Such foreign matter is also removed by increasing the high frequency power. Therefore, in order to increase the processing speed so that no etch residue appears, a relatively high frequency power is required. However, if the high-frequency power is large, the selectivity with respect to the underlying oxide film becomes low. Therefore, if the etching is continued as it is, the underlying oxide film is etched, which leads to a defective element. In order to prevent this, it is only necessary to switch to a condition having a high selection ratio at a certain stage. Here, in step 2, on / off control was performed without changing the amplitude of the high frequency voltage. The ON / OFF repetition frequency was 1 kHz. Such etching having a relatively high selectivity after the main etch is hereinafter referred to as overetch. By performing on / off control of the high-frequency power supply in step 2, as shown in FIG. 2 (c), it becomes possible to process without leaving an etch residue and leaving a sufficient base oxide film.

【0010】ステップ1とステップ2の切り替えは、Si
原子の発光強度をモニターし、発光強度が落ちはじめた
ら、あるいは発光強度曲線の変極点(2次微分が0にな
る点)で切り替えるとよい。また、下地酸化膜が薄い場
合は、あらかじめ多結晶シリコンのエッチングが終了す
る時間を測定しておき、その少し手前で切り替える方法
でも良い。
The switching between step 1 and step 2 is performed by using Si
It is advisable to monitor the emission intensity of the atoms and switch the emission intensity when the emission intensity starts to decrease or at the inflection point of the emission intensity curve (point at which the second derivative becomes zero). If the underlying oxide film is thin, a method may be used in which the time when the etching of the polycrystalline silicon is completed is measured in advance and the switching is performed slightly before the time.

【0011】選択比を高くするためには、単に電力を下
げる方法もある。しかし、下地酸化膜202が4nmのよ
うに薄くなるとより選択比を上げる必要があり、単に電
力を下げると多結晶シリコンのエッチ速度が低下してエ
ッチ残りも生じ易くなる。本発明のように高周波電源1
09の出力をオンオフ制御すると、多結晶シリコンのエ
ッチ速度は落とさず選択比を上げることができる。その
様子を図3に示す。図3の横軸は多結晶シリコンのエッ
チ速度で縦軸は多結晶シリコンと酸化膜の選択比であ
る。図中点Aは連続80Wの値で、曲線301は連続電力の
値を小さくした場合、曲線302は電圧振幅一定でオン
オフ制御してそのデューティー比(オン−オフの1周期
に占めるオン期間の割合)を小さくした場合を示す。高
周波をオンオフ制御する方が連続電力と比較して同じ多
結晶シリコンエッチ速度でも選択比が高くなる。この原
因は以下のように推定できる。酸素あるいは酸素を含む
反応生成物が付着すると酸化膜のエッチ速度は低下す
る。一方、多結晶シリコンのエッチ速度は酸素の付着量
がある程度までは低下しない。高周波電源をオンオフ制
御するとオフ期間にはイオンは加速されず、酸素あるい
は反応生成物の堆積だけが生じる。オン期間にはイオン
が加速され表面に入射するが、オフ期間の堆積物に阻害
されて酸化膜のエッチ速度が低下して選択比があがる。
In order to increase the selection ratio, there is a method of simply lowering the power. However, when the thickness of the underlying oxide film 202 is reduced to 4 nm, it is necessary to further increase the selection ratio. If the power is simply reduced, the etching speed of the polycrystalline silicon is reduced, and the remaining etching tends to occur. High frequency power supply 1 as in the present invention
The on / off control of the output of 09 can increase the selectivity without decreasing the etching speed of the polycrystalline silicon. This is shown in FIG. The horizontal axis in FIG. 3 is the etch rate of the polysilicon and the vertical axis is the selectivity between the polysilicon and the oxide film. A point A in the figure is a value of continuous 80 W, a curve 301 is a case where the value of the continuous power is reduced, and a curve 302 is an on / off control with a constant voltage amplitude and the duty ratio (the ratio of the on period to one on / off cycle). ) Is reduced. When the high frequency is turned on / off, the selection ratio becomes higher at the same polycrystalline silicon etch rate as compared with the continuous power. The cause can be estimated as follows. When oxygen or a reaction product containing oxygen adheres, the etch rate of the oxide film decreases. On the other hand, the etching rate of polycrystalline silicon does not decrease to a certain extent in the amount of oxygen attached. When the high-frequency power supply is turned on and off, ions are not accelerated during the off period, and only oxygen or reaction products are deposited. Ions are accelerated and incident on the surface during the on-period, but are inhibited by the deposits during the off-period, and the etch rate of the oxide film is reduced to increase the selectivity.

【0012】図3よりオンオフ制御の効果をより高くす
るためには、デューティー比を30%以下にすれば良いこ
とが分かる。またオン−オフの繰り返し周波数は100Hz
から10kHzの間が適当である。周波数がこれより低くな
ると、オンオフ制御したことの効果が徐々に低くなる結
果となった。また、繰り返し周波数が高いと高周波電源
109の製作が技術的に難しくなる。
FIG. 3 shows that the duty ratio can be reduced to 30% or less in order to further enhance the effect of the on / off control. On-off repetition frequency is 100Hz
Between 10 and 10 kHz is appropriate. When the frequency is lower than this, the effect of the on / off control gradually decreases. Also, if the repetition frequency is high, it becomes technically difficult to manufacture the high-frequency power supply 109.

【0013】なお、同じエッチ速度を得るために必要な
高周波電源109の電力の値は、装置の種類や高周波の
周波数によって大きく異なるが、どの場合でも酸化膜の
エッチ速度はデューティー比に比例する。従って、装置
構造などが変わると図3の電力の絶対値は変わるが、デ
ューティー比と選択比の関係は成り立つために、デュー
ティー比30%以下という数値はどの場合にも当てはま
る。
The value of the power of the high-frequency power supply 109 required to obtain the same etching speed greatly varies depending on the type of the device and the frequency of the high frequency, but in any case, the etching speed of the oxide film is proportional to the duty ratio. Therefore, although the absolute value of the power shown in FIG. 3 changes when the device structure or the like changes, the relationship between the duty ratio and the selection ratio is satisfied, and the numerical value of 30% or less applies to any case.

【0014】以上の実施例では2つのステップでエッチ
ングする方法を述べたが、被エッチング物質が金属、あ
るいは金属とシリコンの化合物などの多層構造でも、ス
テップの数を増してかつ下地部分が露出する直前あるい
は直後に、高周波電源をオンオフ制御することで、エッ
チ残りを抑えると同時に高選択比を保つことができる。
また、試料の構造によってはオーバエッチの部分をさら
に複数のステップに分けても良い。
In the above embodiment, the method of etching in two steps has been described. However, even when the material to be etched is a metal or a multilayer structure of a compound of metal and silicon, the number of steps is increased and the underlying portion is exposed. Immediately before or immediately after the high-frequency power supply is turned on / off, it is possible to suppress the remaining etch and to maintain a high selection ratio.
Further, depending on the structure of the sample, the overetched portion may be further divided into a plurality of steps.

【0015】〔実施例2〕図4は本発明を適用する別の
装置構造で、この装置では数百kHzから数十M Hzのいわ
ゆるラジオ波帯(以後rfと呼ぶ)の周波数で誘導結合に
よりプラズマを発生させる。真空容器401はアルミナ
や石英などの電磁波を透過する物質でつくられている。
その回りに、プラズマ403を発生させるための電磁コ
イル402が巻いてある。コイルにはrf電源404が接
続されている。真空容器401内には試料台408があ
りその上に試料407が置かれ、高周波電源409が接
続されている。真空容器401には上蓋405がついて
いるがこれは一体型でもかまわない。
[Embodiment 2] FIG. 4 shows another apparatus structure to which the present invention is applied. In this apparatus, inductive coupling is performed at a frequency of a so-called radio wave band (hereinafter referred to as rf) of several hundred kHz to several tens MHz. Generates plasma. The vacuum container 401 is made of a material that transmits electromagnetic waves, such as alumina and quartz.
An electromagnetic coil 402 for generating a plasma 403 is wound therearound. An rf power supply 404 is connected to the coil. A sample stage 408 is provided in the vacuum vessel 401, on which a sample 407 is placed, and to which a high-frequency power source 409 is connected. The vacuum vessel 401 has an upper lid 405, which may be an integral type.

【0016】この装置でも、この装置でも加工を複数の
ステップに分けてオーバエッチで高周波電源409をオ
ンオフ制御することでエッチ残りを抑えてかつ選択比を
高く保つことができる。図4に示す装置では、電磁コイ
ル402は上蓋405の上に設置されていても効果は同
じである。
In this apparatus as well, in this apparatus, the processing is divided into a plurality of steps, and the high frequency power supply 409 is turned on / off by overetching, so that the remaining etching can be suppressed and the selection ratio can be kept high. In the device shown in FIG. 4, the effect is the same even if the electromagnetic coil 402 is installed on the upper lid 405.

【0017】〔実施例3〕図5は本発明を適用する別の
装置構造で、この装置ではrf電力の容量結合によりプラ
ズマを発生させる。真空容器501内には2枚の電極5
02、505が平行に配置してある。電極にはそれぞれ
rf電源503と高周波電源506が接続してある。試料
504は試料台をかねる電極505の上におかれる。ガ
スは試料と対向した電極502に開いた穴から導入管5
08を通して容器内に入れられる。プラズマ507は2
枚の電極の間で発生する。
[Embodiment 3] FIG. 5 shows another apparatus structure to which the present invention is applied. In this apparatus, plasma is generated by capacitive coupling of rf power. Two electrodes 5 are placed in a vacuum vessel 501.
02 and 505 are arranged in parallel. Each of the electrodes
An rf power supply 503 and a high-frequency power supply 506 are connected. The sample 504 is placed on an electrode 505 serving as a sample stage. The gas is introduced into the inlet tube 5 through the hole opened in the electrode 502 facing the sample.
08 into the container. Plasma 507 is 2
Occurs between the electrodes.

【0018】この装置でも、この装置でも加工を複数の
ステップに分けてオーバエッチで高周波電源506をオ
ンオフ制御することでエッチ残りを抑えてかつ選択比を
高く保つことができる。
In this apparatus as well, in this apparatus, the processing is divided into a plurality of steps, and the high-frequency power supply 506 is turned on and off by overetching, so that the remaining etching can be suppressed and the selection ratio can be kept high.

【0019】〔実施例4〕次に、オーバエッチでさらに
高い選択比を実現する方法を述べる。図6は被加工物の
マスクをレジストではなく酸化膜にした場合の多結晶シ
リコンのエッチ速度と選択比の関係を示す。点Aは高周
波電力が連続80Wの値で、曲線601は連続で電力を小
さくした値、曲線602は電圧振幅一定でオンオフ制御
でデューティー比を小さくした場合の値である。図3と
比較してオンオフ制御することにより、選択比がさらに
最大50%程度上がることが分かる。この理由はレジス
ト中に含まれる炭素原子を排除したことによる。先に述
べたように、バイアスをオンオフ制御すると高周波がオ
フの期間に酸化膜上に反応生成物や酸素原子が堆積して
酸化膜のエッチ速度を低下させるが、同時に炭素原子あ
るいは炭素を含む反応生成物も堆積する。これらの物質
は酸化膜のエッチ速度を高める性質があることが知られ
ている。このために、オンオフ制御の効果を低くしてし
まう。マスク材に酸化膜のような炭素を含まない物質を
用いることにより、バイアスがオフ期間の炭素の付着が
なくなり、より高い選択比が得られる。炭素を含まない
マスク材としては他に窒化シリコンなどがある。
[Embodiment 4] Next, a method for realizing a higher selectivity by overetching will be described. FIG. 6 shows the relationship between the etching rate and the selectivity of polycrystalline silicon when the mask of the workpiece is not a resist but an oxide film. A point A is a value where the high-frequency power is 80 W continuously, a curve 601 is a value where the power is continuously reduced, and a curve 602 is a value where the voltage amplitude is constant and the duty ratio is reduced by on / off control. It can be seen that by performing the on / off control as compared with FIG. 3, the selection ratio is further increased by about 50% at the maximum. This is because the carbon atoms contained in the resist were excluded. As described above, when the bias is turned on and off, reaction products and oxygen atoms are deposited on the oxide film during a period in which the high frequency is off, thereby lowering the etch rate of the oxide film. Products also accumulate. It is known that these substances have a property of increasing the etching rate of an oxide film. For this reason, the effect of the on / off control is reduced. By using a material that does not contain carbon, such as an oxide film, for the mask material, the deposition of carbon during the bias off period is eliminated, and a higher selectivity can be obtained. Another example of a mask material that does not contain carbon is silicon nitride.

【0020】以上、本実施例によれば、下地の酸化膜が
露出するまでを高速で加工することで加工時間を短縮で
きる。かつ、下地が露出する直前あるいは直後から、試
料に加える高周波をオンオフ制御することで、連続電力
を印加した場合と比べて、エッチ速度の低下を抑えつつ
高い選択比を保つことができる。従って、エッチ残りも
抑えられる。
As described above, according to this embodiment, the processing time can be shortened by processing at a high speed until the underlying oxide film is exposed. In addition, by controlling on / off of the high frequency applied to the sample immediately before or immediately after the base is exposed, it is possible to maintain a high selection ratio while suppressing a decrease in the etching speed as compared with a case where continuous power is applied. Therefore, the remaining etch is suppressed.

【0021】[0021]

【発明の効果】本発明によれば、多結晶シリコンのエッ
チングにおけるエッチ速度の低下あるいはエッチ残りの
発生を抑えて、かつ高い対酸化膜選択比を保ち、半導体
素子の加工を行うことができるという効果がある。
According to the present invention, it is possible to process a semiconductor element while suppressing a decrease in the etching rate or the occurrence of the remaining etching in the etching of polycrystalline silicon, and maintaining a high selectivity to an oxide film. effective.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の表面加工方法を実施するための装置の
一実施例を示す全体構成図である。
FIG. 1 is an overall configuration diagram showing one embodiment of an apparatus for performing a surface processing method of the present invention.

【図2】図1の装置による半導体試料の処理断面を示す
図である。
FIG. 2 is a view showing a processing cross section of a semiconductor sample by the apparatus of FIG. 1;

【図3】多結晶シリコンエッチ速度と選択比との関係を
示す図である。
FIG. 3 is a diagram showing a relationship between a polycrystalline silicon etch rate and a selectivity.

【図4】本発明の表面加工方法を実施するための装置の
他の実施例を示す全体構成図である。
FIG. 4 is an overall configuration diagram showing another embodiment of an apparatus for performing the surface processing method of the present invention.

【図5】本発明の表面加工方法を実施するための装置の
さらに他の実施例を示す全体構成図である。
FIG. 5 is an overall configuration diagram showing still another embodiment of the apparatus for performing the surface processing method of the present invention.

【図6】多結晶シリコンエッチ速度と選択比との関係を
示す図である。
FIG. 6 is a diagram showing a relationship between a polycrystalline silicon etch rate and a selectivity.

【符号の説明】[Explanation of symbols]

101…マイクロ波電源、102…導波管、103…導入窓、10
4,401,501…真空容器、105…磁石、106,403,507…プラ
ズマ、107,407,504…試料、108,408…試料台、109,409,
506…高周波電源、110…電圧波形、201…シリコン基板,
202…酸化膜, 203 …多結晶シリコン、204…レジス
ト、301,302,601,602…曲線、402…電磁コイル、404,50
3…rf電源、405…上蓋、502,505…電極、508…ガス導
入管。
101 ... microwave power supply, 102 ... waveguide, 103 ... introduction window, 10
4,401,501… Vacuum container, 105… Magnet, 106,403,507… Plasma, 107,407,504… Sample, 108,408… Sample stand, 109,409,
506: High frequency power supply, 110: Voltage waveform, 201: Silicon substrate,
202: oxide film, 203: polycrystalline silicon, 204: resist, 301, 302, 601, 602: curve, 402: electromagnetic coil, 404, 50
3 rf power source, 405 top cover, 502,505 electrodes, 508 gas introduction tube.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 久礼 得男 東京都国分寺市東恋ヶ窪一丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 徳永 尚文 東京都青梅市今井町2326番地 株式会社日 立製作所デバイス開発センタ内 (72)発明者 児島 雅之 東京都小平市上水本町五丁目20番1号 株 式会社日立製作所半導体事業部内 ──────────────────────────────────────────────────の Continuing on the front page (72) Tokuo Kure, Inventor 1-280 Higashi Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Masayuki Kojima 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo In-house Semiconductor Division, Hitachi, Ltd.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】真空容器内にプラズマを発生させ、該プラ
ズマにより表面加工される試料が配置される試料台に高
周波電圧を印加して、前記試料の表面加工開始から終了
までを複数のステップに分け、かつそれらのステップを
加工を終了させる下地物質との加工速度比が比較的小さ
い前半と、比較的大きい後半の2つに分け、少なくとも
後半のステップの一つで、高周波電圧をオンとオフの期
間に分けて繰り返し印加することを特徴とする表面加工
方法。
1. A plasma is generated in a vacuum vessel, a high-frequency voltage is applied to a sample stage on which a sample to be surface-processed by the plasma is placed, and a plurality of steps are performed from the start to the end of the surface processing of the sample. And divide the steps into two parts: a first half in which the processing speed ratio with the base material for finishing the processing is relatively small, and a second half in which the processing speed ratio is relatively large. At least in one of the latter steps, the high-frequency voltage is turned on and off. Wherein the repetitive application is performed separately for each period.
【請求項2】請求項1記載の表面加工方法において、加
工される前記試料に主成分として炭素を含まないことを
特徴とする表面加工方法。
2. The surface processing method according to claim 1, wherein the sample to be processed does not contain carbon as a main component.
【請求項3】請求項1記載の高周波電圧において、オン
の期間がオンとオフの1周期に占める割合を30%以下
としたことを特徴とする表面加工方法。
3. A surface processing method according to claim 1, wherein the ratio of the ON period to one ON / OFF cycle in the high frequency voltage is 30% or less.
【請求項4】請求項1または3記載の高周波電圧におい
て、周波数を100Hzから10kHzとしたことを特徴とする表
面加工方法。
4. A surface processing method according to claim 1, wherein the frequency is changed from 100 Hz to 10 kHz.
【請求項5】請求項1記載の表面加工方法において、前
半のステップ郡と後半のステップ郡を、時間で決めて切
り替えることを特徴とする表面加工方法。
5. The surface processing method according to claim 1, wherein the step group in the first half and the step group in the second half are determined and switched according to time.
【請求項6】請求項1記載の表面加工方法において、前
半のステップ郡と後半のステップ郡を、被エッチング物
質がプラズマ中で放出する光の強度を検出して切り替え
ることを特徴とする表面加工方法。
6. The surface processing method according to claim 1, wherein the first group of steps and the second group of steps are switched by detecting the intensity of light emitted in the plasma by the substance to be etched. Method.
JP03086598A 1998-02-13 1998-02-13 Surface processing method Expired - Fee Related JP4061691B2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165032A (en) * 2004-12-02 2006-06-22 Ulvac Japan Ltd Etching method and apparatus thereof
JP2012084872A (en) * 2010-09-15 2012-04-26 Tokyo Electron Ltd Plasma etching processing apparatus, plasma etching processing method and manufacturing method of semiconductor device
JP2012169390A (en) * 2011-02-14 2012-09-06 Hitachi High-Technologies Corp Plasma processing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165032A (en) * 2004-12-02 2006-06-22 Ulvac Japan Ltd Etching method and apparatus thereof
JP2012084872A (en) * 2010-09-15 2012-04-26 Tokyo Electron Ltd Plasma etching processing apparatus, plasma etching processing method and manufacturing method of semiconductor device
JP2012169390A (en) * 2011-02-14 2012-09-06 Hitachi High-Technologies Corp Plasma processing method

Also Published As

Publication number Publication date
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