JPH11232885A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent rewriting from exceeding the number of rewriting times of EEPROM in a semiconductor memory provided with an electrically erasable programmable ROM (EEPROM). SOLUTION: A counter 11 counts the number of rewriting times in each memory cell in an EEPROM 10 from an address (Address) and a write-enable signal (Write Enable/), when th number of times of rewriting reaches the limit in either of memory cells, a warning signal OVF is generated. When the warning signal OVF is generated an OR gate 12 set forcibly a level of a write-enable signal (Write Enable/) to the EEPROM 10 to invalid 'H' level. Thereby, rewriting in the EEPROM 10 is prohibited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrically erasable and rewritable programmable ROM (hereinafter referred to as EEPR).
OM).

[0002]

2. Description of the Related Art Conventionally, as a technique in this field, there is a technique described in the following document, for example. Reference 1: Japanese Patent Application Laid-Open No. 7-254290 Document 2: Japanese Patent Application Laid-Open No. 7-307095 Reference 3: Japanese Patent Application Laid-Open No. 8-241599 The number of rewritable times in an EEPROM has a limit.
10 is about ^four times. If further rewriting is performed, the written data changes in the EEPROM, and the written data may differ from the read data. Reference 1
3 shows a semiconductor memory device which calculates the number of times of rewriting of the EEPROM using a counter, and generates a warning signal when the number of times of rewriting is more than a certain number of times (for example, 10 ⁴ times).

[0003]

However, the semiconductor memory devices disclosed in the prior art documents 1 to 3 have the following problems. Even if the number of rewrites to the EEPROM exceeds the limit and a warning signal is generated, the warning signal is overlooked, and if the rewriting of the EEPROM is continued, the data written at that time changes in the EEPROM, There is a possibility that data different from the written data may be read, and there has been a problem that the reliability of information processing requiring accuracy is lost.

[0004]

In order to solve the above-mentioned problems, a first and a second invention of the present invention have a plurality of memory cells each storing information and an address for designating the memory cells. And a control signal instructing access to the memory cell, the semiconductor memory device including the EEPROM has the following configuration. That is, an address is input, the number of erasures and rewrites in each memory cell is counted, and a counter that generates a warning signal when the number of erasures and rewrites is equal to or greater than a predetermined value. Prohibiting means is provided for forcibly invalidating erasure and rewriting of a plurality of memory cells when an error occurs.

The third and fourth inventions are directed to a first EEPRO.
The semiconductor memory device provided with M has the following configuration. That is, a second EEPROM having a plurality of memory cells each storing information and having a common address and a control signal applied to the first EEPROM,
An address is input, the number of erasures and rewrites in each memory cell in the first EEPROM is counted, and when the number of erasures and rewrites exceeds a predetermined value, a counter for generating a warning signal; Occurs,
Erasing, rewriting and reading of a plurality of memory cells in the first EEPROM are invalidated, and the second EEPROM
There is provided selection means for enabling only erasing, rewriting, and reading of each of the memory cells therein.

According to a fifth aspect of the present invention, a semiconductor memory device having a first EEPROM has the following configuration. That is, an address is input and the first EEPROM is input.
A first counter for generating a warning signal when the number of times of erasing and rewriting is equal to or more than a predetermined value, and a first counter for generating a warning signal when the number of times of erasing and rewriting exceeds a predetermined value. When it occurs, the first EEPRO
First prohibiting means for invalidating erasing, rewriting, and reading of a plurality of memory cells in M;
M and an arbitrary number of stages of second EEPROM for inputting a control signal and an address common to M and an arbitrary number of stages of second EEPROM are provided corresponding to the address, a start signal, and the start signal is input. The number of erasures and rewrites of each memory cell in the second EEPROM corresponding to the given number is counted, and when the number of erasures and rewrites exceeds a predetermined value, a warning signal is generated. The second EEPROM of each stage is provided corresponding to the second EEPROM of an arbitrary number of stages, and when the corresponding second counter generates a warning signal, the corresponding second EEPROM is provided.
An arbitrary number of stages of second prohibiting means for invalidating erasing, rewriting and reading of a plurality of memory cells in M are provided. The first counter of the arbitrary number of second counters receives the warning signal of the first counter as a start signal, and the other of the arbitrary number of second counters receives the warning signal of the first counter. The warning signal of the second counter is input as a start signal.

According to a sixth aspect of the present invention, a semiconductor device having the first EEPROM has the following configuration. That is, a second EEPROM for inputting a control signal and an address common to the first EEPROM, an address for the second EEPROM, and the number of erase and rewrite operations in each memory cell in the first EEPROM are counted. When the number of times of erasing and rewriting in a memory cell becomes equal to or more than a predetermined value, a counter for generating a warning signal for each memory cell and a first address specified by an address based on the warning signal for each memory cell. And a selection circuit for generating a selection signal indicating whether the memory cell in the EEPROM can be erased and rewritten. The number of times of erasing and rewriting of the memory cell designated by the address in the first EEPROM is determined based on the selection signal. Is not equal to or greater than the value of the first E
The control signal is directly supplied to the EPROM and the second E
When the control signal given to the EPROM is invalidated, and the number of erasures and rewrites of the memory cell specified by the address exceeds a predetermined value, the second EEPROM is set.
The control signal is supplied to the ROM as it is and the first E
And a switching circuit for invalidating a control signal given to the EPROM.

According to the first and second aspects of the present invention, since the semiconductor memory device is configured as described above, it is counted by the counter that the number of rewrites in the memory cell in the EEPROM has reached the limit, and a warning is issued. A signal is emitted. When a warning signal is generated, rewriting of each memory cell in the EEPROM is prohibited by the prohibiting means. Third and fourth
According to the invention, the counter counts the fact that the number of rewrites in the memory cells in the first EEPROM has reached the limit, and issues a warning signal. When a warning signal is generated, the rewriting of each memory cell in the first EEPROM is inhibited by the selection means, and thereafter, the second EEPROM is rewritten.
Rewriting and reading are performed on the OM.

According to the fifth invention, the first EEPROM
The first counter counts that the number of rewrites in the middle memory cell has reached the limit, and issues a warning signal. When a warning signal is generated in the first counter, the first counter
The rewriting of the first EEPROM is prohibited by the prohibiting means, and thereafter, the rewriting and reading of the second EEPROM of an arbitrary number of stages are performed. According to the sixth aspect, the fact that the number of rewrites in each memory cell in the first EEPROM has reached the limit is counted by the counter, and a warning signal is issued. When a warning signal is generated by the first counter, a selection signal corresponding to the memory targeted by the warning signal is output from the selection circuit. With this selection signal, rewriting and reading of the memory cells in the first EEPROM whose rewriting frequency exceeds the limit are prohibited, and rewriting and reading of the corresponding memory cells of the second EEPROM are performed. Therefore, the above problem can be solved.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention. This semiconductor storage device includes an EEPROM 10 having a plurality of memory cells for storing information. The EEPROM 10 has a terminal AD for inputting an externally provided address Address, and a terminal CE / for inputting a chip enable signal Chip Enable / (where / indicates a signal at which the "L" level becomes valid). And a terminal OE / for inputting an output enable signal Output Enable /
And W for inputting the write enable signal Write Enable /
E / and a terminal I / O for inputting and outputting information Data for accessing the memory cell are provided. The semiconductor memory device further includes an address Address and a signal Write Enable.
Enter / to specify the EEPRO specified by the address Address.
The number of rewrites performed on the memory cell in M10 is counted, and when the number of rewrites reaches a limit (a predetermined value) in any one of the memory cells, a counter 11 for generating a warning signal OVF, A two-input OR gate 12, which is a means, is provided. The output terminal of the counter 11 is connected to one input terminal of the OR gate 12, and the signal Write Enable / is input to the other input terminal.
The output terminal of the OR gate 12 is connected to the terminal WE / of the EEPROM 10.

FIG. 2 is a time chart for explaining the operation of FIG. 1. The operation of the semiconductor memory device of FIG. 1 will be described with reference to FIG. FIG. 2 shows two periods T1 and T
2, each terminal AD, CE /, OE /, WE /, I /
The waveforms of the signal on O and the warning signal OVF are shown.
The number of rewritable times of each memory cell of the EEPROM 10 is as follows.
As described above, for example, the limit is about 10 ⁴ , and the period T1 indicates a period in which the number of rewrites in a plurality of memory cells in the EEPROM has not reached the limit. The period T2 is, for example, the address Addres
This indicates the period when the memory cell specified by s reaches the limit. In the period T1, for example, when the address “0” is externally given and the signal Chip Enable / becomes valid “L”, the EEPROM 10 rewrites or stores the information stored in the memory cell “0”. Is ready for reading. Here, when the signal Write Enable / becomes valid “L”, the counter 11 still outputs the warning signal OV.
Since no F is generated, the OR gate 12 outputs the signal Writ
e Enable / pass through the terminal W of EEPROM 10
Give to E /. The EEPROM 10 has a valid signal Write
When Enable / is given, the information Data given to the terminal I / O is stored in, for example, a memory cell of “0” designated by the address “Address”.

In a period T2, the address Addr is externally supplied.
When ess is given and the signal Chip Enable / becomes valid “L”, the EEPROM 10 operates similarly to the case of the period T1.
It becomes possible to rewrite or read the information stored in the “0” -th memory cell. Here, when the counter 11 for inputting the address "Address" detects, for example, that the number of rewrites for the "0" th memory cell specified by the address "Address" has reached a limit, an "H" level warning signal OVF is generated. I do. The OR gate 12 supplied with the warning signal OVF forcibly sets the terminal WE / of the EEPROM 10 to "H". Therefore, even if the signal Write Enable / becomes "L", it is invalidated and EEPROM
Rewriting at 10 is prohibited.

As described above, in the first embodiment,
In any one of the memory cells in the EEPROM 10, the counter 11 generates a warning signal OVF by detecting that the number of rewrites has reached the limit. When the warning signal OVF is generated, the rewriting in the EEPROM 10 is invalidated. An inhibiting OR gate 12 is provided. for that reason,
In addition to issuing a warning, rewriting of the EEPROM 10 cannot be performed.
Despite the occurrence of F, the information is not overlooked and erroneously rewritten.

Second Embodiment FIG. 3 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention. This semiconductor memory device includes a first EEPROM 20 for inputting a common address, and an EEPROM
A second EEPROM 21 having the same configuration as the OM 20, a counter 22 having the same function as the counter 11 in the first embodiment, and a selection unit 23 connected to the counter 22 are provided. Each EEPROM 20, 21
Has a plurality of memory cells for storing information, respectively,
Terminal A for inputting an externally provided address Address
D, terminals CE1 / and CE2 / for inputting a chip enable signal Chip Enable /, and an output enable signal Output E
nable / input terminals OE1 /, OE2 // and write enable signal Write Enable / input WE1 /, WE
2 / and a terminal I / O for inputting / outputting information Data for accessing a memory cell are provided. Each EEP
Address AD is commonly input to the terminals AD of the ROMs 20 and 21, and the terminal C of each of the EEPROMs 20 and 21 is
A signal Chip Enable / is commonly input to E.

The selection means 23 comprises two two-input OR gates 23 forming a first gate circuit for inputting the warning signal OVF output from the counter 22 to one input terminal.
a and 23b, and two two-input OR gates 23c and 23d forming a second gate circuit for inputting a signal obtained by inverting the logic of the warning signal OVF to one input terminal. The other terminal of the OR gate 23a
This is a connection to which the signal Output Enable / is input. The output terminal of the OR gate 23a is connected to the terminal OE of the EEPROM 20.
Connected to 1 /. The other terminal of the OR gate 23b is a connection to which the signal Write Enable / is input, and the output terminal of the OR gate 23b is connected to the terminal WE1 / of the EEPROM 20. The other terminal of the OR gate 23c is connected to receive the signal Output Enable /, and the output terminal of the OR gate 23c is connected to the EEPROM.
21 terminal OE2 /. OR gate 23
The other terminal of d is connected to receive the signal Write Enable /, and the output terminal of the OR gate 23d is
It is connected to the terminal WE2 / of the EEPROM 21.

FIG. 4 is a time chart showing the operation of FIG. 3. The operation of the semiconductor memory device of FIG. 3 will be described with reference to FIG. FIG. 4 shows terminals AD, CE /, OE1 /, OE2 //, WE in two periods T3, T4.
The waveforms of the signals on 1 /, WE2 /, I / O and the warning signal OVF are shown. Rewritable times of the memory cells of the EEPROM20 is, for example, 10 about ⁴ is the limit, the counter 22, the address Address signal Write En
The number of rewrites in each memory cell of the EEPROM 20 is counted from “able /”. The period T3 is a period in which, for example, the number of rewrites in a plurality of memory cells in the EEPROM 20 has not reached the limit. The period T4 indicates a period in which the number of rewrites of the memory cell specified by the address “Address” reaches the limit, for example.

In the period T3, the counter 22 outputs "H".
No level warning signal OVF is generated, and the output signal of the counter 22 is at "L" level. In this state, when the address “0”, for example, is given from the outside and the signal Chip Enable / becomes valid “L”, the EEP
The ROMs 20 and 21 are in a state where the information stored in the memory cell of the number “0” can be rewritten or the information can be read. As shown in FIG. 4, when the signal Write Enable / is given a valid "L" level and given, since the output signal of the counter 22 is at the "L" level, the level of the signal Write Enable / is supplied via the OR gate 23b. The data is given to the terminal WE1 / of the EEPROM 20, and the information Data given to the terminal I / O at this time is written to the memory cell of the number "0". That is, the information in the “0” -th memory cell is rewritten. However, since the output signal of the counter 22 is at the "L" level, the OR gate 23d outputs a valid "L" signal.
The level signal Write Enable / is not supplied to the terminal WE2 / of the EEPROM 21. That is, the data is not rewritten to the EEPROM 21 in the period T3 after being selected by the selection unit 23. When data is read from the EEPROMs 20 and 21, the signal Output Enable / is set to a valid "L" level.
, The read operation on the memory cell in the EEPROM 20 is performed, but the read operation on the memory cell in the EEPROM 21 is not performed.

In a period T4, an address "0" is externally supplied and a signal Chip Enable /
Becomes effective "L", the EEPROMs 20 and 21
It becomes possible to rewrite or read the information stored in the memory cell of "0", but the counter 22 counting the number of rewrites indicates that the number of rewrites for the memory cell of "0" has reached the limit. Upon detection, an "H" level warning signal OVF is generated. At this time, even if the signal Write Enable / becomes valid "L" level, the OR gate 23b does not pass through it, and the terminal WE1 / of the EEPROM 20 is maintained at "H" level. On the other hand, the OR gate 23d outputs a valid “L” level signal Write Enable / to the EEPROM 21.
To the terminal WE2 /. Therefore, at this time EEP
By the information Data given to the terminal I / O of the ROM 21,
The “0” -th memory cell in the EEPROM 21 is rewritten. Thereafter, since the counter 22 continues to output the "H" level warning signal OVF, the EEPROM 20 is not rewritten. When data is read from the EEPROMs 20 and 21, the signal Output Enable / is set to a valid "L" level.
1 is read out, but the EEP
Reading from the memory cells in the ROM 20 is not performed.

As described above, according to the semiconductor memory device of the second embodiment, the EEPROM 20 having the memory cells whose rewriting and reading are designated by the address Address is performed.
In addition to the above, an EEPROM 21 is provided, and a counter 22 that functions in the same manner as the counter 11 of the first embodiment,
A selection means 23 comprising OR gates 23a to 23d is provided, and when the number of times of rewriting of memory cells in the EEPROM 20 reaches a limit, information is stored in the EEPROM 21. Therefore, the number of rewritable times of the information Data stored in the semiconductor memory device is equal to the address Addr.
Even if the ess and the chip enable signal Chip Enable / are not changed, the number becomes twice (for example, 10 ⁴ × 2) as compared with the semiconductor memory device of the related art and the first embodiment.

Third Embodiment FIG. 5 is a configuration diagram of a semiconductor memory device according to a third embodiment of the present invention. In this semiconductor memory device, a first EEPROM 31 and a second EEPROM 32 which commonly receive and share a chip enable signal Chip Enable / and an address Address, a first counter 33, a first counter 33,
, A second counter 35, and a second prohibiting unit 36. The EEPROMs 31 and 32 and the counter 33 correspond to the EEPROM 2 in the second embodiment.
It has the same configuration as 0, 21 and the counter 22.
The counter 35 has an address Address and a signal Write Enable.
/ And the warning signal OVF1 output from the counter 32, and the warning signal OVF1 is
The configuration is such that the number of rewrites in the memory cells in the EPROM 32 is counted. The counter 35 is EEPRO
It has a function of generating a warning signal OVF2 when the number of rewrites in the memory cell in M32 reaches the limit.

The first prohibiting means 34 comprises OR gates 34a and 34b for inputting the warning signal OVF1 output from the counter 33 to one input terminal. O
The other terminal of the R gate 34a has a signal Output Enable /
Is input, and the output terminal of the OR gate 34a is connected to the terminal OE1 / of the EEPROM 31. The signal Write En is connected to the other terminal of the OR gate 34b.
"able /" is input, and the output terminal of the OR gate 34b is connected to the terminal WE1 / of the EEPROM 31. The second prohibiting means 36 includes OR gates 36a and 36b for inputting the warning signal OVF2 output from the counter 35 to one input terminal. OR
The other terminal of the gate 36a is a connection to which the signal Output Enable / is input, and the output terminal of the OR gate 36a is connected to the terminal OE2 / of the EEPROM 32. The other terminal of the OR gate 36b has a signal Write En
"able /" is input, and the output terminal of the OR gate 36b is connected to the terminal WE2 / of the EEPROM 32.

FIG. 6 is a time chart showing the operation of FIG. 5, and the operation of the semiconductor memory device of FIG. 5 will be described with reference to FIG. FIG. 6 shows three periods T5, T6,
Each terminal AD, CE /, OE1 /, OE2 at T7
Signals on WE1 /, WE2 //, I / O and warning signal OV
The waveforms of F1 and OVF2 are shown. EEPROM3
The maximum number of rewrites of each memory cell is, for example, about 10 ^4.
The number of rewrites in each memory cell of the EEPROM 31 is counted from the signal Write Enable /. The period T5 in FIG. 6 is a period in which, for example, the number of rewrites in a plurality of memory cells in the EEPROM 31 has not reached the limit. The period T6 indicates a period in which, for example, the memory cell in the EEPROM 31 specified by the address “Address” reaches the limit of the number of rewrites. The period T7 is EE
In both the PROMs 31 and 32, there is a period in which there is a memory cell at an address where the number of rewrites has reached the limit.

In the period T5, if no memory cell in the EEPROM 31 has reached the limit of the number of rewrites,
The rewriting operation for the PROM 31 is the same as in the second embodiment. The counter 33 counts the number of rewrites at that time. In the period T6, the counter 33 sets the EEPR
Detecting that the memory cell corresponding to the address “0” in the OM 31 has reached the limit of the number of rewrites,
An "H" level warning signal OVF1 is generated. The warning signal OVF1 is given to the counter 35, and the counter 35 which has been outputting the "H" level starts counting and outputs an "L" level signal. That is, the warning signal OVF1 becomes a start signal of the counter 35. When the counter 33 outputs the warning signal OVF1 of “H”, the first prohibiting means 34 makes the terminal O of the EEPROM 31
Signal Output Enable /, Write to E1 /, WE1 /
Forcibly set Enable / to an invalid “H” level to prohibit rewriting and reading. Conversely, when the counter 35 outputs a signal of “L”, the second prohibiting means 36
Signal given to terminals OE2 // WE2 // of EPROM 32
Output Enable /, Write Enable / are connected to terminal OE2
/, WE2 /. Therefore, rewriting and reading of the EEPROM 32 are performed.

In the period T7, when the counter 35 detects a memory cell whose number of rewrites has reached the limit in the EEPROM 32, the counter 35 generates an "H" level warning signal OVF2. In this state, the second prohibiting means 36 outputs the signals Output Enable /, Writ to the terminals OE2 /, WE2 / of the EEPROM 32.
e Enable / is forcibly set to the invalid "H" level, and rewriting and reading are prohibited. As described above, in the third embodiment, the EEPROM 32, the counter 35 that uses the warning signal OVF1 of the counter 33 as a start signal,
Since the prohibiting means 36 corresponding to these is provided, similarly to the second embodiment, the number of times the EEPROM can be rewritten is apparently increased, and the warning signal OVF2 is generated even if the EEPROM 32 cannot be rewritten. Rewriting can be prohibited.

Fourth Embodiment FIG. 7 is a configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention. This semiconductor memory device includes a first EEPROM 41 and a second EEPROM 42 similar to those in the second embodiment, in which a chip enable signal Chip Enable / and an address Address are commonly input and shared.
A counter 43 different from the embodiment of FIG.
And a selection circuit 44, which is connected to the output side, and gate units 45 and 46 as switching circuits. Counter 43
Has a plurality of output terminals corresponding to each memory cell in the EEPROM 41, and outputs a signal Write Enable / and an address Addres.
s is input, the number of rewrites in each memory cell of the EEPROM 43 is counted, and a warning signal is output from an output terminal for a memory cell in which the number of rewrites has reached a limit. , No warning signal is generated. The selection circuit 44 stores the memory cell corresponding to the address “Address” given at that time based on the output signal of the counter 43 into the EEPROM.
A selection signal for selection is output from the EEPROM 41 or the EEPROM 42.

The gate section 45 is an OR gate 45 for inputting a selection signal of the selection circuit 44 to one input terminal.
a, 45b and 45c. OR gate 45
The other terminal of the OR gate 45a is connected to receive the signal Chip Enable /, and the output terminal of the OR gate 45a is EEPRO
It is connected to the terminal CE1 / of M41. OR gate 4
5b is a connection to which the signal Output Enable / is input, and the output terminal of the OR gate 45b is connected to the EE
It is connected to the terminal OE1 / of the PROM 41. The other terminal of the OR gate 45c is a connection for inputting the signal Write Enable /, and the output terminal of the OR gate 45c is connected to the terminal WE1 / of the EEPROM 41. The gate unit 46 is an OR gate 46 that inverts the selection signal of the selection circuit 44 and inputs the inverted signal to one input terminal.
a, 46b and 46c. OR gate 46
is connected to receive the signal Chip Enable /, and the output terminal of the OR gate 46a is connected to the EEPRO
M42 is connected to terminal CE2 /. OR gate 4
The output terminal of the OR gate 46b is connected to the other terminal of the OR gate 46b.
It is connected to terminal OE2 / of PROM42. The other terminal of the OR gate 46c is a connection for inputting the signal Write Enable /, and the output terminal of the OR gate 46c is connected to the terminal WE2 / of the EEPROM 42.

FIG. 8 is a time chart showing the operation of FIG. 7. The operation of the semiconductor memory device of FIG. 7 will be described with reference to FIG. FIG. 8 shows three periods T8, T9,
Each terminal AD, CE1 /, CE2 //, OE at T10
Waveforms on 1 /, OE2 //, WE1 /, WE2 //, I / O are shown. The number of rewrites of each memory cell of the EEPROM 41 is limited to, for example, about 10 ^4.
Thus, the number of rewrites in each memory cell of the EEPROM 41 is counted. The period T8 is an address
This shows a state where the memory cell of “0” is designated by Address and the memory cell of “0” of the EEPROM 41 has not reached the limit of the number of rewrites. In the period T8, since the memory cell corresponding to the address "0" in the EEPROM 41 can be rewritten, the counter 43 does not generate a warning signal for the memory cell. Based on the output signal of the counter 43, the selection circuit 44 applies an "L" level selection signal to each of the OR gates 45a to 45b in order to select a memory cell corresponding to "0" of the given address "Address" from the EEPROM 41 at that time. 45c and an "H" level signal to OR gates 46a-46c. In this state, the signal Ch
When ip Enable / and Write Enable / are given at a valid “L” level, the terminal WE1 / becomes “L” and the terminal WE
2 is forcibly set to "H". As a result, EEPR
Rewriting is performed on the “0” -th memory cell of the OM 41.

The period T9 shown in FIG.
This shows a case where the “0” -th memory cell of the PROM 41 has reached the limit of the number of rewrites. At this time, the counter 43 generates a warning signal for the “0” -th memory cell of the EEPROM 41 based on the counting result. Therefore, based on the output signal of the counter 43, the selection circuit 44 applies an "H" level selection signal to each OR gate in order to select a memory cell corresponding to the "0" of the given address "Address" from the EEPROM 42. 45A to 45c and an "L" level signal to OR gates 46a to 46c. In this state, the signal Ch
When ip Enable / and Write Enable / are given at a valid “L” level, the terminal WE1 / is forcibly set to the “H” level, and the terminal WE2 is set to the “L” level. As a result, rewriting is performed on the memory cell of the number “0” of the EEPROM 42.

The period T10 after the period T9 has already been set to the EE
While the “0” memory cell in the PROM 41 has reached the limit of the number of rewrites, the “1” memory cell in the EEPROM 41 has the address “1” when the number of rewrites has not yet reached the limit. "Is specified.
In this period T10, the address Ad in the EEPROM 41 is
Since the memory cell corresponding to the number "1" of the dress is rewritable, the counter 43 does not generate a warning signal for that memory cell. The selection circuit 44 determines the address given at that time based on the output signal of the counter 43.
The memory cell corresponding to address “1” is EEPRO
To select from M41, an "L" level selection signal is applied to each O.
The signal is applied to R gates 45a to 45c and an "H" level signal is applied to OR gates 46a to 46c. In this state, when the signals Chip Enable / and Write Enable / are given at valid “L” levels, the terminal WE1 / becomes “L”,
The terminal WE2 is forcibly set to "H". as a result,
Rewriting is performed on the "1" th memory cell of the EEPROM 41, and the information Data input from the terminal I / O at that time is written in the memory cell. Similarly, when information Data is read from the memory cells in the EEPROMs 41 and 42 specified by the address Address, the selected EEPROM is similarly read.
Information Data is read from the OMs 41 and 42.

As described above, in the fourth embodiment,
A counter 4 for counting the number of rewrites of the memory cells in the EEPROM 41 and generating a warning signal for each memory cell
3, the selector circuit 44, and the switching circuit including the gate sections 45 and 46 are provided, so that the memory cell in the EEPROM 41 corresponding to the number "0" designated by the address "Address" only reaches the limit of the number of rewrites. And EEPRO
Since M42 is used, the memory cells in the EEPROM 41 can be used without waste, and the number of rewritable times of the entire semiconductor memory device can be increased.

The present invention is not limited to the above embodiment, but can be variously modified. For example, there are the following modifications. (1) In the first embodiment, when prohibiting rewriting,
Although the OR gate 12 forcibly sets the signal Write Enable / to the invalid “H” level, the signal Chip Enable / may be forcibly set to “H”. (2) In the third embodiment, the EEPROM 32 and the counter 35 to be added to the EEPROM 31 are one set. However, an arbitrary number of stages may be added, and each of the counters 35 may use the preceding warning signal OVF2 as a start signal. Good. In this case, the limit of the number of rewrites in the semiconductor memory device increases by the number of stages.

[0032]

As described above in detail, according to the first and second aspects of the present invention, there is provided a semiconductor memory device having an EEPROM which can be erased and rewritten and has a limited number of times. A counter that counts the number of rewrites in the EEPROM and generates a warning signal when the number of rewrites exceeds a predetermined value. When a warning signal is generated, erasing and rewriting of each memory cell in the EEPROM are forcibly performed. Since the prohibiting means for invalidating the warning signal is provided, it is possible to prevent the warning signal from being overlooked and erroneously rewriting the information even though the warning signal is generated. According to the third and fourth aspects of the present invention, erasing and rewriting are possible, and the number of possible erasing and rewriting is limited in the semiconductor memory device including the first EEPROM.
A counter for counting the number of times of erasing and rewriting in the OM, and generating a warning signal when the number becomes equal to or more than a predetermined value; and a first EEPROM when a warning signal is generated.
Since the erasing, rewriting, and reading of each memory cell in M are prohibited and the selecting means for enabling erasing, rewriting, and reading only for each memory cell in the second EEPROM are provided, As in the first invention, the information is not erroneously rewritten, and the number of times the information stored in the semiconductor memory device can be rewritten is increased as compared with the first invention.

According to the fifth aspect, erasing and rewriting are possible, and the first EEPR, which has a limited number of possible erasures.
A first EEPROM in a semiconductor memory device having an OM;
The number of erasures and rewrites in each of the memory cells therein is counted, and when the number of erasures and rewrites reaches a limit, a first counter for generating a warning signal and erasing, rewriting and reading of the first EEPROM are inhibited. Since the first prohibiting means, the arbitrary number of second EEPROMs, the arbitrary number of second counters, and the second prohibiting means are provided, the number of times the information can be rewritten in the semiconductor memory device is apparently increased. With the increase, even if rewriting cannot be performed in the second EEPROM, a warning signal is generated and rewriting can be prohibited.

According to a sixth aspect of the present invention, there is provided a semiconductor memory device having a first EEPROM, which is capable of erasing and rewriting, and has a limited number of possible times.
A first counter for generating a warning signal for each memory when the number of erasures and rewrites in each memory cell of the EEPROM reaches a limit, and a limit signal, a selection circuit, and a switching circuit are provided. So, the first EEPROM
As a result, the second EEPROM is used only for the memory cells for which the number of times of erasing and rewriting has reached the limit.
Can be used without waste, and the number of rewritable times of the entire semiconductor memory device can be increased.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

FIG. 3 is a configuration diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a time chart showing the operation of FIG. 3;

FIG. 5 is a configuration diagram of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a time chart showing the operation of FIG.

FIG. 7 is a configuration diagram of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a time chart showing the operation of FIG. 7;

[Explanation of symbols]

10, 20, 21, 31, 32, 41, 42 EEO
PROM 11, 22, 33, 35, 43 Counter 12 Inhibiting means (gate circuit) 23 Selecting means 23a, 23b First gate circuit 23c, 23d Second gate circuit 34 First inhibiting means 36 Second inhibiting means 44 Selection circuit 45, 46 Switching circuit Address Address Chip Enable / Chip enable signal Output Enable / Output enable signal Write Enable / Write enable signal OVF, OVF1, OVF2 Warning signal

Claims (6)

[Claims] A plurality of memory cells each storing information; an address designating the memory cell; and a control signal designating access to the memory cell. The information of each memory cell is electrically connected. In the semiconductor memory device having a programmable ROM capable of erasing and rewriting, the address is input, the number of erasing and rewriting in each of the memory cells is counted, and the number of erasing and rewriting is equal to or more than a predetermined value. A counter that generates a warning signal when the warning signal is generated; and a prohibiting unit that forcibly invalidates the erasing and rewriting of the plurality of memory cells when the warning signal is generated. Semiconductor storage device. 2. The semiconductor memory device according to claim 1, wherein said inhibiting means comprises a gate circuit for forcibly invalidating said control signal when said warning signal is generated. A plurality of memory cells each storing information; an address designating the memory cells; and a control signal designating access to the memory cells. The information of each memory cell is electrically stored. A semiconductor memory device having a first programmable ROM that can be erased and rewritten has a plurality of memory cells each storing information, the address and the control signal are provided, and the information of each memory cell is An electrically erasable and rewritable second programmable ROM, the address being input, and the first programmable RO
A counter that counts the number of times of erasing and rewriting in each memory cell in M, and generates a warning signal when the number of times of erasing and rewriting is equal to or greater than a predetermined value; Selecting means for invalidating the erase, rewrite, and read for a plurality of memory cells in the first programmable ROM, and enabling only the erase, rewrite, and read for each memory cell in the second programmable ROM; , A semiconductor memory device. 4. The selecting means supplies the control signal to the first programmable ROM as it is before the warning signal is generated, and supplies the control signal to the first programmable ROM when the warning signal is generated. A first gate circuit forcibly disabling the control signal; and forcibly disabling the control signal to be supplied to the second programmable ROM before the warning signal is generated.
4. The semiconductor memory device according to claim 3, wherein a second gate circuit that supplies the control signal to the second programmable ROM as it is when the warning signal is generated. 5. A memory cell having a plurality of memory cells each storing information, an address designating the memory cell and a control signal designating access to the memory cell are provided, and the information of each memory cell is electrically connected. A semiconductor memory device having a first programmable ROM that can be erased and rewritten in the first memory;
A first counter that counts the number of times of erasing and rewriting in each memory cell in M, and generates a warning signal when the number of times of erasing and rewriting is equal to or greater than a predetermined value; A first prohibiting means for invalidating the erasing, rewriting, and reading of a plurality of memory cells in the first programmable ROM when the warning signal is generated; and a plurality of memory cells each storing information. At the same time, the address designating the memory cell and the control signal are provided, and the information of each memory cell can be electrically erased and rewritten in any number of second programmable ROs.
M, respectively, corresponding to the second programmable ROM of the arbitrary number of stages, receiving the address and the start signal, and receiving the address and the start signal.
Counting the number of times of erasing and rewriting of each memory cell in the programmable ROM, and when the number of erasing and rewriting becomes a predetermined value or more, a second counter of an arbitrary number of stages for generating a warning signal; When the corresponding second counter generates the warning signal, the plurality of memory cells in the corresponding second programmable ROM are provided corresponding to the arbitrary number of second programmable ROMs. Arbitrary stages of second prohibiting means for invalidating erasure, rewriting, and reading are provided, and the first one of the arbitrary number of second counters outputs a warning signal of the first counter to the first counter. Input as a start signal, and the other of the arbitrary number of second counters input the warning signal of the preceding second counter as a start signal The semiconductor memory device characterized by the. 6. A plurality of memory cells each storing information, an address designating the memory cells and a control signal designating access to the memory cells are provided, and information in each of the memory cells is erased and erased. A semiconductor memory device having a rewritable first programmable ROM, comprising: a plurality of memory cells each storing information; receiving the address designating the memory cells and the control signal; And a second programmable ROM capable of erasing and rewriting the information of the first programmable RO.
A counter that counts the number of erasures and rewrites in each memory cell in M, and generates a warning signal for each memory cell when the number of erasures and rewrites in each memory cell exceeds a predetermined value; A selection circuit that generates a selection signal indicating whether a memory cell in the first programmable ROM designated by the address is erasable and rewritable, based on a warning signal for each of the memory cells; Based on a selection signal, the first programmable RO
If the number of times of erasing and rewriting of the memory cell designated by the address in M is not equal to or more than the predetermined value, the control signal is supplied to the first programmable ROM as it is and the second programmable ROM is When the control signal given to the ROM is invalidated, and the number of times of erasing and rewriting of the memory cell specified by the address becomes equal to or more than a predetermined value, the control signal is sent to the second programmable ROM. And a switching circuit that invalidates the control signal supplied to the first programmable ROM.