JPH11232450A - Image processing device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the gray level conversion by means of a simple conversion circuit even if the gradation of output image data is increased in the gray level conversion. SOLUTION: In the gray level conversion, the data which are inputted in 8 bits are separated into the higher data of higher 2 bits and the lower data of lower 6 bits. Then the higher data are directly outputted as higher 2 bits of the output data received from a gradation conversion part. In regard to the lower 6 bits, the data of 6 bits are converted into the data of 3 buts by the comparators 1 to 3, converted into the data of 2 bits by a decoder circuit 5 and outputted as lower 2 bits. Thus, it's possible to prevent such a case where the circuitry becomes large and complicated to increase the cost and the load capacity of the circuit wiring is increased to lower the operating speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and method for converting multivalued image data into smaller multivalued image data and outputting the converted data. For example, the present invention relates to a laser beam printer, an ink jet printer, a copying machine, and computer graphics. The present invention relates to an image processing apparatus and method for performing image processing suitable for a display.

[0002]

2. Description of the Related Art In a conventional apparatus for converting input multi-valued image data into smaller multi-valued image data that can be printed out by a printing apparatus and outputting the converted data, gradation conversion is performed by a dither method. It is commonly used.

[0003] The dither matrix method is a method of expressing a high gradation by a combination of low gradation data for each preset range. If the output gradation is binary, the reference data is set for each pixel in the preset range. Is prepared, and the input data is compared with the corresponding reference data. If the input data is larger than the reference data, it is drawn as black, and if smaller, it is drawn as white. FIG. 11 shows an example of the 8 × 8 dither matrix method. Assuming that pixel data having a value of 31 is drawn, for example, at the position of 26 dots on the 16th line of the image bitmap memory, the corresponding value in the reference data table is obtained by dividing the number of lines and dots by the value in the reference table. The value 20 of the necessary table of the reference data table obtained in the above is extracted and compared with the input data. If the pixel is 26 pixels on the 18th line, the dot is black on the image bitmap. For example, if the pixel on the 18th line is 28 pixels, the value of the lookup table is 46 and the input data is smaller than this value. Is drawn.

FIG. 7 shows a configuration example of a conventional dither gradation converter. FIG. 7 is a diagram showing a circuit configuration of a conventional gradation conversion unit.

[0005] The conventional tone conversion section includes, for example, 15 8-bit comparators 200 to 202 shown in FIG. 7. These comparators 200 to 202 output 1-bit data when the input data is larger than the reference data. And outputs 0 when the values are smaller or equal.

Reference numeral 203 denotes 15 comparators 200 to
A decoder circuit for generating 4-bit output data based on the output from the decoder 202. Reference numeral 204 denotes a dither table that stores reference data, and supplies necessary reference data to each of the comparators 200 to 202 depending on the position of a pixel. Since the selection control of the output of the reference data of the dither table 204 is known, detailed description thereof is omitted.

The dither table 204 is composed of a RAM, and when the size of the dither window is 8 × 8, the required storage capacity is 8 × 8 × 15 = 7680 bits.

FIG. 8 is a circuit diagram showing a detailed configuration of the conventional 8-bit comparators 200 to 202 shown in FIG.
8, reference numerals 301 to 309 denote NAND gates, 31
EXOR (exclusive OR) gates 317 to 317
324 are inverters.

The data input from REF7 to REF0 is compared with the data input from IN7 to IN0,
If IN7-0 is larger than REF7-0, "1" is output to the output (OUT).

FIG. 9 shows the conventional decoder circuit 20 shown in FIG.
FIG. 10 is a circuit diagram showing the detailed configuration of the decoder circuit 3 of FIG. 7. Hereinafter, the detailed configuration of the 16-bit input 4-bit output decoder circuit 203 shown in FIG.

In FIG. 9, 350-352 are OR gates, 353-363 are AND gates, and 364-374 are inverters. The 16 data input from IN0 are converted into 4 bits and output from OUT3 to OUT0.

In the conventional gradation conversion apparatus having the above-described configuration, the reference values input to the comparators 200 to 202 shown in FIG.
Is the largest, and the value always input to the previous REF is assumed to be smaller than its own value.

FIG. 10 shows a state in which the input 16-bit data in the decoder circuit shown in FIG. 9 is converted into 4-bit data. As shown in FIG.
The 6-bit data is divided into 16 equal parts so that it can be represented by the output 4 bits, and the gray scale (data) to be input is represented by 4 bits according to which part of the 16 equally divided area. Make up.

That is, the input value is compared with the values of A to O (# 0 to # 15 in FIG. 7), and 4
Decode the bit output.

[0015]

However, in the above-mentioned conventional example, as the gradation of output image data increases, the size of the conversion circuit becomes large and the configuration becomes complicated, leading to an increase in cost. It becomes a cause that it becomes difficult to process an image at high speed for the integration of the image. In other words, an increase in the load capacitance of the circuit wiring did not prevent a decrease in the operation speed of the circuit.

[0016]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has, for example, the following arrangement as one means for achieving the above objects.

That is, the image processing apparatus further comprises conversion means for converting the multi-valued image data into less multi-valued image data. The conversion means divides the original image data into at least one or more upper bits and the remaining lower bits, It is characterized in that upper bits are outputted as upper data of multi-valued image data, and lower bits of the multi-valued image data to be outputted are constituted by using the lower bits.

Further, for example, the conversion means performs a predetermined image processing on the lower data, and switches the processing method of the lower data using the upper data at the time of the image processing.

Further, for example, the conversion means firstly outputs the higher-order data as output data of the input image data as it is, and performs gradation conversion using the remaining lower-order input data, thereby converting the multi-valued image data. It is characterized in that it is converted into less multi-valued image data. Alternatively, the conversion means switches the lower data conversion using at least a part of the upper data.

Further, for example, the conversion means performs gradation conversion by a dither conversion method using a dither conversion table,
In the case of gradation conversion, an upper address of input data is used as at least a part of a memory address of the dither conversion table.

Further, for example, the apparatus is further characterized by further comprising output means for outputting the converted data in the conversion means.
The output unit is a print output unit that permanently and visually displays the image data on a recording medium. Alternatively, the output means is a display output means for visually outputting the image data.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. First Embodiment FIG. 1 is a diagram showing a configuration of a printing apparatus to which an image processing apparatus according to an embodiment of the present invention is applied. In FIG. 1, reference numeral 100 denotes an external information processing apparatus (host) which generates output data and supplies the output data to the printing apparatus of the embodiment, and 111 denotes a printing apparatus having an image processing function of the embodiment.

In the printing device 111, a printing device engine 109 prints out a corresponding image according to an image signal from the image conversion unit 110. 110 is the host 1
This is an image conversion unit that converts output data from 00 into print data output to the printing device engine 109.

In the image conversion unit 110, a CPU 101 controls the entire printing apparatus 111 of this embodiment including the image conversion unit 110, which will be described in detail later, according to a control procedure stored in the ROM 102, for example. A ROM 103 for storing a program or the like, which is a control procedure of the CPU 100, has an RA 103 for temporarily storing output data from the host 100, variables for executing the program, and the like.
M.

A CPU 104 outputs, for example, output data (image data for printing) sent from the host 100 to a CPU.
The image memory 105 forms print output data that can be printed out by the printing device engine 109 under the control of the image memory 105.
And an image memory 105 for storing image data.

Further, 106 reads out the image data stored in the image memory 105, and
A video circuit which controls an interface with the printing device engine 109 which converts the video signal into a video signal which can be received by the printer 9 and outputs
Reference numeral 107 denotes a host interface circuit that manages an interface with the host 100 for receiving output data from the host 100. Reference numeral 108 denotes a bus that connects the CPU 101 to each component.

In the present embodiment having the above-described configuration, print data is generated by the host 100, taken in as output data via the host interface circuit 107 into the printing apparatus, and temporarily output to the CPU 101 by the CPU 101.
It is stored in the AM 103.

Subsequently, the CPU 101 analyzes the output data from the host 100 taken into the RAM 103, and
The image forming circuit 104 converts the image data into image data that can be printed out by the printing device engine 109,
Deployed during 05. The image data developed and generated in the image memory 105 is read by the video circuit 106, transferred to the printing device engine 109, and formed as a corresponding image on a printing medium such as paper.

In the above-described image forming process in the image forming circuit 104, the gradation of the output data from the host 100 is higher than the gradation of the image printable by the printing engine 109. in case of,
In some cases, the image quality of the actual print output image may be different from the print image quality expected on the host 100 side.

Therefore, in such a case, it is necessary to convert the gradation of the output data into image data having a gradation that can be printed out by the printing device engine 109. Therefore, in such a case, the image forming circuit 104 of the present embodiment uses the printing device engine when forming an image in the image memory 105 or the image data expanded in the image memory 105 via the video circuit 106. 109, the gradation conversion processing is performed either when sending the data.

FIG. 2 shows the detailed configuration of the gradation conversion unit for performing the gradation conversion processing in the image forming circuit 104. In the present embodiment, the gradation is converted by dither conversion processing with reference to a dither reference data table.

In FIG. 2, reference numerals 1 to 3 denote data comparators, which have a 6-bit input circuit configuration in this embodiment. 4 is a dither table,
The reference data is supplied to the comparators 1 to 3.

The outputs of the comparators 1 to 3 are connected to a decoder 5, converted into 2-bit data by the decoder 5, and taken out as an output of the gradation converter together with the upper bits of the input data.

That is, in the present embodiment, as shown in FIG. 2, first, output data from the host 100, for example, input with 8 bits on the input side is converted into upper 2 bits of upper data and lower 6 bits of lower data. Separate from lower data. The upper data is output as it is as the upper 2 bits of the output data from the gradation converter.

On the other hand, the lower 6 bits include comparators 1 to
In step 3, the 6-bit data is converted into 3-bit data. The 3-bit data is further converted into 2-bit data via the decoder circuit 5 and output as lower 2 bits of output data from the gradation conversion unit. Is done.

6-bit comparators 1 to 3 shown in FIG.
3 is shown in FIG. In FIG.
6 is a NAND gate, 477 to 481 are EXOR (exclusive OR) gates, and 482 to 487 are inverters.

The dither table 4 is used for REF5 to REF0.
Is input, and the processing target image data is input to IN5 to IN0. And IN5 to IN0
Is larger than the reference data of REF5 to REF0, "1" is output to the output OUT.

FIG. 4 shows a detailed configuration of the decoder circuit 5 shown in FIG. In FIG. 4, reference numeral 400 denotes an OR gate;
Is an AND gate, and 402 is an inverter.

FIG. 5 shows a state in which the input 4-bit data is converted into 2-bit data in the decoder circuit of the present embodiment shown in FIG. As shown in FIG. 5, it is configured to represent, in two bits, which part of a quadrant area in which the input 4-bit data can be represented by the output 2 bits.

According to the present embodiment, when the same 8-bit image data as the above-mentioned conventional one is received, even when this data is converted into 4-bit data, as shown in FIG. The converter may be a 6-bit input circuit, and the output from the decoder circuit may be a 2-bit output. Therefore, the number of comparators may be three. Even when the same 8 × 8 window as the conventional example is used for the dither table, an image memory having a storage capacity of 8 × 8 × 6 × 3 = 1152 bits may be prepared, and the configuration of the conversion circuit is simplified. And can be.

That is, among the input image data, first, the higher-order data is output as it is as output data, and the actual gradation conversion is performed using the remaining lower-order input data, thereby reducing the circuit scale. it can.

As described above, according to the present embodiment, when converting multivalued grayscale data into smaller grayscale data, the upper part of the input data is output as it is. , While reducing the required circuit size,
High-speed gradation conversion can be performed.

With the configuration of the present embodiment described above, the number of dither reference tables is one compared to the conventional example.
It can be reduced to 5%, and the logic circuit to be used can be constituted by 1/4 or less of the conventional one.

[Second Embodiment] FIG. 6 is a diagram showing a detailed configuration of a gradation converter according to a second embodiment of the present invention. In the second embodiment, the other basic configuration is the same as that of the above-described first embodiment, and therefore the detailed description of the same configuration as that of the first embodiment will be omitted.

In FIG. 6, the same components as those in the first embodiment shown in FIG. 2 described above are denoted by the same reference numerals, and detailed description thereof will be omitted. In the second embodiment shown in FIG. 6, the configuration of the dither table shown in FIG. 6 is different, and upper two bits used as direct output among the input data to the dither table 6 are input as a switching signal. The points are different.

In other words, the dither table 4 for dither conversion of the first embodiment shown in FIG. 2 has a reference specified only by the horizontal coordinate and the vertical coordinate regardless of the value of the upper bit of the input data. Although the data is supplied to the comparators 1 to 3, in the second embodiment, a plurality of different types of dithers (for example, four types of upper 2 bits) differ according to the value of the upper 2 bits of the input data. A conversion table is prepared to enable more detailed dither conversion.

With this configuration, even when the relationship between the input data and the output data is poor in the proportional relationship, the gradation conversion process according to the lower bits is changed to obtain the optimum reproducibility. Good gradation conversion processing can be performed. Even in this case, the capacity of the dither table is 8 even if the same 8 × 8 dither matrix is used.
* 8 * 4 * 6 * 3 = 4608 bits.

As described above, according to the second embodiment, the lower data conversion is switched by using part or all of the upper output which is output as it is, thereby improving the conversion accuracy. Is achieved. Further, in the case of gradation conversion using the dither table, by inputting the upper address of the input data to the address of the memory of the dither table, the conversion accuracy can be improved with a simple configuration.

For example, the dither reference table can be reduced to 60% as compared with the conventional example. Furthermore, since the conversion format of dither can be changed depending on the input data, good gradation conversion can be performed even when the linearity of the density relationship between the input data and the actual print is poor.

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus including a single device can be used. (For example, a copying machine, a facsimile machine, etc.).

Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instructions of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the flowcharts described above.

[0057]

As described above, according to the present invention, when converting multi-valued grayscale data into smaller grayscale data, the upper part of the input data is output as it is. The required circuit scale can be reduced, and high-speed gradation conversion can be performed.

Further, the capacity of the dither reference table can be greatly reduced as compared with the conventional example.

Further, since it is possible to change the dither conversion format depending on the input data, it is possible to select an appropriate dither conversion format, and it is possible to select a straight line between the input data and the actual print density relationship. Good gradation conversion is possible even when the performance is poor.

[0060]

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a printing apparatus to which an image processing apparatus according to an embodiment of the present invention is applied;

FIG. 2 is a diagram illustrating a detailed configuration of a gradation conversion unit according to the embodiment.

FIG. 3 is a diagram showing a detailed configuration of a 6-bit comparator shown in FIG. 2;

FIG. 4 is a diagram showing a detailed configuration of a decoder circuit 5 shown in FIG.

FIG. 5 is a diagram showing input 4 in the decoder circuit shown in FIG. 4;
FIG. 3 is a diagram illustrating a state in which bit data is converted into 2-bit data.

FIG. 6 is a diagram showing a detailed configuration of a gradation conversion unit according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a circuit configuration of a conventional tone conversion unit.

8 is a circuit diagram showing a detailed configuration of the conventional comparator shown in FIG.

9 is a circuit diagram showing a detailed configuration of the conventional decoder circuit shown in FIG.

10 is a diagram showing a state where 16-bit data input to the decoder circuit shown in FIG. 9 is converted into 4-bit data.

[Explanation of symbols]

1, 2, 3 Comparator 4, 6, 204 Dither table 5, 200, 201, 202 Decoder 100 Host 101 CPU 102 ROM 103 RAM 104 Image forming circuit 105 Image memory 106 Video circuit 107 Host I / F circuit 108 Bus 109 Printing device Engine 110 Image control circuit 111 Printing device 301 to 309, 353 to 363, 470 to 476 N
AND gate 310-316, 477-481 EXOR gate 317-324, 364-374, 402, 482-4
87, inverter 350-352 OR gate 400 OR gate 401 AND gate

Claims (17)

[Claims] A conversion unit configured to convert the multi-valued image data into less multi-valued image data, wherein the conversion unit divides the original image data into at least one or more upper bits and the remaining lower bits, An image processing apparatus comprising: outputting higher-order bits of multi-valued image data as higher-order data; and using the lower-order bits to form lower-order data of multi-valued image data. 2. The apparatus according to claim 1, wherein said conversion means performs predetermined image processing on said lower data, and switches the processing method of lower data using said upper data during image processing. Image processing device. 3. The conversion means outputs high-order data as output data among the input image data first, and performs gradation conversion using the remaining low-order input data, thereby converting the multi-valued image data. 3. The image processing apparatus according to claim 2, wherein the image data is converted into small multi-valued image data. 4. The image processing apparatus according to claim 3, wherein the conversion unit switches the conversion of the lower data using at least a part of the higher data. 5. The conversion means performs gradation conversion by a dither conversion method using a dither conversion table. In the case of gradation conversion, an upper address of input data is stored in at least a part of a memory address of the dither conversion table. The image processing apparatus according to claim 2, wherein the image processing apparatus is used. 6. The image processing apparatus according to claim 1, further comprising an output unit configured to output the converted data from the conversion unit. 7. The image processing apparatus according to claim 6, wherein the output unit is a print output unit that permanently and visually displays the image data on a recording medium. 8. The apparatus according to claim 6, wherein said output means is a display output means for visually outputting and outputting image data.
The image processing apparatus according to any one of the preceding claims. 9. An image processing method for converting multi-valued image data into less multi-valued image data, wherein in the conversion, the original image data is divided into at least one or more upper bits and the remaining lower bits. Outputting the higher-order bits as higher-order data of multi-valued image data to be output, and outputting the lower-order bits as lower-order data of the multi-valued image data to be output. 10. The image processing method according to claim 9, further comprising performing predetermined image processing on the lower data, and switching the processing method of the lower data using the upper data at the time of the image processing. 11. In the conversion, high-level data of input image data is first output as it is as output data, and gradation conversion is performed using the remaining low-level input data to convert multi-valued image data. 11. The image processing method according to claim 10, wherein the image data is converted into small multi-valued image data. 12. The image processing method according to claim 11, wherein, in the conversion, switching of lower data conversion is performed using at least a part of the upper data. 13. In the conversion, gradation conversion is performed by a dither conversion method using a dither conversion table. In the case of gradation conversion, an upper address of input data is stored in at least a part of a memory address of the dither conversion table. The image processing method according to claim 10, wherein the image processing method is used. 14. The image processing method according to claim 9, wherein said conversion data is printed out on a recording medium. 15. The image processing method according to claim 9, wherein said conversion data is displayed and output on a display screen. 16. A computer program sequence for realizing the function according to any one of claims 1 to 15. 17. A computer-readable storage medium storing a computer control procedure for realizing the functions according to claim 1. Description: