JPH02155762A - Recorder - Google Patents

Abstract

PURPOSE:To replace a dot density without using a special application software by generating and storing dot information received in a first recording dot density, and generating an interpolated dot information of a second recording dot density on the basis of it. CONSTITUTION:When a line memory 6 is in writing mode and line memories 7, 8 are in reading mode, a data selector 14 selects the read data D2 of the line memory 7, and outputs a DS1 signal to a comparison discriminator 10. A data selector 15 selects the read data D3 of the line memory 8, and outputs a DS2 signal to the comparison discriminator 10. The comparison discriminator 10 inputting a DS1 signal zone DS2 signal compares the data, and outputs an output signal responsive to the result to a shift register 20. This shift register 20 parallel/serial-converts a 3-bit input signal with the clock of a LCLK, and outputs 1-bit signal to a line memory 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording device such as a laser beam printer.

[Prior Art] In recent years, laser beam printers have been widely used as output devices for computers. Especially low density (e.g. 30
0dpi) laser beam printers are rapidly becoming popular due to their advantages such as low cost and compactness.

For example, in a laser beam printer that prints at a printing density of 300 dpi, as shown in FIG. The printer controller 5 receives code data sent from the external host computer 54, generates page information consisting of dot data based on this code data, and sequentially sends the dot data to the printer engine section 51.
It consists of 2.

Further, the host computer 54 loads one application software from a floppy disk 55 containing many types of application software and starts the program.For example, if the application software is for document creation, It functions as a word processor and allows the user to create and store a large number of data information.

On the other hand, the printer engine section 51 has a higher printing density and higher gradation in order to perform higher quality printing, and has a printer engine of 600 dpi or more, or a printer engine that handles multi-value data. Printer engines have also been announced in recent years.

[Problem to be solved by the invention] However, the above-mentioned high-density printer engine (600
Conventionally, the printer controller 52 connected to the print density (600 dpi) has required an amount of data memory corresponding to each print density (600 dpi) (for example, in the case of 600 dpf, the memory is four times that of 300 dpi).

In addition, application software had to be created specifically for high-density printers, and the numerous application software mentioned above could not be used as is for high-density printers.

For example, FIG. 2 is a diagram showing the dot configuration of the alphabet raJ at a print density of 300 dpi.

If the dot configuration is used as it is and printed at a print density of 600 dpi, the character size will be reduced to 1/2 in both the vertical and horizontal directions.

Therefore, one data interpolation method is to simply double the dot configuration in both the vertical and horizontal directions and apply the dot configuration of 300 dpi to 600 dpi. If you convert 7, the size of the image will not be reduced, but the
When printing at 600 dpi and when printing at 600 dpi, the outlines and jaggedness of the characters were not improved, and there was a drawback that it was not possible to make the print engine beautiful to the fullest (600 dpi).

The present invention has been made in view of the above-mentioned conventional drawbacks, and aims to provide a recording device that can perform high-density recording by using many existing application software created for low-density recording as they are. purpose.

Another object of the present invention is to provide a recording device that converts recorded data developed as a low recording density into recorded data with a high recording density using a minimum memory, and performs high quality recording at a high recording density.

[Means for Solving the Problems] In order to achieve the above object, a recording device of the present invention has the following configuration. That is, first dot information generation means for generating dot information at a first recording dot density, storage means for storing dot information from the first dot information generation means, and dot information stored in the storage means. and second dot information generation means for generating interpolated dot information of a second recording dot density based on the second recording dot density.

[Operation] In the above configuration, dot information received at the first recording dot density is generated and stored. Then, based on the stored dot information, it operates to generate interpolated dot information of the second recording dot density.

[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

<Description of Apparatus> FIG. 4A is a block diagram showing a first embodiment of the present invention. As shown in FIG. 4A, the circuit of this embodiment includes a printer controller 52 as shown in FIG. This is a data conversion circuit inserted between the printer engine section 51 and a state in which it is configured as a part of the printer engine section 51 (of course, it may also be a part of the printer controller). Further, the printer controller 52 sends out dot data of 300 dpt, and the printer engine section 51 is shown as an example of a data conversion circuit when receiving dot data of 600 dpi. Signal (dot information)
a laser driver, which modulates the laser beam based on
It consists of a scanner for scanning the beam, a photosensitive drum, etc.

The printer controller 52 responds to the horizontal synchronization signal HSYNC output by the horizontal synchronization signal generation circuit 4
The image signal VDO of 0 dpi and the image clock VCLK are sent to the printer engine 51. The horizontal synchronization signal generation circuit 4 is a circuit that sends out a horizontal synchronization signal based on a well-known beam detect signal BD, which is a synchronization signal in the main scanning direction.

On the other hand, the printer engine 51 prints a laser drive signal LD, which is converted to 600 dpi from a 300 dpi image signal VDO and an image clock VCLK by a data conversion circuit, the details of which will be described later, at the 600 dpi printer engine 51. be.

Description of Interpolation> Next, the above data conversion circuit will be described in more detail with reference to FIG. 4A.

1 is a frequency multiplier circuit that multiplies the frequency of the image clock VCLK to obtain a clock VCLK' whose frequency is doubled. 5 is an oscillation circuit, and an image clock VCL
A clock LCLK1 having a frequency 12 times that of K is generated. A frequency dividing circuit 21 divides the frequency by three and outputs a clock LCLK2 having a frequency four times that of VCLK. 11.12.
13 is a switching circuit, and the clock VCLK' or LCL
K is selected and supplied as a write clock or a read clock for each line memory 6 to 8.

A demultiplexer 2 has a function of selectively supplying the image signal VDO to each of the line memories 6 to 8. 4 is a beam detect signal (hereinafter, BD scratch signal is counted,
One horizontal synchronization signal HSY every time two BD scratch signals are input
Output NC.

Reference numeral 3 denotes a device control circuit, which controls the demultiplexer 2, each switching circuit 11 to 13, and each data selector 14 to 16, which will be described later, to write or read each line based on the BD scratch signal.

This device control circuit 3 controls each line memory 6 to 8.
The image signal VDO is written into one of the line memories using the clock VCLK', and the image signal is read from the other two line memories based on the clock LCLK.

This operation is performed sequentially; when writing to line memory 6, line memory 7 and line memory 8 perform a read operation, and at the next timing, line memory 7 performs a write operation, and line memories 6 and 8 perform a read operation. Similarly, at the next timing, the line memory 8 performs a write operation, the line memories 6 and 7 perform a read operation, and the above-described control is repeated.

Note that each line memory 6 to 8 has a memory capacity twice as large as the data in the main scanning direction of 300 dpi, that is, 600 dpi.
data memory capacity in the main scanning direction. Then, the image signals read from each line memory 6 to 8 are transferred to Di, D2, . This will be explained below as D3.

14 and 15 are data selectors 1.2, and read signals DI for each of the line memories 6 to 8 described above.

D2. For example, when the line memory 6 is in a write operation and the line memory 6 is in a write operation,
When the line memory 7.8 is in a read operation, the data selector 14 selects the read data D2 of the line memory 7 and outputs the DS1 signal to the comparison/determination circuit 10. Also,
The data selector 15 selects the read data D3 of the line memory 8 and outputs the DS2 signal to the comparison/determination circuit 10. Then, the comparison/discrimination circuit 10 which receives the DSL signal and the DS2 signal compares each data and outputs an output signal X1. X z and X s are output to the shift register 20. This shift register 20 is "3"
Parallel-to-serial conversion is performed on an input signal of "1 bit" using the LCLK clock, and a signal of "1 bit" is output to the line memory 9.

Note that the memory capacity of the line memory 9 that stores this output signal is three times that of each of the line memories 6 to 8 described above. LCLK is used as a clock for writing and reading from this line memory 9. Also,
Writing to each line memory 6 to 8 and line memory 9,
Control of the read operation and selection control of the data selectors 14 and 15 are executed by the device control circuit 3.

Next, the data selector 16 selects each signal DI-D3 read from each line memory 6 to 8 and the line memory 9.
One of the signals D4 read from the signal D4 is selected and outputted as the laser drive signal LD. The selection control is similarly performed by the device control circuit 3.

Next, an example of the comparison/discrimination circuit 10 described above will be described below with reference to the configuration diagram shown in FIG.

As shown, input signals DSL and DS2 are each input to 7-bit shift registers 17 and 18. Shift output AB, C, D, E, D, G of each shift register
, and a, b, c, de, f, and g are input to the logic circuit 19. Divide the pixel of interest into three in the main scanning direction,
A logical operation is performed on each of them according to the logical formula shown below, and as a result, "3-bit" signals of output signals x1 to X are set.

x,=Aabcdef+Fabcdef+Bbcdef
+Ebcde +Ccd +Dd +ABCDEF+abcdef = (A+F)abcdef + (B+E)bade + (Cc+D)d +ABCDEF+abcdef Xs =Aabcdefg+Gabcdefg+Bb
cdef +Fbcdef +Ccde +Ecde +Dd+BCDEF+bcde f = (A+G)abcdefg + (B+F)bcdef + (C+E)cde +Dd+BCDEF+bcde f xs =Bbcdefg+Gbcdefg+Ccde
f +Fcdef +Dd +Ede +BCDEFG+bcdef g = (B1G)bCdefg + (C+F)cdef + (D+Ee)d +BCDEFG+bcdef g To realize the above logical formula, a memory FROM as shown in FIG. 7 is used. can do 0
As shown in the figure, the input signals A-G, B-'-g are FR
Connected to 80~A, 3 as the address signal of OM,
Output signals x1 to x3 are output from terminals D1 to D.

In this case, data has been written in advance according to the above-mentioned logical formula.

FIG. 8 is a diagram showing the result of printing by the method of this embodiment. As can be seen from the diagram, the jagged portion of the alphabet raJ has been improved compared to FIG. 3.

Incidentally, FIG. 4B is a timing chart of the data conversion circuit in this embodiment.

As explained above, according to this embodiment, it is possible to use the application software as is, and
Enables high-density printing with minimum memory capacity.

[Other Embodiments] FIG. 9 is a diagram showing a dot configuration when the logical expression in the above-mentioned embodiment is replaced with the following logical expression.

Comparing this result with FIG. 8, it can be seen that the outline of the characters has been further improved.

X+ = (Aa+Ff)bcde + (B+Ee)bed + (Cc+D)d +BCDb +ABCDEF+abcdef X2: (A+G)abcdefg+ (B+F)
bcdef + (C+E)cde +Dd+BCDEF+bcdef f X3 = (Bb+Gg)cdef+ (Cc
+F)def +(D+Ee) d +DEFf +BCDEFG+bcdef g According to this embodiment, high-quality printing can be performed with higher printing density.

In the above embodiment, 300 dpi and 600 dpi were used as an example, but a combination of 400 dpi and 800 dpi may also be used.

Furthermore, in the above-described embodiments, the printer engine section is explained using a laser beam printer as an example, but it may also be an LED printer or an inkjet printer.

Furthermore, in the embodiment described above, 14 pixels surrounding the pixel of interest
Although the interpolation data is determined by a logical formula for each pixel, it may be 14 or more, and the logical formula is not limited to this example but may be any other logical formula.

Further, although the pixel of interest is divided into three in the main scanning direction, it may be divided into four or more.

[Effects of the Invention] As explained above, according to the present invention, dot densities can be exchanged without using special application software.

[Brief explanation of the drawing]

Figure 1 is a diagram explaining the configuration of a laser beam printer, Figure 2 is a diagram showing the dot configuration in the conventional example, Figure 3 is a diagram showing the case where dot conversion is performed, and Figure 4A is the data in this embodiment. FIG. 4B is a block diagram of the conversion circuit; FIG. 4B is a timing chart of the data conversion circuit in this embodiment; FIG. 5 is a diagram showing the configuration of the comparison/discrimination circuit in this embodiment; FIG. FIG. 7 is a diagram showing a configuration example of a logic circuit in this embodiment. FIG. 8 is a diagram showing a dot configuration in this embodiment. FIG. 9 is a diagram showing a dot configuration in this embodiment. FIG. 3 is a diagram showing the configuration. In the figure, 1...multiplier circuit, 2... demultiplexer,
3... Device control circuit, 4... Horizontal synchronization signal generation circuit, 5... Oscillation circuit, 6 to 9... Line memory,
10... Comparison/discrimination circuit, 11-13... Switching circuit,
14-16...data selector, 17,18.20.
...Shift register, 19...Logic circuit, 21...
It is a frequency divider. Figure 2 Figure 8 Figure 8

Claims (1)

[Scope of Claims] First dot information generation means for generating dot information at a first recording dot density; storage means for storing dot information from the first dot information generation means; and second dot information generation means for generating interpolated dot information of a second recording dot density based on the dot information obtained by recording.