JPH11220383A - Counter device with output holding function, clock controller, counter device, and interval timer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a counter device which can read or write a timer counter stably with a timer clock asynchronous with a system clock, a clock controller which stably supplies the timer clock, and a interval timer device which is equipped with those devices and actualized by easy designing. SOLUTION: The interval timer device is equipped with the timer counter 11 which inputs and counts the TLCK (timer clock) asynchronous with the CLK (system clock) or writes external input data from an asynchronous preset terminal, a means 12 which decides the timing of counter value update, a readout temporary register 13 which inputs and holds the counter value again when the timing is constant, a means 14 which controls whether or not the TCLK is allowed to pass, a write temporary register 16 which temporarily stores the external input data when the timer clock passes, and a means 15 which generates a control signal showing the timing of the writing of the temporarily stored data to the timer counter 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for use in a system including a CPU and the like, and a counter apparatus having a timer counter operating with the system clock and the timer clock and operating with the timer clock, and the timer clock. The present invention relates to a clock control device for controlling the supply of power and an interval timer device provided with these devices.

[0002]

2. Description of the Related Art Generally, a clock (timer clock) supplied to a circuit for keeping a fixed time such as an interval timer is asynchronous with a system clock supplied to a CPU or the like. Conventionally, the system clock supplied to the CPU has been used at the highest possible frequency in order to pursue high-speed operation.However, a timer clock such as an interval timer for counting a certain time requires an extremely fast clock. In general, it should not. Therefore, a method of sampling the timer clock with the system clock and using the timer clock in synchronization with the system clock has been generally used. However, with the advent of mobile devices and other devices that require low power consumption, when the system performs little processing, such as in a standby state, it is necessary to lower the system clock frequency or stop the system clock in some cases. It has become. On the other hand, since the interval timer ticks a fixed time, it is necessary to always supply a timer clock having a constant frequency, and the frequency of the system clock may be lower than the frequency of the timer clock. In some cases, sampling techniques could not be used.

[0003] Therefore, a method of correctly reading the value of a timer counter that operates asynchronously with the system clock (for example, Japanese Patent Application Laid-Open No. 6-197010) and a method of controlling the on / off of an asynchronous clock that can be realized with a simple circuit are proposed. It has been proposed (for example, JP-A-6-125247).

When the system clock and the timer clock are asynchronous, writing data to the timer counter includes writing data from the CPU in synchronization with the system clock and subtracting 1 from the timer counter data in synchronization with the timer clock. There is a write access to the value (1 added value if the timer counter is an up counter), but the write access from the CPU synchronized with the system clock and the write access from the timer counter subtracted value synchronized with the timer clock are within a minute time interval. There is a possibility that the value of the timer counter becomes an incorrect value. For example, assuming that the delay time for subtracting 1 in the circuit shown in FIG. 12 is Dm, as shown in the time chart of FIG. 13, when there is a rising edge of the timer clock at time △ immediately after writing from the CPU to the timer counter, If Dm> △, the subtraction time Dm of the one-subtractor cannot be ensured, and the value obtained by correctly subtracting one is not written into the timer counter. In addition, it is not easy to design the selector 161 for the system clock (CLK) and the timer clock (TCLK) so as not to generate a whisker-like pulse, and it is very difficult to adjust the clock skew.

In order to avoid this, conventionally, as shown in FIG. 14, a method has been used in which an asynchronous TCLK is sampled by CLK, and then TCLK synchronized with CLK is supplied to a timer counter.

[0006]

However, the method described in Japanese Patent Laid-Open No. 6-197010 is based on the timing chart (FIG. 16) of the circuit (FIG. 15).
When the timer counter transitions from N-2 to N-3 by latching the value of the timer counter with the ATCH_1 signal,
It is explained that the timer counter value can be read correctly without taking the timer counter value during transition,
Since the method uses both the rising edge and the falling edge of the system clock, the control is complicated. That is, as shown in FIG. 15, the counter clock (C_CLK) (corresponding to the timer clock of the present invention)
Is divided by the system clock (S_C)
LK), so that C_CLK
It is difficult to determine the relationship between and S_CLK. For example, the delay from the clock input terminal D to the terminal Q of the flip-flop FF1 shown in FIG.
LK division delay D (TGL) and flip-flop FF
When the sum of the setup time (FF2), which is the setup time of C2, is larger than the phase difference Ｃ between C_CLK and S_CLK, the operation shown in the time chart of FIG. The latch signal LATCH_1 has the same timing as LATCH_0. Therefore, the counter value is latched during the transition of the counter value, and accurate reading cannot be performed. To avoid this, D (TGL) + Setup (FF2) <
It is necessary to guarantee Δ, and it is necessary to perform a design by strictly analyzing variations in element characteristics and variations in wiring delay, which makes the design extremely difficult.

In Japanese Patent Application Laid-Open No. 6-125247, FIG.
8, a specific circuit shown in FIG. 19 is used. After the signal TON, which is a signal for controlling ON / OFF of the timer clock, becomes L, as shown in the timing chart of the circuit in FIG. After issuing a command to stop TCLK), one pulse of TCLK may be supplied. When this is used for the clock of the interval timer, there is a possibility that the timer count operation is performed once after the CPU turns off the interval timer. If this phenomenon occurs, for example, after turning off the interval timer in the user program, the timer counter may advance by one after a while and an interrupt signal from the timer may be generated. Will be out of sync.

Further, in the circuit shown in FIG. 14, when the system enters a low-speed operation state, the frequency of the system clock becomes lower than the frequency of the timer clock, and the timer cannot be sampled by the system clock. There is. On the other hand, when the timer counter is stopped, the timer clock is not supplied to the timer counter. However, even in that case, writing to the timer counter must be performed. There is also a method of generating a clock specially when there is a write to the timer counter, but the clock circuit becomes very complicated, and it is very difficult to realize the circuit by avoiding the generation of mustache-like pulses and clock skew. Have difficulty. That is, in the write access to the timer counter, the frequency of the timer clock is f (TCLK) and the frequency of the system clock is f (CCLK).
LK), f (TCLK = 0), f (CLK)>
In both cases of f (TCLK) and f (CLK) <f (TCLK), write access from the CPU to the timer counter is possible, and f (CLK = 0),
f (CLK) <f (TCLK) and f (CLK)> f
In any case of (TCLK), in synchronization with TCLK,
A timer counter writing circuit capable of writing a subtraction value to a timer counter can be realized without sampling TCLK with CLK, avoiding generation of whisker-like pulses and clock skew, and with an easy clock wiring design. Is required.

As described above, the prior art cannot cope with the case where the system clock is slow, or even if it can cope with it, the circuit becomes very complicated, and it takes much effort to realize it, and in some cases, malfunctions may occur. There was a problem that it would.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a counter device capable of reading or writing a timer counter stably with a timer clock asynchronous with a system clock, and stabilizing the timer clock. It is an object of the present invention to provide a clock control device to be supplied as a clock, and an interval timer device provided with these devices, which can be realized with an easy design.

[0011]

In order to solve the above-mentioned problems, a counter device with an output holding function according to the present invention (claim 1) is a counter device which samples a timer clock asynchronous with a system clock by the system clock. A counter for counting by inputting the timer clock, read-out temporary storage means for taking in and holding the value of the counter at a first timing synchronized with the system clock, and a system clock half before and after the first timing, respectively. Means for determining whether or not there is a second timing at which the counter updates the counter value with the timer clock in the cycle section, and wherein the read temporary storage means has the second timing in the section. The value of the above counter is captured and held again when A.

In the counter device with an output holding function according to the present invention (claim 2), in the counter device with the output holding function according to claim 1, the read temporary storage means includes the second timing in the section. When there is a delay, the value of the counter is fetched and held again one cycle after the system clock from the first timing.

The clock control device according to the present invention (claim 3) is a clock control device for controlling the passage / non-passage of a timer clock by inputting a control signal synchronized with a system clock. A delay means for delaying a fixed time, a timer clock delayed by the delay means and the control signal are input, and when the timer clock is at a low level, the control signal is output as it is, and when the timer clock is at a high level. Storage means for holding and outputting an input control signal when the signal changes to the high level, and gate means for outputting a high level when the output from the timer clock and the storage means is at a high level. Things.

Further, a counter device according to the present invention (claim 4) is a counter device for controlling start or stop of a count operation by passing or non-passing of a timer clock asynchronous with a system clock. Clock control means for controlling the passage / non-passage of the timer clock in response to the controlled control signal, a flip-flop element having an asynchronous preset terminal, and the timer clock supplied to the flip-flop element from the clock control means A counter for inputting the external input data from the asynchronous preset terminal when the timer clock is supplied, and a counter for counting the timer clock by inputting the timer clock to the flip-flop element when the timer clock is supplied. The clock control means is Writing temporary storage means for temporarily storing the external input data and outputting the data to the counter when the clock is passed; and a first timer counter value after the data written in the writing temporary storage means is stabilized. Signal generating means for generating a control signal for writing the value of the data into the counter at the timing of updating.

In the counter device according to the present invention (claim 5), in the counter device according to claim 4, the counter is controlled by the signal generation unit while the clock control unit passes the timer clock. When the signal is lost, the flip-flop element counts by subtracting 1 from the value of data input before the signal disappears, under the control of the timer clock. .

The counter device according to the present invention (claim 6) is the counter device according to claim 4 or 5, wherein the clock control means is the clock control device according to claim 3.

Further, an interval timer device according to the present invention (claim 7) is an interval timer device having a counter device that operates with a timer clock that is asynchronous with a system clock, wherein the counter device is as defined in claim 1. A counter device having an output holding function and a counter device according to claim 4 are provided.

The interval timer device according to the present invention (claim 8) is the interval timer device according to claim 7, wherein the read temporary storage means of the counter device with the output holding function and the write temporary storage device of the counter device. Instead of the storage means, one storage means for switching to one of read storage and write storage for storage is provided.

[0019]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of an interval timer device according to Embodiment 1 of the present invention. As shown in FIG. 1, the interval timer device includes a timer counter 11, a TCLK rising determination circuit 12, a read temporary register 13, a timer clock on / off circuit 14, a write synchronization circuit 15, and a write temporary register 16.
That is, the interval timer device includes a counter device having an output holding function including a timer counter 11, a TCLK rising determination circuit 12, and a read temporary register 13, a clock control device including a timer clock on / off circuit 14, a timer counter 11, and a timer clock on / off. It comprises a circuit 14, a write synchronizing circuit 15, and a counter device comprising a write temporary register 16.

Hereinafter, each device constituting the interval timer device shown in FIG. 1 will be described in detail by dividing into first to third embodiments. The following description is based on the premise that the above devices operate based on the rising edge of the system clock, the timer counter operates based on the rising edge of the timer clock, and the timer counter is a down counter.

Embodiment 1 FIG. 2 is a block diagram showing a configuration of a counter device with an output holding function according to Embodiment 1. In FIG. 2, TCLK is a timer clock,
This is a clock of a circuit such as an interval timer for counting a certain time. TRD_2 is a counter readout advance signal, which is at least 2 × T_
This occurs at a timing before clk. Where T_clk
Is the cycle of CLK, and T_tclk is the cycle of TCLK. Further, TRD_1 is a TCLK rising determination signal, which indicates the rising of TCLK. CLK is a system clock and is supplied to a CPU or the like. Reference numeral 11 denotes a timer counter, which counts down at the rising edge of TCLK. 12 is a TCLK rising judgment circuit, TR
It is determined whether TCLK has risen between the first half cycle and the second half cycle of the rising edge of CLK when D_2 is valid, and if TCLK has risen, TRD_
Issue TRD_1 at the next system clock cycle after 2. Reference numeral 13 denotes a read temporary register. When TRD_2 is at the H level or TRD_1 is at the H level, the data CNT [n−1:
0] is written.

FIG. 3 is a diagram showing a timing chart in the counter device with an output holding function of FIG. In the figure, TRD is a read cycle in which data taken into the read temporary register 13 is read by an external CPU or the like at a timing t0.

Next, the operation of the counter device with an output holding function according to the first embodiment will be schematically described with reference to FIG. At the rising edge timing t0 of the CLK in the H section of TRD_2 synchronized with the clock CLK, the data CNT of the timer counter 11 is
[N−1: 0] is taken into the read temporary register 13. As shown in FIG. 3A, when there is a rising edge of TCLK in the first half cycle section R0 of the timing t0, TRD_1 becomes H, and at the next CLK rising edge timing t1, the counter value CNT [n −
1: 0] is taken into the read temporary register 13, and this data is taken into the CPU or the like by TRD. As shown in FIG. 3B, when there is no rising edge of TCLK in the section R0, TRD_1 does not become H, and the data N taken in at the time t0 is read out to the outside by TRD and the CPU reads out.
Etc.

FIG. 4 is a circuit diagram showing an example of a circuit of the counter device with an output holding function shown in FIG. 4, the same reference numerals as those in FIG. 2 denote the same or corresponding parts. Also, 3
1, 32, 34 and 38 are flip-flops,
31 and 32 are the falling edges of CLK, and 34 and 3
Reference numeral 8 denotes a rising edge of CLK, each of which takes in input data D, and 34 denotes input data (TRD_2) of T_clk.
Output with a delay. 33, 35, 36 and 37 are logic gates. By passing the signal through the logic gate 33, the TCL during the first and second half cycles of the rising edge of CLK is set.
The logic gate 35 determines whether or not there has been a rise of K, and the logic gate 35 performs an AND logic operation on the signal passed through the logic gate 33 and the signal obtained by delaying TRD_2 by T_clk, thereby giving TRD_1 to the read temporary register 13 and permitting write permission. To instruct.

Next, the operation of the counter device with an output holding function according to the first embodiment will be described with reference to FIGS. First, the flip-flops 31 and 32 sample TCLK at the falling edge of CLK and pass through the logic gate 33 to determine whether or not TCLK has risen during the first and second half cycles of CLK rising. That is, in the case of FIG. 3A, the flip-flop 31 samples TCLK (L) and outputs an L-level signal at the fall of CLK in the first half cycle of the timing t0. By the falling edge of CLK in the second half cycle of the timing t0,
The flip-flop 32 samples and outputs the output (L), and the flip-flop 31 outputs
(H) is sampled and output. In the logic gate 33, the output (H) of the flip-flop 31 and the negative logic of the output (L) of the flip-flop 32 are ANDed to be at the H level, so that the rising edge of CLK (t
It is determined that TCLK has risen during the first and second half cycles of 0). On the other hand, in the case of FIG. 3B, the output of the flip-flop 31 (L) and the output (H) of the flip-flop 32 are output from the logic gate 33 by the fall of CLK in the second half cycle of the timing t0. Since the logic becomes L level by taking AND logic with negative logic, it is determined that TCLK has not risen.

In the logic gate 35, the signal (H) passed through the logic gate 33 in the case of FIG. 3A and the signal obtained by delaying TRD_2 by T_clk by the flip-flop 34 are AND-operated, so that readout is temporarily performed. A write enable signal TRD_1 for the register 13 is given. That is, the flip-flop 34 takes in TRD_2 at the fall of CLK in the first half cycle of t0, delays by T_clk and outputs it at the fall of CLK in the second half cycle of t0, and passes through (H) of the TRD_2 and the logic gate 33. With the signal (H), the AND logic is taken and the level becomes H level, and TRD_1 is supplied to the read temporary register 13. FIG.
In the case of (b), the signal (L) passed through the logic gate 33 and the flip-flop 34 convert TRD_2 to T_c.
The logic gate 35 takes an AND logic with the signal (H) delayed by lk. The AND logic does not supply the L level, that is, the write enable signal TRD_1.

In the read temporary register 13, TR
When one of D_2 and TRD_1 becomes H, the value of the timer counter 11 is fetched. That is, FIG.
In the case of (a), at t0, TRD_2 is H and TRD_1 is L
From the H level from the logic gate 36 and the negative logic (L) of the H level of CLK, the logic gate 37 reads the value of the timer counter 11 by the L level negative logic (H) of the AND logic. It is taken into the temporary register 13. Here, since the TCLK rises between the first half cycle and the second half cycle of the CLK rising edge timing (t0) when TRD_2 goes to the H level, the TCLK rising determination circuit 12 again at the next rising edge of the CLK (t1). TRD_1 becomes H, and TRD_2 becomes L
From the H from the logic gate 36 and the negative logic (L) of H of CLK, the logic gate 37 performs AND logic on L.
The value of the timer counter 11 is fetched again by negative logic (H). On the other hand, in the case of FIG.
As in the case of, TRD_2 is higher than H and TRD_1 is lower than L,
H from the logic gate 36 and the negative logic (L
), The logic gate 37 takes in the value of the timer counter 11 into the read-out temporary register 13 by negative logic (H) of L, which is an AND logic. However, unlike (a), there is no rise of TCLK between the first half cycle and the second half cycle of the CLK rising edge timing (t0) when TRD_2 goes to H, so that TCL at t1
While TRD_1 from the K rise determination circuit 12 remains L,
TRD_2 is also lower than L, and L from logic gate 36 and CL
From the negative logic (L) of K to the negative logic (L) of which the AND logic is obtained by the logic gate 37, the logic gate 37 remains at the H level, and the value of the timer counter 11 is not taken in again.

As described above, in the counter device with the output holding function according to the first embodiment, the value of the timer counter that operates on TCLK asynchronous with CLK is set to C when TRD_2 is valid.
At the rising edge of LK, the value is read into the read temporary register, and the presence or absence of a count operation is determined during a half cycle of CLK before and after this timing. When it is determined that the count operation is performed, the above value is read again after one cycle of CLK from the above timing. Since it is configured to take in the temporary register, TCLK is sampled directly with CLK, so that control becomes complicated, and a design that strictly analyzes variations in element characteristics and variations in wiring delays is required, which is very difficult to design. Can be avoided. Further, the value of the counter can be read stably without being adversely affected by interference between CLK and TCLK.

(Embodiment 2) FIG. 5 is a circuit diagram showing an example of a circuit of a clock control device according to Embodiment 2. As described above, the clock control device corresponds to the timer clock on / off circuit 14 in FIG. In FIG. 5, signals indicated by the same abbreviations as those in FIG. 2 are the same signals. Also, TCL
KO is the original TCLK which is supplied from the outside and controlled to be TCLK after being controlled. TON is an on / off signal of a timer clock synchronized with CLK for turning on / off TCLK by controlling TCLKO according to a command from a CPU or the like. Reference numeral 41 denotes a level-sensitive latch. The input D when the input G is at the L level appears on the output Q as it is, and holds the output Q when the input G is at the H level. A delay buffer 42 supplies TCLKO to the input G of the level-sensitive latch 41. 43
Is a logic gate, which supplies a signal based on AND logic of the output Q and TCLKO as TCLK to, for example, a timer counter of the interval timer device shown in FIG.

FIG. 6 is a diagram showing a timing chart in the clock control device of FIG. In FIG. 6, FIG.
The signals indicated by the same abbreviations are the same signals. Next, the operation of the clock control device according to the second embodiment will be described with reference to FIGS.
This will be described below.

First, in the case of FIG.
When the signal is at the level, the ON signal of the timer clock is input to the input D of the level sensitive latch 41 by the rise of TON. At this time, the input G of the level sensitive latch 41 is connected to the TCL passing through the delay buffer 42.
Since L of KO is input, the input D directly appears at the output Q, and the output Q remains at the H level. And TC
Even if LKO becomes H level, that is, the input G becomes H level, the H level of the output Q is maintained and TCLK is output from the logic gate 43 by AND logic with H of TCLKO. When TCLKO is at the L level, the falling edge of TON causes the timer clock off signal to be input to the input D.
, And the input G has a TC
When L of LKO is input, input D directly appears at output Q, and output Q is at L level. And TON and Q
When the level of TCLKO becomes H level, that is, the level of the input G also becomes H level, while the level of the input G also becomes H level, the L level of the output Q is maintained, the AND level cannot be obtained with the H level of TCLKO, and the logic gate 43 does not output TCLK.

Next, in the case of FIG. 6B, TCLKO becomes H
When the signal is at the level, the ON of the timer clock is input to the input D of the level-sensitive latch 41 by the rise of TON. At this time, the input G of the level-sensitive latch 41 is connected to the T
Since the H level of CLKO is input, the output Q maintains the state where the input D is at the L level, and the output Q remains at the L level. In this state, when TCLKO becomes L level, that is, when the input G becomes L level, the H level of the input D appears on the output Q as it is. At this time, the AND logic cannot be obtained between the H level of the output Q and the L level of the TCLKO, so that TCLK is not output. And then TCLK
When O becomes H level, input G becomes H level,
The logic gate 43 outputs TCLK by taking AND logic between the H level of the output Q and the H level of TCLKO. Further, when the timer clock OFF signal is input to the input D due to the fall of TON when TCLKO is at the H level, the input G is at the H level and the output Q is at the input D level.
Hold the H level state. Therefore, TCLKO
Logic gate 4 from the H level of output Q and the H level of output Q.
3 continues to output TCLK. And TCLKO
Is at the L level, that is, when the input G is at the L level, the L level of the input D appears at the output Q as it is, and TCLKO
, The TCLK is no longer output from the logic gate 43. As shown in the timing chart of FIG. 6, no whisker-like pulse appears on TCLK.

In FIG. 6, TON rises when TCLKO is at L level, TON falls when TCLKO is at L level (case (a)), and TC
When LKO is at H level, TON rises and TCLK
The case where TON falls when O is at the H level (case (b)) has been described separately. However, TON rises when TCLKO is at the L level, and TON falls when TCLKO is at the H level, and vice versa. In some cases, description will be made in the same manner as in the above cases (a) and (b).

As described above, in the clock control device according to the second embodiment, when the input of TCLKO is at the L level, the input of TON is output as it is, and when the input of TCLKO is at the H level, the level-sensitive latch for holding the output and the TCLKO Is provided to the level-sensitive latch, and a logic gate that sets the signal based on the AND logic between TCLKO and the output of the level-sensitive latch to TCLK is provided. When switching the TCLK by the control signal, it is possible not only to guarantee the pulse width of the TCLK, but also to avoid the disadvantage that one pulse of the TCLK is supplied after the TON signal becomes L level.
If this clock control device is used as an interval timer device, after the interval timer is turned off by a user program, the timer counter advances one count later and no interrupt signal is generated, so that the interval timer can be turned off. In this case, the timer clock is always turned off, and the user program and the hardware can be synchronized.

(Embodiment 3) FIG. 7 is a circuit diagram showing an example of a circuit of a counter device for controlling start or stop of a count operation according to Embodiment 3. In FIG. 7, FIG.
5 and FIG. 6 are the same or corresponding parts, and the signals indicated by the same abbreviations are the same signals. TWT is a write signal and is synchronized with CLK. TWT_TCLK is a write access signal,
In synchronization with TCLK, the value of the write temporary register WDT_TC
LK [n−1: 0] is a control signal for taking in the timer counter 11. 15 is a write synchronization circuit, and TO
This circuit generates TWT_TCLK when N is H. Reference numeral 16 denotes a write temporary register, which receives TWT when TON is H, and takes in write data WDT [n-1: 0] to the timer counter output from the CPU or the like.
63 is a write circuit, and when TCLK is not supplied,
WDT [n-1: 0] is written to the timer counter 11 through the write circuit. The specific circuit example will be described later. Reference numeral 64 denotes a flip-flop, which is an asynchronous set /
A down counter is provided with a reset terminal. 65
Is a selector, and W depends on the presence or absence of TWT_TCLK.
DT_TCLK [n-1: 0] or CNT [n-
1: 0] is subtracted by 1. Here, the timer counter 11 shown in the third embodiment not only counts down at the rising edge of TCLK as in the first embodiment but also has a flip-flop 64 having an asynchronous set / reset terminal to constitute a down counter. And a write circuit 63 for setting data even when TCLK is not supplied.

FIG. 8 is a diagram showing a timing chart in the counter device of FIG. Next, the operation of the counter device according to the third embodiment will be described. First, the TON shown in FIG.
= H, that is, when TCLK is supplied,
The write temporary register 16 stores TWT = H synchronized with CLK.
Receiving data WDT [n-
1: 0]. At this time, the write synchronization circuit 15
TWT_TCLK = H is output for one cycle of TCLK from the next rise of TCLK. Here, since TCLK is supplied to the timer counter 11,
The clock input terminal of the flip-flop 64 has TCLK
Is always supplied. Therefore, TWT_TCLK
= H, that is, when there is a write access signal from the CPU, WDT_TCLK [n-1: 0] is selected by the selector 65 in synchronization with TCLK, and TC
Write data from the CPU is written to the flip-flop 64 at the next rise of TCLK in synchronization with LK. As a result, data is written to the write temporary register 16 at a timing synchronized with CLK, and after its value is sufficiently stabilized, writing to the timer counter can be stably performed at a timing synchronized with TCLK. In this case, as shown in FIG. 8A, the frequency f (T
Although the case where the frequency f (CLK) of CLK)> CLK has been described, the same applies to the case where f (TCLK) <f (CLK). Next, TWT_
When TCLK is L, that is, when there is no write access signal from the CPU, the selector 65 selects a value obtained by subtracting 1 from the timer counter value CNT [n−1: 0], and writes the value to the flip-flop 64 in synchronization with TCLK. Is performed, and a countdown operation is performed (f
(CLK) = 0).

On the other hand, when TON in FIG.
CLK is not supplied (f (TCLK) =
0), since no clock is supplied to the flip-flop 64, the write data WDT [n-1:
0] to the timer counter 11, the writing circuit 6
3, data is supplied from the set terminal S and the reset terminal R of the flip-flop 64. Here, a specific circuit example of the write circuit 63 is shown in FIG.
The case where N = L will be described. TON = L, TWT
= H, the output of the gate 81 becomes H. That is,
When a write signal is output from the CPU with the timer turned off, the output of the gate 81 becomes H. When the output of the gate 81 is H, and when the k-th bit WDT [k] of the write data from the CPU is H, the output of the gate 83 becomes L in the section where CLK is L, and the timer counter 11 shown in FIG. Is supplied to the set terminal S of the flip-flop 64, and the value of the k-th bit of the timer counter 11 is set to 1. When the output of the gate 81 is H
, The k-th bit W of the write data from the CPU
When DT [k] is L, gate 82
Is supplied to the reset terminal R of the flip-flop 64 constituting the timer counter 11 in FIG. 7, and the value of the k-th bit of the timer counter 11 is set to 0.

As described above, in the counter device according to the third embodiment of the present invention, ON / OFF of the timer counter operation is determined by TC
When the timer counter is off, external input data is set from the asynchronous preset terminal of the flip-flop element constituting the timer counter. When the timer counter is on, the external input data is set in the write temporary register. A control signal for writing the data and writing the value of the write temporary register to the counter at the timing of the first timer counter value update after the written data is stabilized, and furthermore, the control signal while the timer counter is on. Is no longer generated, the data already written in the flip-flop element is decremented by one and counted, so that f (TCLK) = 0, f (TCLK)
(TCLK) <f (CLK), f (TCLK)> f (C
LK), data can be correctly written from the CPU to the timer counter, and f (CL
K) = 0, f (CLK)> f (TCLK), f (CL
K) <f (TCLK), it is possible to write a 1-subtracted value to the timer counter. That is, not only does TCLK turn on or off,
Even when CLK is not supplied, stable data can be written to the timer counter through ON / OFF of the timer counter operation. The clock wiring is TCLK and C
Since the LKs are clearly separated, the clock wiring design is easy. Furthermore, only the timer clock on / off circuit is added to the gate of the clock circuit. By providing the timer clock on / off circuit, which can be realized with a very simple configuration as described in the second embodiment, the timer operation is turned on. A circuit that can write stable data to the timer counter through the OFF state can be easily realized without generating clock skew or generating a whisker-like pulse in the clock.

Next, the overall operation of the interval timer device (FIG. 1) according to the first embodiment constituted by the devices according to the first to third embodiments will be described. First, based on a timer on / off signal TON from the CPU, TCLKO supplied from the outside is controlled on / off by a timer clock on / off circuit 14, and then supplied as TCLK to each section in the interval timer device. TC to which the TCLK is supplied
The LK rising determination circuit 12 determines whether or not TCLK has risen between the first half cycle and the second half cycle of the rising edge of CLK when the counter read advance signal TRD_2 is valid. TCLK in system clock cycle
A rise determination signal TRD_1 is issued. When TRD_2 is H or TRD_1 is H, the read temporary register 13 writes the data CNT [n-1: 0] of the timer counter 11 at the rising edge of CLK, and reads the timer counter value read data RDT [n -1:
0] to transfer the data to the CPU. When TON = H and TWT = H, that is, when the interval timer is on and there is a write access from the CPU, the write temporary register 16 stores the write data from the CPU to the timer counter at a timing synchronized with CLK. WDT [n-1: 0] is written. At this time, in the write synchronization circuit 15, the period TWT of one cycle of TCLK
_TCLK = H is output. When TON = H and TWT_TCLK = H, the timer counter 151 has WDT_TCLK [n−1: 0] in synchronization with TCLK.
Is written. On the other hand, when TON = L and TWT = H, that is, when the interval timer is off and there is a write access from the CPU, the write circuit in the timer counter 11 directly writes WDT [n−
1: 0].

As described above, the interval timer device according to the first embodiment of the present invention has a configuration including the devices according to the first to third embodiments. Therefore, in the timer counter that counts TCLK that is asynchronous with CLK, TCLK is used. CL
The timer counter can be stably read and written without being sampled at K and synchronized with CLK, and can be easily designed.

Embodiment 2 FIG. 10 is a block diagram showing an example of a configuration of an interval timer device according to Embodiment 2 of the present invention. 10, the same reference numerals as those in FIG. 1 denote the same or corresponding parts, and the signals indicated by the same abbreviations are the same signals. Reference numeral 94 denotes a read / write temporary register, which has the functions of the read temporary register 13 and the write temporary register 16 in FIG.

FIG. 11 shows a specific example of the internal configuration of the read / write temporary register 94. In the figure, reference numeral 95 denotes a selector for selecting write data. A flip-flop 96 writes the data selected by the selector 95.

Next, the operation of the read / write temporary register 94 will be described. When the write signal TWT = H from the CPU, the CPU selects write data WDT [n-1: 0] to the timer counter, Otherwise, the data C of the timer counter 11 (see FIG. 10)
NT [n-1: 0] is selected. When writing data from the CPU to the timer counter, the CPU receives a write signal TWT = H from the CPU, and receives data WDT [n−1: 0] from the CPU at the input terminal D of the flip-flop 96 constituting a read / write temporary register. At the same time, CLK is supplied to the flip-flop 96 through the gates 98 and 99, and the write data WDT [n-1:
0] is written, the read / write temporary register 94 operates as a write temporary register. On the other hand, CP
When the timer counter data is read out to U, the counter readout advance signal TRD_2 = H or T
The gate 97 and the gate 9 receive the TCLK rising determination signal TRD_1 = H from the CLK rising determining circuit.
8. CLK is applied to the flip-flop 96 through the gate 99.
Is supplied. On the other hand, when data is read from the CPU to the timer counter, the data is not written from the CPU to the timer counter.
Therefore, the timer counter data CNT [n−1: 0] is input to the input terminal D of the flip-flop 96, and the read / write temporary register 94 operates as a read temporary register.

In the interval timer device according to the second embodiment, reading and writing are performed simultaneously by using one of the reading and writing temporary registers as the function of the reading and writing temporary registers. However, there is no problem since the reading and writing of the timer counter is generally infrequent.

As described above, in the interval timer device according to the second embodiment of the present invention, in the interval timer device according to the first embodiment, these interval timer devices are replaced by the read temporary register and the write temporary register. Readout that combines the functions of
Since the configuration includes the write temporary register, even when the read / write temporary register functions as either the read temporary register or the write temporary register, it operates with the system clock. Also, the clock wiring does not become complicated, and only one register for synchronizing the system clock and the timer clock necessary for reading and writing of the timer counter is required, and the circuit scale can be reduced. is there.

Although the first and second embodiments have been described on the assumption that the timer counter is a down counter, the timer counter may be an up counter. In addition, the valid edges of the system clock and the timer clock have been described as rising edges.
Alternatively, it is possible to obtain the same effect as in the first and second embodiments even when falling.

[0047]

As described above, according to the counter device with an output holding function according to the present invention (claim 1),
In a counter device for sampling a timer clock asynchronous with a system clock with a system clock, a counter for counting by inputting the timer clock, and a reading device for taking in and holding a value of the counter at a first timing synchronized with the system clock Temporary storage means; and means for determining whether or not there is a second timing at which the counter updates the counter value with the timer clock in the system clock half cycle section before and after the first timing, respectively. Since the read temporary storage means takes in and holds the value of the counter again at the time of the second timing in the section, the timer clock is directly sampled by the system clock, so that the control becomes complicated. If the device characteristics Design strictly analyze variations in regard and wiring delay is required, there is an effect that it is possible to avoid problems such as the design becomes very difficult. Further, there is an effect that the value of the counter can be read stably without being adversely affected by the interference between the system clock and the timer clock.

Further, according to the counter device with output holding function according to the present invention (claim 2), in the counter device with output holding function according to claim 1, the read temporary storage means includes the second temporary storage device in the section. In this case, after one cycle of the system clock from the first timing, the value of the counter is fetched and held again, so that each unit always operates in units of one cycle of the system clock. Thus, there is an effect that a stable circuit can be easily realized.

According to the clock control device of the present invention (claim 3), in the clock control device for controlling the passage / non-passage of the timer clock by inputting a control signal synchronized with the system clock, A delay means for delaying a clock for a predetermined time, a timer clock delayed by the delay means and the control signal are input, and when the timer clock is at a low level, the control signal is output as it is, and the timer clock is at a high level. At this time, storage means for holding and outputting a control signal input when the signal changes to the high level, and gate means for outputting a high level when the output from the timer clock and the storage means are at a high level. With this configuration, it can be realized with a very simple configuration, and can be implemented with a control signal synchronized with the system clock. When switching the printer clock, not only to ensure the pulse width of the counter clock, outputs the control signal to turn off the counter clock is effective which can ensure that the counter clock is not output.

According to the counter device of the present invention (claim 4), there is provided a counter device for controlling the start or stop of the count operation by passing or not passing a timer clock asynchronous with the system clock. A clock control means for controlling passage / non-passage of the timer clock in response to a control signal controlled by a clock, a flip-flop element having an asynchronous preset terminal, and a timer clock transmitted from the clock control means to the flip-flop element Means for inputting the external input data from the asynchronous preset terminal when the timer clock is not supplied. When the timer clock is supplied, the timer clock is input to the flip-flop element to perform counting. Counter and clock control means Writing temporary storage means for temporarily storing the external input data and outputting the data to the counter when the timer clock is passed; and a first timer counter after the data written in the writing temporary storage means is stabilized. Signal generating means for generating a control signal for writing the value of the data to the counter at the time of updating the value, so that the timer counter operation is turned on and off regardless of whether the timer clock is on or off. Thus, there is an effect that stable data can be written to the timer counter. In addition, there is an effect that clock wiring design becomes easy.

Further, according to the counter device according to the present invention (claim 5), in the counter device according to claim 4, the counter generates the signal while keeping the clock control means passing the timer clock. When the signal from the means disappears, the flip-flop element counts by subtracting 1 from the value of the data input before the signal disappears under the control of the timer clock. Further, there is an effect that stable data can be written to the timer counter through the ON / OFF operation of the timer counter even when the system clock is not supplied, regardless of whether the timer clock is ON / OFF.

According to the counter device of the present invention (claim 6), in the counter device of claim 4 or 5, the clock control means is the clock control device of claim 3. Furthermore, there is an effect that a circuit capable of writing stable data to the timer counter through ON / OFF of the timer operation can be easily realized without generating clock skew or generating a whisker-like pulse in the clock.

Further, according to the interval device of the present invention (claim 7), there is provided an interval timer device having a counter device that operates with a timer clock that is asynchronous with a system clock. And a counter device having an output holding function, and a timer device that counts a timer clock that is asynchronous with the system clock. In the timer counter, the timer clock is sampled by the system clock and synchronized with the system clock. Even without,
The timer counter can be read and written stably, and the design can be made easily.

According to the interval device of the present invention (claim 8), in the interval timer device according to claim 7, the reading temporary storage means of the counter device with the output holding function and the writing of the counter device. In place of the temporary storage means, one storage means for switching to either read storage or write storage for storage is provided, so that the read / write temporary register is used for the read temporary storage means and the write temporary storage means. Even if both functions are provided, the clock wiring does not become complicated, and only one storage unit for synchronizing the system clock and the timer clock necessary for reading and writing of the timer counter can be used. This has the effect of reducing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an interval timer device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a counter device with an output holding function according to the first embodiment.

3 is a diagram showing a timing chart in the counter device with an output holding function of FIG. 2;

FIG. 4 is a circuit diagram showing an example of a circuit of the counter device with an output holding function of FIG. 2;

FIG. 5 is a circuit diagram illustrating an example of a circuit of a clock control device according to a second embodiment.

6 is a diagram showing a timing chart in the clock control device of FIG. 5;

FIG. 7 is a circuit diagram illustrating an example of a circuit of a counter device that controls start or stop of a count operation according to a third embodiment.

8 is a diagram showing a timing chart in the counter device of FIG. 7;

FIG. 9 is a circuit diagram showing a specific example of the write circuit shown in FIG. 7;

FIG. 10 is a block diagram showing a configuration of an interval timer device according to a second embodiment of the present invention.

FIG. 11 is a circuit diagram showing a specific example of a read / write temporary register shown in FIG. 11;

FIG. 12 is a circuit diagram showing an example of a circuit of a conventional counter device.

FIG. 13 is a timing chart showing an operation in the circuit shown in FIG. 12;

FIG. 14 is a circuit diagram showing another example of the circuit of the conventional counter device.

FIG. 15 is a circuit diagram showing an example of a circuit of a conventional counter device with an output holding function.

16 is a timing chart showing an example of the operation of the circuit shown in FIG.

17 is a timing chart showing another example of the operation of the counter device of FIG.

FIG. 18 is a circuit diagram showing an example of a circuit of a conventional clock control device.

FIG. 19 is a timing chart showing an operation in the circuit shown in FIG. 18;

[Explanation of symbols]

11 Timer Counter 12 TCLK Rising Judgment Circuit 13 Read Temporary Register 14 Timer Clock On / Off Circuit 15 Write Synchronous Circuit 16 Write Temporary Register 31, 32, 34, 38 Flip-Flop 33, 35, 36, 37 Gate 41 Level Sensitive Latch 42 Delay Buffer 43 gate 63 write circuit 64 flip-flop with asynchronous set / reset terminal 65 selector 81, 82, 83 gate 94 read / write temporary register 95 flip-flop 96 selector 97-99 gate 161, 181 selector

Claims (8)

[Claims] 1. A counter device for sampling a timer clock asynchronous with a system clock by a system clock, wherein the counter counts by inputting the timer clock, and a value of the counter at a first timing synchronized with the system clock. A temporary storage means for taking in and holding, and a means for determining whether or not there is a second timing at which the counter updates the counter value by the timer clock in a half cycle of the system clock before and after the first timing. A counter device with an output holding function, wherein the reading temporary storage means takes in and holds the value of the counter again when the second timing occurs in the section. 2. The counter device with an output holding function according to claim 1, wherein said read temporary storage means, when said second timing occurs in said section, after one system clock cycle from said first timing. And a counter device with an output holding function, which fetches and holds the value of the counter again. 3. A clock control device for inputting a control signal synchronized with a system clock to control the passage / non-passage of a timer clock, wherein the delay unit delays the timer clock for a predetermined time; When the timer clock is at a low level, the control signal is output as it is, and when the timer clock is at a high level, the control signal input when the timer clock changes to the high level is input. A clock control device comprising: storage means for holding and outputting; and gate means for outputting a high level when the timer clock and the output from the storage means are at a high level. 4. A counter device for controlling start or stop of a count operation by passing or non-passing of a timer clock asynchronous with a system clock, wherein the counter device receives a control signal controlled by the system clock,
Clock control means for controlling the passage / non-passage of the timer clock; a flip-flop element having an asynchronous preset terminal; and when the timer clock is not supplied from the clock control means to the flip-flop element, the external input data is supplied to the flip-flop element. A counter for inputting from the asynchronous preset terminal, wherein the timer clock is supplied to the flip-flop element to count when the timer clock is supplied; and Writing temporary storage means for temporarily storing the external input data and outputting the data to the counter, and updating the first timer counter value after the data written in the writing temporary storage means is stabilized. Write the value of the data to the counter at the timing of Counter device characterized by comprising a signal generating means for generating a control signal for fit. 5. The counter device according to claim 4, wherein the counter controls the flip-flop element when the signal from the signal generation unit is lost while the clock control unit keeps passing the timer clock. By controlling with the timer clock, by subtracting 1 from the value of the input data before the signal disappears,
A counter device for performing counting. 6. The counter device according to claim 4, wherein said clock control means is the clock control device according to claim 3. 7. An interval timer device having a counter device that operates with a timer clock that is asynchronous with a system clock, wherein the counter device has the output holding function according to claim 1 and the counter device according to claim 4. An interval timer device comprising: 8. The interval timer device according to claim 7, wherein the read temporary storage means of the counter device with the output holding function and the write temporary storage device of the counter device are replaced with either read storage or write storage. An interval timer device comprising one storage means for switching and storing the information.