JPH11214723A - Manufacture of solar battery element - Google Patents

Manufacture of solar battery element

Info

Publication number
JPH11214723A
JPH11214723A JP10017088A JP1708898A JPH11214723A JP H11214723 A JPH11214723 A JP H11214723A JP 10017088 A JP10017088 A JP 10017088A JP 1708898 A JP1708898 A JP 1708898A JP H11214723 A JPH11214723 A JP H11214723A
Authority
JP
Japan
Prior art keywords
layer
electrode
solar cell
glass layer
surface electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10017088A
Other languages
Japanese (ja)
Inventor
Shuichi Fujii
修一 藤井
Kenji Fukui
健次 福井
Katsuhiko Shirasawa
勝彦 白沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP10017088A priority Critical patent/JPH11214723A/en
Publication of JPH11214723A publication Critical patent/JPH11214723A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

PROBLEM TO BE SOLVED: To form a surface electrode, without destroying an N-layer by applying an electrode material and baking it by means of leaving a phosphorous glass layer, generated at the time of forming the N-layer on one main face side of a silicon substrate. SOLUTION: A P-type polycrystalline silicon wafer 1 is arranged in a diffusion furnace and is heated in phosphorus oxychloride(POCl3 ). An N-layer 2 is formed, and a P-N junction 3 is formed. A phosphorus glass layer 4 is formed on the outer surface of the wafer 1 through thermal diffusion. A resist 7 is applied to a region where the surface electrode of the wafer 1 is formed and it is immersed in an aqueous HF solution. Then, the phosphorus layer 4 remaining on the surface of the N-layer 2 is removed. The region where the surface electrode is formed is not removed. An electrode material is printed/ applied to the remained phosphorus glass layer 4, is baked at a temperature of 700 deg.C, so that a surface electrode 8 is formed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は太陽電池素子の製造
方法に関し、特にシリコン基板内にP−N接合部を有す
る太陽電池素子の製造方法に関する。
The present invention relates to a method for manufacturing a solar cell element, and more particularly to a method for manufacturing a solar cell element having a PN junction in a silicon substrate.

【0002】[0002]

【従来の技術および発明が解決しようとする課題】シリ
コン基板を用いて形成される太陽電池素子は、第2図に
示すように、シリコンウェハー21に内部電場を形成す
るためのP−N接合部22と、入射した光によって発生
した少数荷電担体を集める表面電極23と裏面電極24
とから構成されている。さらに、必要に応じてシリコン
ウェハー21の受光面に反射防止膜25が形成される。
2. Description of the Related Art As shown in FIG. 2, a solar cell element formed by using a silicon substrate has a PN junction for forming an internal electric field in a silicon wafer 21. 22, a front electrode 23 and a back electrode 24 for collecting minority charge carriers generated by incident light.
It is composed of Further, an anti-reflection film 25 is formed on the light receiving surface of the silicon wafer 21 as needed.

【0003】このような太陽電池素子においては、短波
長側の分光感度を向上させて高い光電変換特性を得るた
めに、第3図に示すように、P−N接合部22を浅く形
成して表面電極23とシリコンウェハー21のN層21
aが接合する領域にN型ドープ剤であるリンなどが高濃
度となるN+ 領域21a′を形成することが知られてい
る。
In such a solar cell element, in order to improve the spectral sensitivity on the short wavelength side and obtain high photoelectric conversion characteristics, the PN junction 22 is formed shallowly as shown in FIG. Surface electrode 23 and N layer 21 of silicon wafer 21
It is known that an N + region 21 a ′ having a high concentration of an N-type dopant such as phosphorus is formed in a region where a is joined.

【0004】即ち、N層21a中に低濃度ドープ領域2
1aと高濃度ドープ領域21a′とが結合するH/L
(ハイロー)接合である。このH/L接合は、少数荷電
担体の寿命を向上させるために、光が照射されるN層領
域21aを適当な抵抗値に設定し、かつ短波長側の分光
感度を向上させるために、P−N接合部22を浅く形成
するとともに、電極23と接合するN+ 領域21a′を
低抵抗値に設定して電極23とシリコンウェハー21と
のオーミックコンタクトを達成することで高い光電変換
効率を得るものである。
That is, the lightly doped region 2 is formed in the N layer 21a.
H / L where 1a is coupled to heavily doped region 21a '
(High-low) joining. This H / L junction is used to set the N-layer region 21a to be irradiated with light to an appropriate resistance value in order to improve the life of the minority charge carriers, and to improve the spectral sensitivity on the short wavelength side. A high photoelectric conversion efficiency is obtained by forming a shallow -N junction portion 22 and setting an N + region 21a 'to be joined to the electrode 23 to a low resistance value to achieve ohmic contact between the electrode 23 and the silicon wafer 21. Things.

【0005】上述のH/L接合したN層21aを有する
太陽電池素子を生産性よく製造する方法としては、特開
昭59−79580号公報に開示されている方法があ
る。これはP−N接合部22を形成する際に、シリコン
ウェハー21の外表面に形成される燐ガラス層26を再
利用するものである。
As a method for manufacturing a solar cell element having the above-described H / L bonded N layer 21a with high productivity, there is a method disclosed in Japanese Patent Application Laid-Open No. 59-79580. This is to reuse the phosphorus glass layer 26 formed on the outer surface of the silicon wafer 21 when forming the PN junction 22.

【0006】つまり、オキシ塩化リン(POCl3 )を
用いてリン原子を拡散することによって、P型シリコン
ウェハー21にN層21aを形成するとき、シリコンウ
ェハー21の外表面にリン原子を含むガラス層26が形
成される(図4(a))。この燐ガラス層26をレジス
ト膜と所定のエッチング液を用いて表面電極23が被着
される部分のみを残して900℃程度で加熱処理を行う
(図4(b))。これにより残存する燐ガラス層26の
リン原子がN層21a中に再拡散され、N+領域21
a′が形成される(図4(c))。その後、燐ガラス層
26及びシリコンウェハー21の側面及び裏面の不要な
N層21aを除去して(図4(d))、反射防止膜4、
表面電極2、及び裏面電極3を形成する(図2)。
That is, when an N layer 21a is formed on a P-type silicon wafer 21 by diffusing phosphorus atoms using phosphorus oxychloride (POCl 3 ), a glass layer containing phosphorus atoms is formed on the outer surface of the silicon wafer 21. 26 are formed (FIG. 4A). The phosphor glass layer 26 is subjected to a heat treatment at about 900 ° C. using a resist film and a predetermined etching solution except for a portion where the surface electrode 23 is to be deposited (FIG. 4B). As a result, the remaining phosphorus atoms of the phosphorus glass layer 26 are re-diffused into the N layer 21a, and the N + region 21
a 'is formed (FIG. 4C). Thereafter, the unnecessary N layer 21a on the side and the back of the phosphor glass layer 26 and the silicon wafer 21 is removed (FIG. 4D), and the anti-reflection film 4,
The front electrode 2 and the back electrode 3 are formed (FIG. 2).

【0007】しかし乍ら、かかる製造方法では、燐ガラ
ス層26をパターニングしてN+ 領域21a′を高温工
程で形成し、燐ガラス層26を除去した後に、さらにこ
のN+ 領域21a′上に電極材料を塗布して焼き付ける
ことによって表面電極23(図3参照)を形成しなけれ
ばならないことから、900℃程度の極めて高温工程が
必要で製造工程が煩雑であるとともに、製造が極めて困
難であるという問題があった。
However, in this manufacturing method, the N + region 21a 'is formed by patterning the phosphor glass layer 26 in a high-temperature step, and after removing the phosphor glass layer 26, the N + region 21a' is further formed on the N + region 21a '. Since the surface electrode 23 (see FIG. 3) must be formed by applying and baking an electrode material, an extremely high-temperature process of about 900 ° C. is required, the manufacturing process is complicated, and the manufacturing is extremely difficult. There was a problem.

【0008】このような問題を解決するために、N層2
1aのシート抵抗を例えば40Ω/□程度に下げて、こ
のN層21aに直接表面電極23を形成することも考え
られるが、N層21aのシート抵抗を下げると、発電す
る電流値も下がり、変換効率が低下するという問題を誘
発する。
In order to solve such a problem, the N layer 2
It is conceivable that the surface electrode 23 is formed directly on the N layer 21a by lowering the sheet resistance of the N layer 21a to, for example, about 40 Ω / □. Induces a problem of reduced efficiency.

【0009】さらに、N層21aのシート抵抗を例えば
60Ω/□程度に上げて、このN層21aに直接表面電
極23を形成すると、表面電極23を形成する際に、電
極材料のペースト中のガラスフリットなどがN層21a
を突き抜けてP層21bまで到達し、太陽電池素子を形
成した場合に、リーク電流が増大して出力特性が低下す
るという問題があった。特に、電流値を向上させるため
に、シート抵抗を大きくしようとすると、N層21aは
浅く形成せざるを得ず、電極材料を焼き付ける際に電極
材料中のガラスフリットがN層21aを突き抜ける可能
性は大きくなる。
Further, if the surface resistance 23 is formed directly on the N layer 21a by increasing the sheet resistance of the N layer 21a to, for example, about 60 Ω / □, the glass in the electrode material paste is formed when the surface electrode 23 is formed. Frit etc. are N layer 21a
When the solar cell element is formed by piercing through to the P layer 21b and forming the solar cell element, there is a problem that the leak current increases and the output characteristics deteriorate. In particular, if the sheet resistance is to be increased in order to improve the current value, the N layer 21a must be formed shallow, and the glass frit in the electrode material may penetrate the N layer 21a when firing the electrode material. Becomes larger.

【0010】本発明はこのような従来方法の問題点に鑑
みてなされたものであり、N層が比較的高抵抗でも、こ
のN層上にこのN層を破壊することなく電極を形成する
ことができる太陽電池素子の製造方法を提供することを
目的とする。
The present invention has been made in view of the problems of the conventional method, and an electrode is formed on the N layer without destroying the N layer even if the N layer has a relatively high resistance. It is an object of the present invention to provide a method for manufacturing a solar cell element that can be used.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するため
に、本発明に係る太陽電池素子の製造方法では、P型シ
リコン基板の一主面側にN層と表面電極を形成すると共
に、他の主面側に裏面電極を形成する太陽電池素子の製
造方法において、前記シリコン基板の一主面側にN層を
形成する際に生成する燐ガラス層を残したまま電極材料
を塗布して焼き付けることによって前記表面電極を形成
することを特徴とする。
In order to achieve the above object, in a method for manufacturing a solar cell element according to the present invention, an N layer and a surface electrode are formed on one principal surface of a P-type silicon substrate, In a method for manufacturing a solar cell element in which a back electrode is formed on the main surface of the silicon substrate, an electrode material is applied and baked while leaving a phosphor glass layer generated when an N layer is formed on one main surface of the silicon substrate. Thus, the surface electrode is formed.

【0012】また、本発明に係る太陽電池素子の製造方
法では、前記シリコン基板の一主面側にN層を形成する
際に生成する燐ガラス層のうち、前記表面電極を形成す
る領域だけ残して、この燐ガラス層上に前記電極材料を
塗布して焼き付けることによって前記表面電極を形成す
ることが望ましい。
Further, in the method for manufacturing a solar cell element according to the present invention, only a region where the surface electrode is to be formed is left in a phosphor glass layer formed when an N layer is formed on one main surface side of the silicon substrate. It is preferable that the surface electrode is formed by applying and baking the electrode material on the phosphor glass layer.

【0013】[0013]

【発明の実施の形態】以下、本発明を添付図面に基づい
て詳細に説明する。図1は本発明の太陽電池素子の製造
方法を示す工程図である。P型を呈する多結晶シリコン
ウェハー1を拡散炉中に配置して、オキシ塩化リン(P
OCl3 )中で加熱することによって、ウェハー1の表
面部分にリン原子を拡散させてN層2を形成し、P−N
接合部3を形成する。この熱拡散により、ウェハー1の
外表面にはリン原子を合む燐ガラス層4が形成される。
なお、5はシリコンウェハー中のP領域を示す(図1
(a))。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a process chart showing a method for manufacturing a solar cell element of the present invention. The P-type polycrystalline silicon wafer 1 is placed in a diffusion furnace, and the phosphorous oxychloride (P
By heating in OCl 3 ), phosphorus atoms are diffused into the surface portion of the wafer 1 to form an N layer 2, and PN
The joint 3 is formed. Due to this thermal diffusion, a phosphorus glass layer 4 containing phosphorus atoms is formed on the outer surface of the wafer 1.
Reference numeral 5 denotes a P region in the silicon wafer (FIG. 1)
(A)).

【0014】次に、シリコンウェハー1の一主面側にレ
ジスト膜6を塗布して弗酸(HF)と硝酸(N2O)を
主成分とするエッチング液に浸漬して、シリコンウェハ
ー1の側面部と他の主面側の燐ガラス層4およびN層2
を除去した後、シリコンウェハー1の一主面側のレジス
ト膜6を除去し、純水で洗浄する(図1(b)
(c))。
Next, a resist film 6 is applied to one main surface side of the silicon wafer 1 and immersed in an etching solution containing hydrofluoric acid (HF) and nitric acid (N 2 O) as main components to form a side surface of the silicon wafer 1. And the other main surface side phosphor glass layer 4 and N layer 2
Is removed, the resist film 6 on one main surface side of the silicon wafer 1 is removed, and the silicon wafer 1 is washed with pure water (FIG. 1B).
(C)).

【0015】次に、シリコンウェハー1の一主面側の表
面電極が形成される領域にレジスト膜7を塗布して、弗
酸(HF)の水溶液中に浸漬することによって、N層2
の表面部に残存する燐ガラス層4を除去する(図1
(d)(e))。なお、表面電極を形成する領域の燐ガ
ラス層4は除去しない。この場合、N層2は0.3μm
程度までの厚みに形成し、シート抵抗が60Ω/□以上
になるように形成する。
Next, a resist film 7 is applied to a region on one main surface of the silicon wafer 1 where a surface electrode is to be formed, and is dipped in an aqueous solution of hydrofluoric acid (HF) to form an N layer 2.
The phosphor glass layer 4 remaining on the surface of the substrate is removed (FIG. 1).
(D) (e)). The phosphor glass layer 4 in the region where the surface electrode is to be formed is not removed. In this case, the N layer 2 is 0.3 μm
It is formed so as to have a thickness up to the order, and the sheet resistance is 60 Ω / □ or more.

【0016】次に、残存した燐ガラス層4上に電極材料
をスクリーン印刷法などで印刷塗布して、700℃程度
の温度で焼き付けることによって、表面電極8を形成す
る(図1(f))。電極材料は銀粉末、ガラスフリッ
ト、バインダー、溶剤などを含有して構成される。この
ような電極材料を700℃程度の温度で焼き付けると、
電極材料中のバインダーと溶剤は揮発し、銀粉末とガラ
スフリットだけが電極として残る。また、電極材料は燐
ガラス層4上に塗布されることから、この電極材料が加
熱されても、電極材料中のガラスフリットは燐ガラスに
固着するだけで、シリコン基板1中に侵入することはな
い。したがって、電極材料中のガラスフリットでN層2
が破壊されることもない。
Next, an electrode material is printed and applied on the remaining phosphor glass layer 4 by a screen printing method or the like, and baked at a temperature of about 700 ° C. to form a surface electrode 8 (FIG. 1F). . The electrode material contains silver powder, glass frit, a binder, a solvent, and the like. When such an electrode material is baked at a temperature of about 700 ° C.,
The binder and the solvent in the electrode material volatilize, leaving only the silver powder and the glass frit as the electrode. Further, since the electrode material is applied on the phosphor glass layer 4, even if this electrode material is heated, the glass frit in the electrode material only adheres to the phosphor glass and does not enter the silicon substrate 1. Absent. Therefore, the N layer 2 is formed by the glass frit in the electrode material.
Is not destroyed.

【0017】次に、シリコンウェハー1の一主面側に反
射防止膜10を形成する(図1(g))。反射防止膜1
0はシランとアンモニアとの混合ガスをプラズマCVD
法を用いて形成する。表面電極パターン8部分の反射防
止膜10を除去して、純水で洗浄する(図1(g))。
Next, an antireflection film 10 is formed on one main surface side of the silicon wafer 1 (FIG. 1G). Anti-reflection film 1
0 is plasma CVD of mixed gas of silane and ammonia
It is formed using a method. The antireflection film 10 at the surface electrode pattern 8 is removed and washed with pure water (FIG. 1 (g)).

【0018】最後に、シリコンウェハーの他の主面側
に、アルミニウム(Al)ぺーストを印刷焼成して裏面
電極11を形成した後、半田デップ法により、表面電極
8と裏面電極11の表面を半田層12、13で被覆する
(図1(h))。
Finally, after printing and baking aluminum (Al) paste on the other main surface of the silicon wafer to form the back electrode 11, the surfaces of the front electrode 8 and the back electrode 11 are formed by a solder dipping method. Covering with solder layers 12 and 13 (FIG. 1 (h)).

【0019】尚、上述の実施例では電極3をAlぺース
トを用いて厚膜手法で形成したが、真空蒸着法、メッキ
法などの薄膜手法で形成してもよく、また反射肪止膜を
電極形成後に被着しても構わない。
In the above-described embodiment, the electrode 3 is formed by a thick film method using Al paste. However, the electrode 3 may be formed by a thin film method such as a vacuum evaporation method or a plating method. It may be applied after the electrodes are formed.

【0020】[0020]

【実施例】表面電極部分の燐ガラス層を残したまま、表
面電極を焼き付けた本発明の実施形態の方法による太陽
電池素子と、燐ガラス層を全て除去して表面電極を焼き
付けた従来の構造の太陽電池素子を形成して、それぞぞ
れの特性を測定した。なお、N層部分のシート抵抗は6
0Ω/□に設定したものである。その結果を表1に示
す。
EXAMPLE A solar cell element according to the method of the embodiment of the present invention in which the surface electrode was baked while the phosphor glass layer in the surface electrode portion was left, and a conventional structure in which the surface electrode was baked by removing all the phosphor glass layer. Was formed, and the characteristics of each were measured. The sheet resistance of the N layer portion is 6
It is set to 0Ω / □. Table 1 shows the results.

【0021】[0021]

【表1】 [Table 1]

【0022】表1から明らかなように、本発明方法によ
る太陽電池素子では、従来方法による太陽電池素子に比
較して、解放電圧(Voc)が52mV向上し、曲線因子
(F.F.)が0.226向上し、変換効率(Eff
i)が5.3%向上する。
As is clear from Table 1, in the solar cell device according to the method of the present invention, the open-circuit voltage (V oc ) is improved by 52 mV and the fill factor (FF) is increased as compared with the solar cell device according to the conventional method. Is improved by 0.226, and the conversion efficiency (Eff
i) is improved by 5.3%.

【0023】[0023]

【発明の効果】上述したように、本発明に係る太陽電池
素子の製造方法によれば、シリコン基板の一主面側にN
層を形成する際に生成する燐ガラス層を残したまま電極
材料を塗布して焼き付けることによって表面電極を形成
することから、N層を破壊することなく表面電極を形成
することができ、リーク電流が低減されて、曲線因子や
開放電圧が改善される太陽電池素子の製造方法を提供す
ることができる。
As described above, according to the method for manufacturing a solar cell element of the present invention, N
Since the surface electrode is formed by coating and baking the electrode material while leaving the phosphor glass layer generated when forming the layer, the surface electrode can be formed without breaking the N layer, and the leakage current can be reduced. Can be provided, and the fill factor and the open circuit voltage can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る太陽電池素子の製造方法の一実施
形態を示す工程図である。
FIG. 1 is a process chart showing one embodiment of a method for manufacturing a solar cell element according to the present invention.

【図2】従来の太陽電池素子を示す断面図である。FIG. 2 is a cross-sectional view showing a conventional solar cell element.

【図3】従来の太陽電池素子を示す部分拡大断面図であ
る。
FIG. 3 is a partially enlarged sectional view showing a conventional solar cell element.

【図4】従来の太陽電池素子の製造方法を示す工程図で
ある。
FIG. 4 is a process chart showing a conventional method for manufacturing a solar cell element.

【符号の説明】[Explanation of symbols]

1‥‥‥シリコンウェハー、2‥‥‥N層、3‥‥‥P
−N接合部、4‥‥‥燐ガラス層、5‥‥‥P領域、8
‥‥‥表面電極、9‥‥‥N+ 領域、10‥‥‥反射防
止膜、11‥‥‥裏面電極
1 ‥‥‥ silicon wafer, 2 ‥‥‥ N layer, 3 ‥‥‥ P
−N junction, 4 ° phosphor glass layer, 5 ° P region, 8
{Surface electrode, 9} N + region, 10} Anti-reflective coating, 11} Back electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 P型シリコン基板の一主面側にN層と表
面電極を形成すると共に、他の主面側に裏面電極を形成
する太陽電池素子の製造方法において、前記シリコン基
板の一主面側にN層を形成する際に生成する燐ガラス層
を残したまま電極材料を塗布して焼き付けることによっ
て前記表面電極を形成することを特徴とする太陽電池素
子の製造方法。
1. A method of manufacturing a solar cell element, comprising: forming an N layer and a surface electrode on one principal surface of a P-type silicon substrate; and forming a back electrode on another principal surface. A method for manufacturing a solar cell element, wherein the surface electrode is formed by applying and baking an electrode material while leaving a phosphor glass layer generated when an N layer is formed on a surface side.
【請求項2】 前記シリコン基板の一主面側にN層を形
成する際に生成する燐ガラス層のうち、前記表面電極を
形成する領域だけ残して、この燐ガラス層上に前記電極
材料を塗布して焼き付けることによって前記表面電極を
形成することを特徴とする請求項1に記載の太陽電池素
子の製造方法。
2. The method according to claim 1, wherein, of the phosphor glass layer formed when the N layer is formed on one main surface side of the silicon substrate, only the region for forming the surface electrode is left, and the electrode material is formed on the phosphor glass layer. The method according to claim 1, wherein the surface electrode is formed by applying and baking.
【請求項3】 前記シリコン基板の一主面側に形成され
るN層が60Ω/□以上のシート抵抗を有することを特
徴とする請求項1又は請求項2に記載の太陽電池素子の
製造方法。
3. The method for manufacturing a solar cell element according to claim 1, wherein the N layer formed on one main surface side of the silicon substrate has a sheet resistance of 60 Ω / □ or more. .
JP10017088A 1998-01-29 1998-01-29 Manufacture of solar battery element Pending JPH11214723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10017088A JPH11214723A (en) 1998-01-29 1998-01-29 Manufacture of solar battery element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10017088A JPH11214723A (en) 1998-01-29 1998-01-29 Manufacture of solar battery element

Publications (1)

Publication Number Publication Date
JPH11214723A true JPH11214723A (en) 1999-08-06

Family

ID=11934242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10017088A Pending JPH11214723A (en) 1998-01-29 1998-01-29 Manufacture of solar battery element

Country Status (1)

Country Link
JP (1) JPH11214723A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008109164A (en) * 2008-01-17 2008-05-08 Mitsubishi Electric Corp Solar cell, and solar cell module
CN102509746A (en) * 2011-11-03 2012-06-20 湖南红太阳新能源科技有限公司 Diffusion process for crystalline silicon solar cell
JP2014501456A (en) * 2010-12-29 2014-01-20 ジーティーエイティー・コーポレーション Method for forming a device by building a support element on a thin semiconductor film

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008109164A (en) * 2008-01-17 2008-05-08 Mitsubishi Electric Corp Solar cell, and solar cell module
JP4506838B2 (en) * 2008-01-17 2010-07-21 三菱電機株式会社 Solar cell and solar cell module
JP2014501456A (en) * 2010-12-29 2014-01-20 ジーティーエイティー・コーポレーション Method for forming a device by building a support element on a thin semiconductor film
CN102509746A (en) * 2011-11-03 2012-06-20 湖南红太阳新能源科技有限公司 Diffusion process for crystalline silicon solar cell

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