JPH11214399A - Bipolar semiconductor device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent differences in surface steps of an insulating film which coats a polycrystalline silicon film, without increasing the number of processes regarding structure, and to facilitate the control of selective polishing. SOLUTION: A bipolar semiconductor device is provided with a monocrystal silicon film 3, having an n<+> -type embedded collector layer 4, silicon oxide film 5 formed on the monocrystal silicon layer 3, p-type SiGe films (base regions) 12 and 13, P<++> -type polycrystalline silicon film (base leadout electrode) 6 formed on the silicon oxide film 5, and n<+> -type polycrystalline silicon film (emitter region) 16 separated via a silicon nitride film from the polycrystalline silicon film 6, and formed on a p-type SiGe film 12. Then, the silicon oxide film 5 and the polycrystalline silicon film 6 are coated with a borophosphosilicate glass(BPSG) film 8, and the surface of the BPSG film 8 is planarized by selective polishing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar semiconductor device and a method of manufacturing the same, and more particularly, to a SiGe device.
The present invention relates to a self-aligned bipolar semiconductor device using a base and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the spread of multimedia communication, mobile communication, and the like, demands for high-speed data processing in electronic devices such as data processing devices and communication devices have been increasing more and more than before. To cope with such a situation, it is necessary to further increase the speed of an electronic circuit used in the electronic device, and therefore, it is necessary to improve the high-frequency characteristics of a semiconductor device forming the electronic circuit. Is eagerly awaited. In order to meet this demand, a self-aligned bipolar transistor using a SiGe base has been conventionally proposed.

As a manufacturing technique of this type of bipolar transistor, a buried collector layer is formed by a high-energy ion implantation method, and a CMP (Chemical Mechanical Polishing) method is used.
(shing, chemical-mechanical polishing) method to flatten the surface by selective polishing to form an element isolation region, and furthermore, embed a contact hole for the emitter electrode and a contact hole for the collector electrode with a polycrystalline silicon film. It has been reported by T. Tashiro et al. (T. Tashiro et al., “7-Mask Self-
-Aligned SiGeBase Bipolar Transistors with fT of 8
0GHz "IEICE TRANS.ELECTRON., VOL.E80-C, NO.5 MAY 199
7, P.707-P.713).

A method of manufacturing a bipolar transistor by T. Tashiro et al. Will be described in detail. First, as shown in FIG.
SOI (Silicon-On-Insul) having a three-layer structure of an oxide film (insulating film) 12 m in thickness and a single crystal silicon film 3 having a thickness of about 1 μm
ator) A substrate is prepared, and an implantation energy of about 700 keV and a dose of about 5 are formed in the single crystal silicon film 3 of the SOI substrate.
An n ⁺ -type buried collector layer 4 is formed by implanting phosphorus at × 10 ¹⁴ cm ⁻² (FIG. 1B). Next, a silicon oxide (SiO ₂ ) film 80 having a thickness of about 40 nm is formed by thermally oxidizing the single crystal silicon film 3 (FIG. ₁ ).
(B)). Next, a photoresist mask is formed on the silicon oxide film 80 by a photolithography method, and the silicon oxide film 80, the single crystal silicon film 3, and the buried collector layer 4 in a portion to be an element isolation region are converted to the oxide film 2 Is removed by etching until the surface of the groove is exposed.
Is formed (FIG. 2C). Next, as shown in FIG. 9D, BPSG (Boro
-Phospho-Silicate-Glass) film 24 is deposited to a thickness of approximately 2 μm, and after filling the grooves 22, 22, the BPSG film 24 is reflowed by a heat treatment at about 950 ° C. Next, CMP
By selective polishing by the silicon oxide film 8
The BPSG film 24 is flattened until the surface of
Further, the silicon oxide film 8 is formed using an HF-based etchant.
0 is removed by etching (Fig. (E))

[0005] Next, CVD (Chemical Vapor D)
The silicon oxide film 82 has a thickness of 100
It is deposited to about nm (FIG. (F)). Next, FIG.
As shown in (G), a polycrystalline silicon (Poly-si) film is deposited to a thickness of about 200 nm, boron (B) is ion-implanted into the deposited polycrystalline silicon film, and the sheet resistance is 50Ω / □. the degree of P ⁺⁺ type polycrystalline silicon film 26, again, by photolithography, after forming a photoresist mask on the polycrystalline silicon film 26,
By performing anisotropic etching, a base lead electrode of the P ⁺⁺ type polycrystalline silicon film 26 is formed (FIG. 1H). Thereafter, a silicon nitride (Si ₃ N ₄ ) film 8 is formed on the entire surface where the polycrystalline silicon film 26 and the silicon oxide film 82 are exposed.
4 is formed to a thickness of about 150 nm (FIG. 1I). Next, the silicon nitride film 84 is formed by photolithography.
After forming a resist mask on the silicon nitride film 84 and the polycrystalline silicon film 26 as shown in FIG.
Is removed by anisotropic etching until the surface of the silicon oxide film 82 is exposed, and an emitter contact hole 28 is formed.

After that, the mask is removed and the silicon nitride film 30 is formed by LPCVD (Low Pressure Chemical Depositio).
Then, the silicon nitride film 30 is etched back (anisotropically etched) to a thickness of about 60 nm by the n) method, and only the side surfaces of the contact holes 28 are etched.
The silicon nitride film 30 is left (FIG. 3 (L)). Next, FIG.
As shown in (M), the silicon oxide film 82 exposed at the bottom of the contact hole 28 is immersed in an HF-based etchant and removed by wet etching. At this time, the lower surface of the polycrystalline silicon film 26 has a depth of 150 nm.
The lateral etching is performed until it is exposed to the extent. After completion of the lateral etching, the upper surface of the single crystal silicon film 3 exposed at the bottom of the contact hole 28 and the lower surface of the p ⁺⁺ -type polycrystalline silicon film 26 are respectively formed by p-type epitaxial growth method. Type single crystal SiGe film 3
2. A p-type polycrystalline SiGe film 34 is grown (FIG.
(N)). In this selective epitaxial growth, the p-type single-crystal SiGe film 32 forming the base region and the p-type polycrystalline Si
The process is performed until the Ge film 34 is connected.

Next, a silicon nitride film 36 is deposited to a thickness of about 50 nm by LPCVD on the entire surface of the silicon nitride film 84 in which the emitter contact hole 28 is formed (FIG. 2 (O)). After a photoresist mask is formed on the silicon nitride film by photolithography, as shown in FIG.
6. The silicon oxide film 84 and the single-crystal silicon film 3 are anisotropically etched until reaching the n ⁺ -type buried collector layer 4 to form a collector contact hole 38.

Next, in order to separate the emitter region and the base region, the mask is removed and the silicon nitride film 36 is etched back (anisotropically etched) to leave only the side wall of the emitter contact hole 28 (FIG. 1). (P)). continue,
An n ⁺ -type polycrystalline silicon film 40, which is a conductive film doped with phosphorus, is formed on the entire surface of the silicon nitride film 84 to a thickness of 500 nm.
After being deposited to about nm, etch back (anisotropic etching) is performed to leave the phosphorus-doped polycrystalline silicon film 40 only in the emitter contact hole 28 and the collector contact hole 38 (FIG. 1 (Q)). By filling the emitter contact hole 28 with the phosphorus-doped polycrystalline silicon film 40 in this manner, a P-type emitter region is formed. Next, a silicon oxide film 86 is deposited on the upper surface of the silicon nitride film 84 to a thickness of about 200 nm by a CVD method (FIG. 3 (R)). Further, after forming a mask on the silicon oxide film 86 by photolithography,
The silicon oxide film 86 and the silicon nitride film 84 are removed by anisotropic etching to form a base contact hole 42. Through this contact hole 42, a part of the surface of the p ⁺⁺ type boron (B) -doped polycrystalline silicon film 26 is exposed. Finally, a metal film mainly composed of aluminum is deposited on the silicon oxide film 86, a resist mask is formed on the deposited metal film by a photolithography method, and then selectively removed by etching to form a base electrode. 4
6, an emitter electrode 48 and a collector electrode 50 are formed (FIG. 1 (R)).

[0009]

However, the conventional method of manufacturing a self-aligned bipolar transistor has the following problems. That is, in the conventional structure of the self-aligned bipolar transistor, a surface step is formed in the upper silicon nitride film 84 along the side edge of the polycrystalline silicon film 26 functioning as a base extraction electrode, and thus the film is formed in a subsequent step. Even if the phosphorus-doped polycrystalline silicon film 40 is etched back (anisotropic etching),
The phosphorus-doped polycrystalline silicon film 40 remains on the above-mentioned step, and a short circuit state easily occurs between the collector and the base due to the residue. To prevent this, as described above, the base, emitter, and collector electrodes 46, 4
Before forming the layers 8 and 50, an extra silicon oxide film 86 (FIG. 9 (R)) must be formed on the silicon nitride film 84 covering the polycrystalline silicon film 26. A step of forming a photoresist mask on the deposited polycrystalline silicon film 26 by a photolithography method without being limited to the film forming step, and a step of forming a silicon oxide film 86
(FIG. 2 (S)) is also required.

Further, in the conventional manufacturing method, as described above, when forming a mask on the silicon oxide film 86 to form each electrode, the positioning with respect to the emitter electrode and the collector contact holes 28 and 38 is performed. Since a margin is required, miniaturization of the element is easily restricted. Furthermore, BPSG as an element isolation insulating film
There is also a problem that it is difficult to control selective polishing when flattening the surface of the film 24. That is, in FIG. 9E, if the amount of polishing by the selective polishing is insufficient, the BPSG film 24 remains on the silicon oxide film 80. Conversely, if the amount of polishing is large, the single crystal silicon film 3 is scraped. This is because it will be lost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and eliminates a surface step of an insulating film covering a polycrystalline silicon film without increasing the number of steps in structure. It is an object of the present invention to provide a bipolar semiconductor device that facilitates control and a method of manufacturing the same.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor layer having a buried layer of a first conductivity type forming a collector region on a substrate, and the semiconductor layer. A first insulating film formed on the first insulating film, a second conductive type first conductive film also formed on the semiconductor layer to form a base region, and a first insulating film formed on the first insulating film. And a second conductive type second conductive film connected to the first conductive film and forming a base lead electrode, separated from the second conductive film via a second insulating film, and A bipolar semiconductor device comprising a first conductive type third conductive film formed on the first conductive film and forming an emitter region, wherein the first insulating film and the second conductive film The conductive film is covered with a vitreous insulating film, and the surface of the vitreous insulating film is flat. It is characterized in.

According to a second aspect of the present invention, there is provided the bipolar semiconductor device according to the first aspect, wherein the vitreous insulating film also serves as an element isolation insulating film.

According to a third aspect of the present invention, there is provided the bipolar semiconductor device according to the first or second aspect, wherein the vitreous insulating film is a BPSG film or a PSG film.

According to a fourth aspect of the present invention, there is provided the bipolar semiconductor device according to the first, second or third aspect, wherein the second and third conductive films are made of a polycrystalline silicon film.

According to a fifth aspect of the present invention, there is provided the bipolar semiconductor device according to the first, second or third aspect, wherein the first conductive film is made of a SiGe film.

According to a sixth aspect of the invention, there is provided a method of manufacturing a bipolar semiconductor device, comprising: forming a semiconductor layer having a first conductivity type buried layer forming a collector region on a substrate; A second step of forming a first insulating film on the semiconductor layer, and a third step of forming a second conductive type second conductive film serving as a base lead electrode on the first insulating film. A step of covering the first insulating film and the second conductive film with a vitreous insulating film, and then planarizing the surface of the vitreous insulating film; The first conductive film of the second conductivity type forming the base region is formed on the second conductive type.
Forming an emitter region on the second conductive film while being separated from the first conductive film by a second insulating film; And a sixth step of forming a third conductive film of the first conductivity type.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a bipolar semiconductor device according to the sixth aspect, wherein in the fourth step, the surface of the vitreous insulating film is CM
The flattening process is performed using the P method.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using an embodiment. FIG. 1 is a sectional view showing the structure of a bipolar semiconductor device according to one embodiment of the present invention.
8 are cross-sectional views showing a method of manufacturing the same semiconductor device in the order of steps. As shown in FIG. 1, a semiconductor device of this example has a silicon substrate (supporting substrate) 1-oxide film (insulating film)
2-SOI substrate having a three-layer structure of single-crystal silicon film 3, n ⁺ -type buried collector layer 4 provided in single-crystal silicon film 3, and silicon oxide provided on single-crystal silicon film 3 A film 5, a P ⁺⁺ -type polycrystalline silicon film 6 provided on the silicon oxide film 5 and serving as a base lead electrode, a single-crystal silicon film 3 and a P ⁺⁺ -type polycrystalline silicon film 6. A p-type single-crystal SiGe film 12 and a polycrystalline SiGe film 13 forming a base region, and an n ⁺ -type polycrystalline silicon film 16 forming an emitter region by filling the emitter contact hole 10. A BPSG film 8 covering the P ⁺⁺ -type polycrystalline silicon film 6 and the silicon oxide film 5 and also serving as an element isolation insulating film;
The surface of the BPSG film 8 has been flattened.

Next, a method of manufacturing the semiconductor device having the above-described configuration will be described with reference to FIGS. First, FIG.
As shown in (A), an SOI substrate having a three-layer structure of a silicon substrate (supporting substrate) 1-an oxide film (insulating film) having a thickness of about 5 μm-a single crystal silicon film 3 having a thickness of about 1 μm is prepared The implantation energy is approximately 700 keV and the dose is approximately 5 × 10 ¹⁴ cm in the single crystal silicon film 3 of this SOI substrate.
^{At -2} , an n ⁺ -type buried collector layer 4 is formed by implanting phosphorus (FIG. 1B). Up to this point, it is substantially the same as the above-described conventional manufacturing method. Thereafter, a silicon oxide film 5 is formed on the single crystal silicon film 3 by a CVD method (FIG. 3C).

Next, as shown in FIG.
By a D method, a polycrystalline silicon film 6 is deposited on the silicon oxide film 5 to a thickness of about 300 nm, boron ions are implanted into the deposited polycrystalline silicon film, and P ⁺ having a sheet resistance of about 50Ω / □ is formed. ⁺ a polycrystalline silicon film 6 of the mold, further, by photolithography, after forming a resist mask on the polycrystalline silicon film 6, anisotropic etching is performed, P ⁺⁺ type polycrystalline silicon film 6 (FIG. 10E). Again, a photoresist mask is formed on the surface of the silicon oxide film 5 or the polycrystalline silicon film 6 by the photolithography method, and as shown in FIG. , Single crystal silicon film 3 and buried collector layer 4
Is removed by etching until the surface of the oxide film 2 is exposed, thereby forming grooves 7 and 7 (FIG. 4F). Then, FIG.
As shown in FIG. 2G, a BPSG film 8 is deposited on the entire surface as an element isolation insulating film to a thickness of about 2 μm, and after filling the grooves 7, 7, the BPSG film 8 is reflowed by a heat treatment at about 950 ° C. I do.

Next, the convex portions on the surface of the BPSG film 8 are flattened by selective polishing by the CMP method (FIG.
(H)). In the selective polishing of this example, the purpose is achieved by polishing only the convex portions (thickness: about 0.5 μm) having a high polishing rate. Therefore, the BPSG film must be polished to a thickness of about 2 μm to planarize. Compared to the conventional method
The polishing time can be greatly reduced.

Subsequently, a silicon nitride film 9 is deposited on the flattened BPSG film 8 to a thickness of about 100 nm by LPCVD (FIG. 1I). Next, after forming a mask on the silicon nitride film 9 by photolithography,
As shown in FIG. 5J, the silicon nitride film 9 and the BPSG
The film 8 and the polycrystalline silicon film 6 are removed by anisotropic etching until the surface of the silicon oxide film 5 is exposed, and an emitter contact hole 10 is formed. Thereafter, the mask is removed, and the silicon nitride film 11 is formed to a thickness of 6 by LPCVD.
Then, the silicon nitride film 11 is etched back (anisotropically etched) so that the silicon nitride film 11 is left only on the side surfaces of the contact holes 10 (FIG. 9 (K)). FIG. (L). Next, as shown in FIG. 6 (M), the silicon oxide film 5 exposed at the bottom of the contact hole 10 is immersed in an HF-based etchant and removed by wet etching. At this time, as shown in the figure, the lateral etching is performed until the lower surface of the polycrystalline silicon film 6 is exposed to a depth of, for example, about 150 nm.

After completion of the lateral etching, the upper surface of the single crystal silicon film 3 exposed at the bottom of the contact hole 10 and the lower surface of the p ⁺⁺ type polycrystalline silicon film 6
By the self-aligned epitaxial growth method, p
A monocrystalline SiGe film 12 and a polycrystalline SiGe film 13 are grown. This selective epitaxial growth is performed until the p-type single-crystal SiGe film 12 forming the base region is connected to the p-type polycrystalline SiGe film 13 (FIG. 3 (N)).

Next, a silicon nitride film 14 is deposited on the entire surface of the silicon nitride film 9 on which the emitter contact hole 10 is formed by LPCVD to a thickness of about 50 nm (FIG. 3 (O)). After a photoresist mask is formed on the film 14 by photolithography, the silicon nitride films 14 and 9, the BPSG film 8, the silicon oxide film 5, and the single crystal silicon film 3 reach the buried n ⁺ -type collector layer 4. The collector contact hole 15 is formed as shown in FIG.

Next, in order to separate the emitter region and the base region, the mask is removed and the silicon nitride film 9 is etched back (anisotropically etched) to leave it only on the side wall of the emitter contact hole 10 (the same as in the first embodiment). Figure (Q)). continue,
An n ⁺ -type polycrystalline silicon film 16 which is a conductive film doped with phosphorus is formed on the entire surface of the silicon nitride film 9 to a thickness of 500 n.
After being deposited to about m, etch back (anisotropic etching) is performed to leave the phosphorus-doped polycrystalline silicon film 16 only in the emitter contact hole 10 and the collector contact hole 15 ((R) in the same figure). By filling the emitter contact hole 10 with the phosphorus-doped polycrystalline silicon film 16 in this manner, a P-type emitter region is formed.

Next, a mask is formed by a photolithography method, and the silicon nitride film 9 and the BPSG film 8 are removed by anisotropic etching, as shown in FIG.
A base contact hole 17 is formed. This contact hole 17 exposes a part of the surface of the p ⁺⁺ -type boron-doped polycrystalline silicon film 6. Finally, a base electrode 18, an emitter electrode 19, and a collector electrode 20 are formed by depositing a metal film containing aluminum as a main component and patterning the same by a photolithography method (FIG. 1).
(T)).

As described above, according to the structure of this example, the BPS is formed on the polycrystalline silicon film 6 serving as the base lead electrode.
By depositing the G film 8 and flattening the deposited BPSG film 8 by selective polishing, the influence of the surface step due to the polycrystalline silicon film 6 is eliminated, so that a special process for preventing a short circuit between the electrodes is unnecessary. Becomes Therefore, the number of steps can be reduced as a whole. In addition, since unnecessary steps are not required, restrictions due to an alignment margin at the time of forming a mask are reduced, so that the element can be miniaturized. Also, BP
In the selective polishing of the SG film 8, only the convex portions having a high polishing rate need be polished, so that the polishing time can be greatly reduced, and the polishing is performed to flatten the BPSG film 8 while leaving the BPSG film 8 itself. In addition, control of polishing is much easier.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and there are design changes and the like that do not depart from the gist of the present invention. Is also included in the present invention. For example, in the above embodiment, the BPSG film was used.
G (Phospho-Silicate-Glass film may be used, or zinc glass or arsenic glass may be used. The point is that if it is a vitreous insulating film (passivation film) which can be easily planarized by selective polishing by a CMP method or the like. In the above embodiment, the npn-type bipolar transistor has been described, but the present invention can be applied to a pnp-type bipolar transistor.

[0030]

As described above, according to the structure of the present invention, the glass is formed on the second conductive type second conductive film (preferably, a polycrystalline silicon film) serving as the base lead electrode. Quality insulating film (as a preferred example, the BPSG film 8 is deposited, and the deposited glassy insulating film is planarized by selective polishing or the like to eliminate the influence of the surface step due to the second conductive film. This eliminates the need for a special process for preventing short-circuiting between the electrodes, thereby reducing the number of processes as a whole, and reducing the restriction due to the positioning margin when forming the mask because the extra process is unnecessary. In addition, in the selective polishing of the glassy insulating film, only the convex portions having a high polishing rate need be polished, so that the polishing time can be greatly reduced, and While leaving the insulating film itself glassy, since polishing for flattening this, control of the abrasive is more easily.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a schematic configuration of a bipolar semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view showing the method for manufacturing the same semiconductor device in the order of processes.

FIG. 3 is a process sectional view showing the method for manufacturing the same semiconductor device in the order of processes.

FIG. 4 is a process sectional view showing the method of manufacturing the same semiconductor device in the order of steps.

FIG. 5 is a process sectional view showing the method of manufacturing the same semiconductor device in the order of steps.

FIG. 6 is a process sectional view showing the method of manufacturing the same semiconductor device in the order of steps.

FIG. 7 is a process sectional view showing the method of manufacturing the semiconductor device in order of process.

FIG. 8 is a process sectional view showing the method of manufacturing the semiconductor device in order of process.

FIG. 9 is a process cross-sectional view showing a conventional method of manufacturing a bipolar semiconductor device in the order of processes.

FIG. 10 is a process sectional view showing a conventional method of manufacturing a bipolar semiconductor device in the order of processes.

FIG. 11 is a process sectional view showing a conventional method of manufacturing a bipolar semiconductor device in the order of processes.

FIG. 12 is a process cross-sectional view showing a conventional bipolar semiconductor device manufacturing method in the order of processes.

FIG. 13 is a process sectional view showing a conventional method of manufacturing a bipolar semiconductor device in the order of processes.

FIG. 14 is a process cross-sectional view showing a conventional method of manufacturing a bipolar semiconductor device in the order of processes.

[Explanation of symbols]

Reference Signs List 1 silicon substrate (substrate) 2 oxide film 3 single crystal silicon film (semiconductor layer) 4 buried collector layer (first conductivity type buried layer) 5 silicon oxide film (first insulating film) 6 polycrystalline silicon film (second Conductive second conductive film) 7 Groove 8 BPSG film (glassy insulating film) 9 Silicon nitride film 10 Contact hole for emitter electrode 11 Silicon film nitride film (second insulating film) 12 Single crystal SiGe film (second 2 conductive type first conductive film) 13 polycrystalline SiGe film (second conductive type first conductive film) 14 silicon nitride film (second insulating film) 15 collector electrode contact hole 16 phosphorus-doped polycrystalline silicon film (Third of first conductivity type
17 Contact hole for base electrode 18 Base electrode 19 Emitter electrode 20 Collector electrode

Claims (7)

[Claims] 1. A semiconductor layer having a buried layer of a first conductivity type forming a collector region on a substrate; a first insulating film formed on the semiconductor layer; A first conductive film of a second conductivity type formed to form a base region; and a second conductive film formed on the first insulating film and connected to the first conductive film to form a base lead electrode. A second conductive film of a conductive type; a first conductive type formed between the second conductive film and the second insulating film and formed on the first conductive film to form an emitter region; A bipolar semiconductor device comprising: a third conductive film, wherein the first insulating film and the second conductive film are covered with a vitreous insulating film, and the vitreous insulating film A bipolar semiconductor device, characterized in that the surface of the semiconductor device is flat. 2. The bipolar semiconductor device according to claim 1, wherein said glassy insulating film also serves as an element isolation insulating film. 3. The bipolar semiconductor device according to claim 1, wherein the vitreous insulating film is a BPSG film or a PSG film. 4. The method according to claim 1, wherein the second and third conductive films are made of a polycrystalline silicon film.
The bipolar semiconductor device as described in the above. 5. The bipolar semiconductor device according to claim 1, wherein said first conductive film is made of a SiGe film. 6. A first step of forming a semiconductor layer having a buried layer of a first conductivity type forming a collector region on a substrate, and a second step of forming a first insulating film on the semiconductor layer. And a second forming a base lead electrode on the first insulating film.
A third step of forming a conductive type second conductive film, and after covering the first insulating film and the second conductive film with a vitreous insulating film, removing the surface of the vitreous insulating film. A fourth step of performing a planarization process; and a first of a second conductivity type forming a base region on the semiconductor layer.
A fifth step of forming the conductive film of the second conductive film to be connected to the second conductive film, and the second conductive film being separated from the first conductive film by a second insulating film. Of the emitter region above the first
And a sixth step of forming a third conductive film of conductivity type. A method of manufacturing a bipolar semiconductor device, comprising: 7. The method of manufacturing a bipolar semiconductor device according to claim 6, wherein, in the fourth step, the surface of the vitreous insulating film is planarized by using a CMP method.