JPH06204193A - Manufacture of soi substrate - Google Patents

Abstract

PURPOSE:To provide the manufacture of an SOI substrate, which can thin the semiconductor layer with excellent controllability even if the SOI substrate is lamination-type one and which can make a transistor excellent in resistance to punch through. CONSTITUTION:This manufacture has a process of forming a stopper layer 10, where an opening 12 is made in specified pattern on the surface of a semiconductor substrate 2, a process of growing a single crystal semiconductor layer 14a on the surface of the semiconductor substrate exposed by the opening by epitaxial growth method and also, growing a polycrystalline semiconductor layer 14b on the surface of the stopper layer 10, a process of forming an insulating layer 16 on the surface of these single crystal semiconductor layer 14a and surface of the polycrystalline semiconductor layer 14b, and, sticking a supporting substrate together to it, and a process of grounding and polishing the rear of the semiconductor substrate with the stopper layer 10 as a stopper of polishing so as to expose the surface of the single crystal semiconductor layer 14a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bonded SOI substrate, and more specifically, a bonded S substrate.
The present invention relates to a method for manufacturing an SOI substrate, in which a semiconductor layer can be thinned with good controllability.

[0002]

2. Description of the Related Art In recent years, the SOI technology for forming a transistor in a silicon single crystal semiconductor layer formed on an insulating layer has been actively researched in order to form a transistor excellent in soft error resistance and high speed operation. ing. In particular, a bonded SOI substrate formed by a bonding technique and a selective polishing technique has excellent crystallinity and a small leak current, and thus is expected to be applied to a memory element such as a DRAM.

In order to obtain a substrate having an SOI structure by a bonding technique and a selective polishing technique, as shown in FIG. 6A, a separation stopper step 3 is formed on the surface (lower surface in the figure) of a silicon single crystal semiconductor substrate 2. After forming, the insulating layer 4 such as a silicon oxide film and the flattening film 6 such as a polysilicon film are formed on the surface thereof. Then, a support substrate 8 composed of a silicon single crystal semiconductor substrate or the like is attached to the surface of the flattening film 6.

Next, as shown in FIG. 1B, the surface of the semiconductor substrate 2 is selectively polished, so that the insulating layer 4 having the separation stopper steps 3 formed therein serves as a polishing stopper. The semiconductor layers 2a and 2b composed of silicon single crystal can be obtained. In the MOS transistor, a gate insulating layer and a gate electrode are formed on the semiconductor layers 2a and 2b, and the source / drain regions are formed on the semiconductor layers 2a and 2b in a self-aligned manner with the gate electrode by an ion implantation method or the like. Obtained by forming.

[0005]

However, when an SOI structure is manufactured by using a bonding technique and a selective polishing technique, a thick silicon single crystal wafer is ground and polished to leave a thin silicon single crystal semiconductor layer. Since it is a method, as shown in FIG. 6B, when a large-area semiconductor layer 2b is to be obtained, a recess is formed in the center of the semiconductor layer 2b due to sagging of a polishing cloth used in the selective polishing step. There is a problem such as occurrence of. That is, it was difficult to control the film thickness of the thin film.

By the way, in the MOS transistor using the SOI structure, by thinning the semiconductor layer, the control of the gate electric field to the channel region can be enhanced and punch through can be suppressed. That is, with the miniaturization of devices, it is required to reduce the thickness of the silicon single crystal semiconductor layer.

As the thickness of the semiconductor layer having such an SOI structure is further reduced, the depression formed in the central portion of the semiconductor layer has a great influence, and the characteristics of the MOS transistor formed thereon may be deteriorated.

Further, in the prior art, since the film thickness of the obtained semiconductor layers 2a and 2b is determined by the step 3 formed by the surface etching of the semiconductor substrate 2, the variation of the etching amount is included as an error. When an ordinary RIE apparatus is used for forming the step 3, it is difficult to suppress the variation within 5%, which is an obstacle to the control of the film thickness of the semiconductor layer.

The present invention has been made in view of the above circumstances, and in the method for manufacturing a bonded SOI substrate, the semiconductor layer can be thinned with good controllability and a transistor having excellent punch-through resistance can be manufactured. It aims at providing the manufacturing method of.

[0010]

In order to achieve the above object, a method of manufacturing an SOI substrate according to a first aspect of the present invention is a stopper in which an opening is formed in a predetermined pattern on the surface of a semiconductor substrate. A step of forming a layer, a step of growing a single crystal semiconductor layer on the surface of the semiconductor substrate exposed by the opening by an epitaxial growth method, and a step of growing a polycrystalline semiconductor layer on the surface of the stopper layer; The step of forming an insulating layer on the surfaces of the crystalline semiconductor layer and the polycrystalline semiconductor layer and adhering the supporting substrate, and the back surface of the semiconductor substrate is ground and polished by using the stopper layer as a polishing stopper, and the surface of the single crystal semiconductor layer. And exposing.

A method for manufacturing an SOI substrate according to a second aspect of the present invention is a multi-stage film in which openings are formed in a predetermined pattern on a surface of a semiconductor substrate and a thick film is formed corresponding to an element isolation pattern. By the step of forming a thick stopper layer and the epitaxial growth method, a single crystal semiconductor layer is grown on the surface of the semiconductor substrate exposed by the opening, and a polycrystalline semiconductor layer is formed on the surface of the stopper layer having a multi-step film thickness. The single crystal semiconductor deposited on the surface of the semiconductor substrate by the step of growing and polishing the surfaces of the single crystal silicon layer and the polycrystalline silicon layer using the stopper layer portion of the thick portion corresponding to the element isolation pattern as a polishing stopper. Layer and the polycrystalline semiconductor layer deposited on the stopper layer portion of the thin portion, and forming an insulating layer on the surface of the single crystal semiconductor layer and the polycrystalline semiconductor layer , Comprising the steps of laminating a supporting substrate,
And polishing the back surface of the semiconductor substrate using the stopper layer as a polishing stopper to expose the surface of the single crystal semiconductor layer.

[0012]

In the method for manufacturing an SOI substrate according to the first aspect of the present invention, the conventional method of forming the separation stopper step on the surface of the semiconductor substrate by etching or the like is amended so that a relatively narrow area such as a channel area of a transistor is formed. The entire surface of the removed semiconductor substrate is covered with a stopper layer, and an epitaxial layer is grown on the surface. In the subsequent step, the back surface of the semiconductor substrate is selectively ground and polished using the stopper layer as a polishing stopper. Therefore, the surface of the semiconductor substrate exposed during the selective polishing is limited to a relatively narrow region such as the channel region of the transistor. As a result, it is possible to eliminate the disadvantage that a recess is formed in the central portion of the semiconductor layer during selective polishing. Further, in the method of the present invention, the film thickness of the semiconductor layer formed on the insulating layer is determined not by the etching process with large variations, but by the film thickness of the epitaxial growth film on the semiconductor substrate. Therefore, it becomes easy to control the film thickness of the semiconductor layer. For example, in the present invention, it is possible to reduce the variation in the film thickness of the semiconductor layer to 5% or less. Therefore, in the present invention, the thinning of the semiconductor layer can enhance the control of the gate electric field to the channel region and suppress punch through.

In the epitaxial growth, the epitaxial layer grown from the surface of the semiconductor substrate through the opening of the stopper layer becomes a single crystal semiconductor layer, and the epitaxial layer grown from the surface of the stopper layer becomes a polycrystalline semiconductor layer. When at least the channel region of the transistor is formed of the single crystal semiconductor layer, the characteristics of the transistor are improved, and therefore the characteristics of the transistor are not deteriorated due to the formation of the polycrystalline semiconductor layer.

In the method of manufacturing an SOI substrate according to the second aspect of the present invention, the SOI substrate according to the first aspect of the present invention is basically used.
Although it has the same effect as that of the substrate manufacturing method, the stopper layer region having a larger thickness can be used as an element isolation region by forming the stopper layer in multiple stages. For example, by LOCOS, the element isolation region can be formed in a later step. The process for forming the film becomes unnecessary. Further, in the present invention, the film thickness of the obtained semiconductor layer is determined by the value obtained by subtracting the film thickness of the thinner stopper layer from the film thickness of the thicker stopper layer. Also in this case, the variation in the film thickness of the semiconductor layer can be reduced to within 5%, and the punch-through resistance of the transistor can be improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing an SOI substrate according to an embodiment of the present invention will be described in detail below with reference to the drawings.

1 and 2 show an SOI according to an embodiment of the present invention.
3 to 5 are schematic cross-sectional views showing a manufacturing process of a substrate, and FIGS. 3 to 5 are schematic cross-sectional views showing a manufacturing process of an SOI substrate according to another embodiment of the present invention.

An S according to an embodiment of the present invention shown in FIGS.
In the method of manufacturing the OI substrate, first, as shown in FIG. 1A, the stopper layer 10 is formed on the surface of the semiconductor substrate 2. As the semiconductor substrate 2, for example, a silicon single crystal wafer substrate is used. The stopper layer 10 formed on the surface of the semiconductor substrate 2 is formed of, for example, a silicon oxide layer formed by a thermal oxidation method, a silicon nitride layer formed by a CVD method, or the like. This stopper layer 10
Is not particularly limited, but is, for example, 10 to 30 n.
It is about m.

Next, in this embodiment, as shown in FIG. 1A, the opening 12 is formed in the stopper layer 10 in a pattern corresponding to the channel region of the transistor. The opening width of the opening 12 is determined according to the size of the channel region, and is, for example, about 1.0 μm in the 0.5 μm rule in consideration of the deviation in alignment with the channel width.

Thereafter, as shown in FIG. 1B, the stopper layer 1 having the opening 12 is formed by the epitaxial growth method.
Epitaxial layers 14a and 14b are formed on the surface of the semiconductor substrate 2 on which 0 is formed. The epitaxial layer becomes a good quality single crystal silicon layer 14a on the surface of the semiconductor substrate 2 exposed by the opening 12, and becomes a polycrystalline silicon layer 14b on the surface of the stopper layer 10. The film thickness of the single crystal silicon layer 14a becomes the film thickness of the semiconductor layer in which the finally obtained channel region is formed, and the variation in the film thickness can be within 5%. The film thickness of the single crystal silicon layer 14a is, for example, about 50 nm.

Next, as shown in FIG. 1C, an insulating layer 16 is formed on the surfaces of the epitaxial layers 14a and 14b. The insulating layer 16 is composed of a silicon oxide layer or a silicon nitride layer formed by a thermal oxidation method and a CVD method. The film thickness of the insulating layer 16 is, for example, 200 to 50.
It is about 0 nm.

Next, as shown in FIG.
A flattening layer 18 is formed on the surface of 6. As the flattening layer 18, for example, a polycrystalline silicon layer formed by a CVD method is used, and its film thickness is, for example, about 5 μm. The surface of the flattening layer 18 is flattened by, for example, polishing about 3 μm. Alternatively, the insulating layer 16 may be formed thick and the insulating layer 16 may be polished to be planarized without separately providing the planarizing layer 18. In that case, the insulating layer 16 also serves as a flattening layer.

Next, as shown in FIG. 2 (E), a supporting substrate 20 made of a silicon wafer or the like is bonded to the surface of the planarizing layer 18 whose surface has been planarized, and is thermally bonded. The bonding temperature for heat bonding is 900, for example.
It is about 1100 ° C. The bonding strength of the substrates after heat bonding is generally 200 kg / cm ² or more, and even 2000 kg / cm ² in some cases.

Thereafter, the semiconductor substrate 2 shown in FIG. 1 (D) is ground and polished from the back surface, and as shown in FIG. 2 (E),
The polishing of the semiconductor substrate is completed by using the stopper layer 10 as a polishing stopper. As a result, the single crystal silicon layer 1 formed by the epitaxial growth method on the surface of the insulating layer 16
4a and the polycrystalline silicon layer 14b remain. The single crystal silicon layer 14a becomes the channel region 22 of the transistor.

Next, as shown in FIG. 2F, a selective oxidation method (LOC) using a silicon nitride film having a predetermined pattern is used.
By the OS method), the portion of the polycrystalline silicon layer 14b where the element isolation region is to be formed is selectively oxidized, and
4 is formed.

Next, as shown in FIG. 2G, a gate insulating layer 26 is formed on the surface of the single crystal silicon layer 14a to be the channel region 22, and the gate electrode 2 is formed thereon.
8 is formed. The gate insulating layer 26 is composed of an insulating film such as a silicon oxide film formed by, for example, a thermal oxidation method, and the film thickness thereof is not particularly limited, but is, for example, 10 n.
It is about m. The gate electrode 28 is composed of a conductive layer of polysilicon, silicide, polycide, metal or the like, and R
The gate electrode is processed into a predetermined pattern by an etching method such as IE.

After that, if impurities for forming the source / drain regions are ion-implanted into the polycrystalline silicon layers 14b, 14b, the source / drain regions 30, 30 are formed in those portions.
Are formed in self-alignment with the gate electrode 28.
Ion implantation conditions are not particularly limited, but NMO may be used.
In the case of forming S, the dose of As is 1 × 10 ¹⁵ cm
^- 2, carried out under the conditions of energy 50 KeV. The channel region 22 is formed in the portion of the single crystal silicon layer 14a below the gate electrode 28.

Thereafter, as shown in FIG. 3H, an interlayer insulating layer 32 is formed on the gate electrode 28, and contact holes 34 for the source / drain regions 30, 30 are formed.
34 is formed in the interlayer insulating layer 32, and electrode layers 36, 36 connected to the source / drain regions are embedded and formed in the contact holes 34, 34. Interlayer insulation layer 32
Is not particularly limited, but is formed of a silicon oxide film, a silicon nitride film, a PSG film, a BPSG film, or the like formed by a CVD method. The electrode layer 36 is made of a metal such as aluminum.

In the method of manufacturing an SOI substrate according to this embodiment, the conventional method of forming a separation stopper step on the surface of the semiconductor substrate 2 by etching or the like is modified, and a semiconductor except a relatively narrow region such as a channel region of a transistor is removed. The entire surface of the substrate 2 is covered with the stopper layer 10, and epitaxial layers 14a and 14b are grown on the surface. In the subsequent step, the back surface of the semiconductor substrate 2 is selectively ground and polished as shown in FIG. 2E, using the stopper layer 10 as a polishing stopper. Therefore, the surface of the semiconductor substrate exposed during the selective polishing is limited to a relatively narrow region such as the channel region 22 of the transistor. As a result, it is possible to eliminate the disadvantage that a recess is formed in the central portion of the semiconductor layer 14a during selective polishing.

Further, according to the method of this embodiment, the single crystal silicon layer 14 to be the channel region formed on the insulating layer 16 is formed.
The film thickness of a is not determined by the etching process with large variations, but by the film thickness of the epitaxial growth film on the semiconductor substrate. Therefore, the single crystal silicon layer 1
It becomes easy to control the film thickness of 4a. For example, in the present invention, it is possible to reduce the variation in the film thickness of the single crystal silicon layer 14a to 5% or less. Therefore, in the present invention, by thinning the single crystal silicon layer 14a, the control of the gate electric field to the channel region 22 can be enhanced and punch through can be suppressed.

In this embodiment, the source / drain region regions 30 and 30 are formed not in the single crystal silicon layer but in the polycrystalline silicon layer. However, the channel region 22 which greatly affects the performance of the transistor is formed in the single crystal region. Silicon layer 14
Since it is formed in a, there is no problem such as deterioration of transistor characteristics.

Next, a method of manufacturing an SOI substrate according to various embodiments of the present invention will be described with reference to FIGS.

In this embodiment, as shown in FIG.
Semiconductor substrate 2 composed of single crystal silicon wafer, etc.
A relatively thick first stopper layer 33 is formed on the surface of the.
The first stopper layer 33 is formed of, for example, a silicon oxide layer formed by a thermal oxidation method, a silicon nitride layer formed by a CVD method, or the like. The thickness of the first stopper layer is, for example, about 50 to 60 nm. In the first stopper layer 33, a thin film forming opening 31 is formed by etching or the like corresponding to a region which becomes an active region of the transistor. As a result, the relatively thick first stopper layer 33 is processed into the pattern of the element isolation region. At the time of etching processing, the surface of the semiconductor substrate 2 is hardly etched by using an etching liquid having a high selection ratio.

Next, as shown in FIG. 3B, a second stopper layer 35 thinner than the first stopper layer 33 is formed on the surface of the semiconductor substrate 2 exposed by the thin film forming opening 31. The second stopper layer 35 is formed of, for example, a silicon oxide layer formed by a thermal oxidation method, and its film thickness is, for example, about 10 nm. Since the film thickness of the first stopper layer 33 minus the film thickness of the second stopper layer 35 determines the film thickness of the finally obtained semiconductor layer, these first and second stopper layers 33, 35 are formed. The film thickness variation is 5
Can be kept within%.

Next, in the present embodiment, as shown in FIG. 3C, the opening 38 is formed in a pattern corresponding to the channel region of the transistor with respect to the relatively thin second stopper layer 10.
To form. The opening width of the opening 38 is determined according to the size of the channel region, and is, for example, about 1.0 μm in the 0.5 μm rule in consideration of the deviation in alignment with the channel width.

After that, as shown in FIG. 3D, the epitaxial layers 40a, 40a are formed on the surface of the semiconductor substrate 2 on which the second stopper layer 35 and the first stopper layer 33 having the openings 38 are formed by the epitaxial growth method. 40b is formed. On the surface of the semiconductor substrate 2 exposed by the opening 38, the epitaxial layer is formed of a good quality single crystal silicon layer 40.
Thus, the polycrystalline silicon layer 40b is formed on the surfaces of the stopper layers 33 and 35. The film thickness of the single crystal silicon layer 40a and the polycrystalline silicon layer 40b formed by this epitaxial growth method is, for example, about 200 to 500 nm.

Next, as shown in FIG. 4 (E), the single crystal silicon layer 4 formed by the epitaxial growth method using the relatively thick first stopper layer 33 as a polishing stopper.
0a and the polycrystalline silicon layer 40b are selectively polished to leave the single crystalline silicon layer 42a and the polycrystalline silicon layer 42b which are semiconductor layers only in the active region. In this selective polishing, since the polishing amount is small and uniform, the depression of the central portion of the semiconductor layer as seen in the prior art does not occur.

Next, as shown in FIG. 4F, an insulating layer 44 is formed on the surfaces of the single crystal silicon layer 42a and the polycrystalline silicon layer 42b. The insulating layer 44 is composed of a silicon oxide layer or a silicon nitride layer formed by a thermal oxidation method and a CVD method. The insulating layer 44 has a film thickness of, for example, about 200 to 500 nm.

Next, as shown in FIG. 4G, the insulating layer 4
A flattening layer 46 is formed on the surface of No. 4. As the flattening layer 46, for example, a polycrystalline silicon layer formed by a CVD method is used, and its film thickness is, for example, about 5 μm. The surface of the flattening layer 46 is flattened by polishing, for example, about 3 μm. It is also possible to form the insulating layer 44 thick and polish the insulating layer 44 without providing the flattening layer 46 separately. In that case, the insulating layer 44 also serves as a flattening layer.

Next, as shown in FIG. 5 (H), a support substrate 48 made of a silicon wafer or the like is attached to the surface of the flattened layer 46 whose surface is flattened and heat-bonded. The bonding temperature for heat bonding is 900, for example.
It is about 1100 ° C. The bonding strength of the substrates after heat bonding is generally 200 kg / cm ² or more, and even 2000 kg / cm ² in some cases.

After that, the semiconductor substrate 2 shown in FIG. 4G is ground and polished from the back surface, and as shown in FIG.
The polishing of the semiconductor substrate is completed by using the stopper layers 33 and 35 as polishing stoppers. As a result, the single crystal silicon layer 42a and the polycrystalline silicon layer 42b formed by the epitaxial growth method remain on the surface of the insulating layer 44. The single crystal silicon layer 42a becomes a channel region of the transistor.

Next, as shown in FIG. 5 (I), a gate insulating layer 50 is formed on the surface of the single crystal silicon layer 42a to be the channel region 56, and the gate electrode 5 is formed thereon.
Form 2. The gate insulating layer 50 is formed of an insulating film such as a silicon oxide film formed by, for example, a thermal oxidation method, and the film thickness thereof is not particularly limited, but is, for example, 10 n.
It is about m. The gate electrode 52 is composed of a conductive layer of polysilicon, silicide, polycide, metal or the like, and R
The gate electrode is processed into a predetermined pattern by an etching method such as IE.

After that, if impurities for forming the source / drain regions are ion-implanted into the polycrystalline silicon layers 42b, 42b, the source / drain regions 54, 54 are formed in those portions.
Are formed in self-alignment with the gate electrode 52.
Ion implantation conditions are not particularly limited, but NMO may be used.
In the case of forming S, the dose of As is 1 × 10 ¹⁵ cm
^-2 , energy is 50 KeV. A channel region 56 is formed in the portion of the single crystal silicon layer 42a below the gate electrode 52.

Thereafter, as shown in FIG. 5 (J), an interlayer insulating layer 57 is formed on the gate electrode 52, and contact holes 58 for the source / drain regions 54, 54 are formed.
58 is formed in the interlayer insulating layer 57, and electrode layers 60, 60 connected to the source / drain regions are embedded and formed in the contact holes 58, 58. Interlayer insulation layer 57
Is not particularly limited, but is formed of a silicon oxide film, a silicon nitride film, a PSG film, a BPSG film, or the like formed by a CVD method. The electrode layers 60, 60 are made of metal such as aluminum.

In the method of manufacturing an SOI substrate according to this embodiment, the SO substrate according to the embodiment shown in FIGS.
Although it has the same effect as that of the I substrate manufacturing method, the region of the thicker stopper layer 33 can be used as an element isolation region by making the thicknesses of the stopper layers 33 and 35 in multiple stages. The step for forming the element isolation region in the step becomes unnecessary.

Further, in the present embodiment, the film thickness of the single crystal silicon layer 42a in which the channel region 56 is formed is from the film thickness of the thicker first stopper layer 33 to the film thickness of the thinner second stopper layer 35. It is determined by the value minus. Also in this case, the variation in the film thickness of the single crystal silicon layer can be reduced to within 5%, and the punch-through resistance of the transistor can be improved.

The present invention is not limited to the above-mentioned embodiments, but can be variously modified within the scope of the present invention.

For example, in the embodiment shown in FIGS.
In order to obtain the stopper layers 33 and 35 having the multi-stage film thickness structure shown in (B), the thin film forming opening 31 is once formed in the first stopper layer 33, and then the relatively thin second stopper layer 35 is formed. However, the present invention is not limited to this, and the stopper layer 3 having a multi-stage film thickness structure is formed as follows.
It is also possible to form 3,35. That is, the first stopper layer 33 that is relatively thick over the entire surface of the semiconductor substrate 2
Then, the first stopper layer 33 is etched in a pattern corresponding to the active region of the transistor, and the etching depth is controlled, so that the relatively thin second stopper layer 35 is formed.
Can also be formed. However, in the case of this embodiment, the film thickness of the semiconductor layer is controlled by the etching amount.

[0048]

As described above, according to the present invention, the surface of the semiconductor substrate which is exposed during the selective polishing for forming the bonded SOI substrate is a transistor corresponding to the opening formed in the stopper layer. It is limited to a relatively narrow area such as a channel area. As a result, it is possible to eliminate the disadvantage that a recess is formed in the central portion of the semiconductor layer during selective polishing.

Further, in the method of the present invention, the film thickness of the semiconductor layer formed on the insulating layer is not determined by the etching process with large variations, but the film thickness of the epitaxial growth film on the semiconductor substrate, or It is determined by a value obtained by subtracting the film thickness of the thinner stopper layer from the film thickness of the thicker stopper layer in the stopper layer having a multi-stage film thickness. Therefore, it becomes easy to control the film thickness of the semiconductor layer. For example, in the present invention, it is possible to reduce the variation in the film thickness of the semiconductor layer to 5% or less. Therefore, in the present invention, the thinning of the semiconductor layer can enhance the control of the gate electric field to the channel region and suppress punch through.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a process of manufacturing an SOI substrate according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the SOI substrate according to the example.

FIG. 3 is a schematic cross-sectional view showing a process of manufacturing an SOI substrate according to another embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing the process of manufacturing the SOI substrate according to the example.

FIG. 5 is a schematic cross-sectional view showing the manufacturing process of the SOI substrate according to the example.

FIG. 6 is a schematic cross-sectional view showing a manufacturing process of an SOI substrate according to a conventional example.

[Explanation of symbols]

 2 ... Semiconductor substrate 10 ... Stopper layer 12 ... Openings 14a, 40a, 42a ... Single-crystal silicon layer 14b, 40b, 42b ... Polycrystalline silicon layer 16, 44 ... Insulating layer 18, 46 ... Planarization layer 20, 48 ... Support Substrate 22, 56 ... Channel region 26, 50 ... Gate insulating layer 28, 52 ... Gate electrode 30, 54 ... Source / drain region region 31 ... Thin film forming opening 33 ... First stopper layer 35 ... Second stopper layer 38 ... Aperture

Claims (5)

[Claims] 1. A step of forming a stopper layer in which an opening is formed in a predetermined pattern on the surface of a semiconductor substrate, and a single crystal semiconductor layer is formed on the surface of the semiconductor substrate exposed by the opening by an epitaxial growth method. A step of growing a polycrystalline semiconductor layer on the surface of the stopper layer, and a step of growing the single crystal semiconductor layer and the polycrystalline semiconductor layer on the surface of the stopper layer.
A method for manufacturing an SOI substrate, which includes a step of forming an insulating layer and bonding a supporting substrate, and a step of grinding and polishing the back surface of the semiconductor substrate using the stopper layer as a polishing stopper to expose the surface of the single crystal semiconductor layer. . 2. A step of forming a stopper layer having a multi-step film thickness in which a plurality of openings are formed in a predetermined pattern on a surface of a semiconductor substrate and corresponding to an element isolation pattern, and an epitaxial growth method is used. Growing a single crystal semiconductor layer on the surface of the semiconductor substrate exposed by the opening and growing a polycrystalline semiconductor layer on the surface of the stopper layer having a multi-step film thickness, and the single crystal silicon layer and the polycrystalline silicon layer. The surface of the layer is polished by using the stopper layer portion of the thick portion corresponding to the element isolation pattern as a polishing stopper, and the single crystal semiconductor layer deposited on the surface of the semiconductor substrate and the multi-layer deposited on the stopper layer portion of the thin portion. The step of leaving the crystalline semiconductor layer and the surface of the single crystal semiconductor layer and the polycrystalline semiconductor layer,
A method for manufacturing an SOI substrate, which includes a step of forming an insulating layer and bonding a supporting substrate, and a step of grinding and polishing the back surface of the semiconductor substrate using the stopper layer as a polishing stopper to expose the surface of the single crystal semiconductor layer. . 3. The SOI substrate according to claim 1, further comprising the step of forming a channel region in the single crystal semiconductor layer and forming source / drain region regions in the polycrystalline semiconductor layer. Production method. 4. A semiconductor layer having a relatively thick stopper layer having a thin film forming opening formed in a pattern corresponding to an active region of a transistor, formed on the surface of a semiconductor substrate, and then exposed by the thin film forming opening. By forming a relatively thin stopper layer on the surface of the substrate and forming openings in the relatively thin stopper layer in a pattern corresponding to the channel region of the transistor, the stopper layer having the above-mentioned multi-stage film thickness is formed. It is formed, The claim 2 or 3 characterized by the above-mentioned.
A method for manufacturing an SOI substrate according to item 1. 5. The SOI substrate according to claim 1, wherein a flattening layer is laminated on a surface of the insulating layer, and the supporting substrate is bonded via the flattening layer. Production method.