JPH11212606A - Programming device and program monitoring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programming device for automatically generating a program with which it is monitored whether an indirectly designated address is suitable or not and an alarm is outputted corresponding to the monitored result. SOLUTION: The monitor program for monitoring the contents of a pointer is automatically generated and when an abnormal value is stored in the pointer, the alarm is issued. When the increment values of the reference program and the addresses of respective circuit elements are designated in the case of programming to repeat a similar program, the program is automatically expanded and in the correction, the source program is reproduced. Besides, the memory contents of respective circuit elements in the program are time sequentially displayed together with a ladder diagram.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable controller used in the FA field.

[0002]

2. Description of the Related Art Programmable controllers have been developed as replacements for relay boards, and control by calculating Boolean algebras such as AND and OR. In recent years, with the development of microprocessors, they have been called application instructions. Numerical operations such as addition, subtraction, multiplication and division can be performed. Some of the application instructions are similar to the assembly language of a microprocessor, and an address can be indirectly specified using a pointer.

When a program using a pointer is shown in a ladder diagram in which a circuit diagram and an application instruction are combined, for example, a ladder diagram as shown in FIG. 1 is obtained. "MOV" is one of the application instructions 1 representing the assignment, in this case, "When the relay 2 (address is 0000) is ON, the memory content at the address 9000 is assigned to the address specified at the address 9100". Is a pointer 3 indicating the indirect designation of an address
Is represented.

FIG. 2 shows the operation according to the memory map. The contents "5555" at address 9000 are assigned to the address "9300" designated at address 9100. At this time, for example, at address 9100, the value of address 9100 that changes according to some condition =
Since it is possible to dynamically change the address of the substitution destination by storing it as a variable such as b + a * i, which is useful for simplifying the program, indirect designation using a pointer is frequently used.

When an address is specified indirectly in a program, the address specified by the pointer is not explicit in the program ("9300" is not displayed in FIG. 1). May be an unintended value. In such a case, theoretically, any address in the memory can be an assignment destination, so there is a risk that important data may be destroyed or a program may not be executed normally. The same applies when the value of the pointer becomes an abnormal value due to a malfunction of hardware during execution of the program.

As a method for avoiding this, Japanese Patent Laid-Open No. 6-2
Japanese Patent Laid-Open No. 22958 discloses a method of allocating a variable to a memory at the time of compilation with a plurality of methods for misuse of a pointer in the C language, and comparing and checking a plurality of compiled objects.

Next, when a program having a plurality of circuit configurations similar to each other is created by a programmable controller, usually, a method of creating all the circuits 40 one by one in a ladder diagram format as shown in FIG. A method is used in which a reference program 41 is created, copied, and the addresses of circuit elements (sensors, proximity switches, solenoids, lamps, etc.) such as input / output devices are changed to create a duplicate program 42 and repeatedly obtain a program 50. Can be

In the figure, LS1 to LS4 are limit switches, / EMER is the reversal of emergency stop, SOL1,
SOL2 indicates a solenoid, and LS1, LS3,
/ EMER, the second-stage SOL1 and the fourth-stage SOL2 are input devices that are connected when turned on, and LS2 and LS4 are input devices that are connected to be turned off when turned on. SOL1 of the first stage is LS1, LS2, / EMER
Represents an output device that turns on when connected at the same time.
The same applies to SOL2 at the stage. The numerical value above each circuit element indicates the address number of each element.

[0009] For a ladder diagram with high diversion,
A method of registering as a library and calling it when necessary to make corrections, a method of using a macro library to increase or decrease a relay number or a register number by a certain amount at the time of calling and collectively processing them, and the like are also used.
No. 60 proposes a method of registering a symbol as a common symbol in a library and developing the symbol in a ladder diagram format when necessary.

[0010] Alternatively, a method is also used in which the program is looped by the required number of times using the FOR to NEXT instructions, and the relay number or the register number is increased or decreased by a fixed amount to create a program at once.

[0011] Next, when checking the operation of the input / output device when the program is executed by the programmable controller, a method of monitoring the state of the equipment is as follows.
On / off information of circuit elements (hereinafter referred to as “bit information”) and numerical information stored in a register (hereinafter referred to as “register information”. It is bit information that indicates whether or not register information is stored in a register. ) Focuses on a specific circuit element or register, displays its memory contents by specifying its address, monitors the change, or monitors the operation by adding bit information and register information to the ladder diagram and displaying it. There is a way.

Since these methods are performed on-line, the display switching speed is high and the contents cannot be visually recognized, and detailed timing cannot be confirmed, so that effective monitoring cannot be performed.

On the other hand, Japanese Patent No. 261663 proposes a method of displaying bit information in a time chart format so that a change in the bit information can be confirmed in a time series. According to this method, as shown in FIG. 4, the operation state of each circuit element (address 0000 to 0002) at every unit time t0 is displayed, and the on / off timing of each circuit element can be known. I have.

[0014]

In the case where an abnormal address value is stored when an address is indirectly specified by a program, the method disclosed in Japanese Patent Laid-Open No. 6-222958 discloses a method in which a programmable controller uses a variable. Is not automatically allocated to memory, requires more memory to store multiple objects, and must be compiled for each test, requiring more time to verify become.

Further, it is conceivable to improve the application instruction itself such that an address range that can be accessed when the indirect specification is performed by the application instruction is simultaneously specified so that writing to an address outside the range cannot be performed. Since there are many types of application instructions that can be indirectly specified, enormous man-hours are required to create such application instructions with added functions.

Next, when a program having a plurality of similar circuit configurations is created by a programmable controller, it takes a lot of time to create a program if the method is to create a program for all circuits one by one. Also,
A method of correcting the address of a circuit element after repeatedly calling a copy of a reference circuit or a library is as follows.
If the number of repetitions increases, omission of correction or erroneous correction may occur.

In the method of developing a macro library or developing a symbol in a ladder diagram format, processing can be performed collectively at the time of program creation, and the program creation time can be reduced. When the address is changed, omission of correction or erroneous correction may occur as described above.

When the program is created by using the FOR to NEXT instructions, the address of a circuit element is incremented (increased) every time a similar circuit is repeated during execution of a program.
The execution speed of the program is reduced due to the computations that cause it to be performed, and it is difficult to compare the state of each circuit element with the displayed ladder diagram, so the state of each circuit element being executed during debugging etc. There is a problem that can not be determined.

Next, in the case of confirming the operation of the input / output device when the program is executed by the programmable controller, the method disclosed in Japanese Patent No. 261663 knows the execution result of the program stored in advance in time series. It is useful for confirming the order of ON / OFF of the relay and the change history of the register.

However, in the time chart as shown in FIG. 4 described above, it is not possible to judge the progress of the program execution because the relationship between the circuit elements is not known. However, it is necessary to perform the comparison, which is inefficient and increases the working time.

An object of the present invention is to provide a program creating apparatus for monitoring whether an indirectly designated address is appropriate and automatically creating a program for outputting an alarm according to the monitoring result.

Further, according to the present invention, when a program in which a similar program is repeated is used, work can be performed collectively at the time of program creation / change, and at the time of program execution, the execution speed is high and the operation of each element can be performed. An object of the present invention is to provide a program creating apparatus for automatically adding a program that allows a user to visually recognize a corresponding ladder diagram.

Another object of the present invention is to provide a monitor device of a programmable controller which can check the state of each circuit element in a program in a time series on a ladder diagram.

[0024]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention has means for designating an access range in which an address indirectly specified by an indirectly specifiable instruction can be accessed, wherein the address and the access are specified. A program that stops the program or outputs an alarm according to the result of comparison with the range is added so as to be executed before the instruction.

According to this configuration, when an indirect designation command is described in a program by a user, an input screen for inquiring about a range in which the indirectly designated address can be accessed is displayed. A monitoring program for monitoring whether the specified address is within the accessible range is automatically created so as to be executed before the indirect designation instruction.

Further, the present invention comprises means for preventing the monitoring program from being displayed on a screen. According to this configuration, a monitoring program unrelated to the design circuit is not displayed on the display screen as needed.

Further, when creating a program in which a similar program having circuit elements and registers is repeated a plurality of times, the first reference program, the number of duplications for duplicating the first program, and the first program Means for designating a change rule for changing a circuit element or a register for each copy program obtained by duplicating a program; and copying the first program the number of times of copying and changing a circuit element or a register in accordance with the change rule Means for creating a second program, and means for recording, in a third program, information from which the first program, the change rule, and the number of duplications can be derived, wherein the second and third programs are provided. When displaying a program including the second program, the second,
The program includes means for reproducing the first program and the change rule from a third program, and first display means for displaying the first program, the change rule, and the number of times of copying.

According to this configuration, when the copy source program (first program), the number of times of copying, and the increment amount for incrementing the address of each circuit element or register included in the program for each copy are specified, a similar result is obtained. A desired program (second program) that repeats the program is automatically created, and a third program indicating information such as the start position, end position, and the number of times of duplication of the second program is automatically added. You. When displaying this program, the source program and the increment are obtained from the start position, the final position, and the number of copies, and the source program, the increment, and the number of copies are represented in a ladder diagram. It is displayed.

Further, the present invention has second display means for displaying the second program so that the display can be switched between the first display means and the second display means. Has become.

According to this configuration, it is possible to switch so as to display the original program, the increment amount and the number of times of copying when the program is modified, and to display the entire second program when executing the program. .

The present invention further comprises a storage means for storing the contents of the memory in a time-series manner when the program of the programmable controller is executed, and sequentially fetching the contents of the memory from the storage means in a time-series at an arbitrary timing. The state of the circuit elements and registers inside are displayed together with the ladder diagram.

According to this configuration, the progress of execution of the program is stored, and each time a trigger is input from the user off-line, the state of each circuit element and register per unit time is called and sequentially displayed on the ladder diagram. Become like

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings. Application instruction 1 as shown in FIG.
When the pointer 3 is described in the input screen, an input screen 6 is displayed as shown in FIG.

The input screen 6 has an upper limit address 7, which can be accessed by an address designated by the pointer 3,
The lower address 8 that can be accessed, the address 9 of the relay that issues an alarm when the address specified by the pointer 3 is not between the upper address 7 and the lower address 8, and the address specified by the pointer 3 are the upper limit A switch 4 for selecting whether to stop or continue the execution of the program when it is not between the address 7 and the lower limit address 8, a switch 5 for selecting whether to display a monitoring program described later on the screen, and the like. Then, when the user inputs, the "OK" button is selected and the input screen 6 is closed.

Then, a monitoring program 30 as shown in the ladder diagram of FIG. 1
The “WCMP” at the bottom is an application instruction for determining whether or not the contents of the address indicated by the argument 13 are between the arguments 17 and 18. The register 13 of the first argument has the address of the pointer 3, The upper limit address 7 is assigned to the register 17 of the second argument, and the lower limit address 8 is assigned to the register 18 of the third argument. The flag 21 (address 1000) corresponding to the execution result of “WCMP” is “WCM”.
It turns on when the execution result of "P" is true, and turns off when it is false. The address of the flag 21 is determined in advance.

The flag 21a in the second stage indicates the execution result of the flag 21 and is turned off when the flag 21 is true. The flag 21a is connected when the execution result of "WCMP" is false, and is connected to the alarm relay 22 (address 1234). Is turned on. As the address of the alarm relay 22, the address 9 of the relay that issues an alarm on the input screen 6 is substituted.

When the alarm relay 22 is turned on, the buzzer 23 and the light 24 are turned on by a circuit as shown in FIG.
Is turned on and an alarm can be issued.

The flag 21b at the third stage in FIG.
1 shows the execution result, and is inserted when “Stop” is selected by the switch 4 on the input screen 6 and “WCM” is displayed.
"MOV" is executed only when the execution result of "P" is true.

FIG. 8 is a flowchart of the procedure for creating the monitoring program 30 described above. First, WC
FIG. 6 with MP instruction, flag 21 and alarm relay 22
The monitoring program 30 having such a circuit is inserted before the indirect designation command (110). Next, the address of the pointer 3 and the WCM are stored in the register 13 of the first argument of the WCMP instruction.
The address 7 of the upper limit is stored in the register 17 of the second argument of the P instruction,
The lower limit address 8 is assigned to the register 18 of the third argument of the WCMP instruction (120). Next, the address 9 of the alarm relay is substituted into the address of the alarm relay 22 (130). Next, it is determined whether or not "stop" is selected in the switch 4 (140). If it is selected, the flag 21b is inserted (150), and the process ends (160).

Next, when the switch 5 for selecting whether or not to display the monitoring program on the input screen 6 has been selected not to be displayed, the display format is created according to the flowchart shown in FIG. You.

First, it is determined whether the circuit has the WCMP instruction, the flag 21 and the alarm relay 22 as shown in FIG. 6 (210), and the register 13 of the first argument of the WCMP instruction is the same as the address of the pointer 3. Is checked (220). Next, in the case of yes, it is determined that the monitoring program has been inserted, so it is determined whether or not the switch 5 is selected to “display” (230).
The image is displayed without the 0 part (240). If any of the above is no, the program is displayed without performing any processing (250).

By being able to select the display format in this way, it is possible to prevent a monitoring program unrelated to the design circuit from being displayed on the display screen as required.

It should be noted that an alarm can be issued when the address specified by the pointer 3 is within the access range. It is also possible to select whether or not to output an alarm, and it may be possible to have only one of outputting an alarm or stopping a program.

In the present embodiment, the program of the programmable controller has been described. However, it is also possible to monitor other languages such as an assembly language and a C language in which addresses can be specified indirectly in the same manner.

As described above, by creating and inserting the monitoring program 30 in accordance with the contents input on the input screen 6, an alarm can be issued when an abnormal value is stored at the address specified by the pointer. It is also possible to stop the program, thereby preventing destruction of important data and runaway of the program.

Next, FIG. 10 shows the relationship between a programmable controller and a program creating device for the programmable controller. The programmable controller 46 is connected to the personal computer 43 via an interface 45 such as RS232C or RS422, and is controlled by a program created by a program creating device 44 which is software operating on the personal computer 43. By operating the 43, it is possible to read and write a program.

A second embodiment of the present invention will be described with reference to FIGS. In FIG. 3 described above, when a program that repeats a similar program is created, a reference program (first program) 41 serving as a reference for repetition is created or a repetition range is designated after calling from a library. For example, when a command having a name such as “repeat input” is selected, the number of times of copying is input, and then an input screen 47 as shown in FIG.
Is displayed.

On the input screen 47, addresses of circuit elements such as LS1 and SOL1 included in the program 41 and registers are displayed, and it is possible to input an increment amount for increasing or decreasing each address for each copy. I have.

In the example of FIG. 3, the number of duplications is two,
(Address 000000), LS2 (address 0000)
1), / EMER (address 00200), SOL1
When the increments of (address 00100) are input as +2, +2, 0, and +1 and the input screen 47 is closed, a repetitive program (second program) 50 as shown in FIG. 12 is created. The address of the circuit element included in the copy program 42 similar to the reference program 41 is incremented as specified and changed to a desired circuit element such that LS3 is replaced at the position of LS1.

However, when the repetitive program 50 has a large number of duplications, omission of correction or erroneous correction is likely to occur when the program is corrected. In order to avoid this, FIG.
As shown in (3), a third program 54 including an instruction 51 indicating the start position of the repetition program 50, an instruction 52 indicating the number of times the reference program 41 is duplicated, and an instruction 53 indicating the end position of the repetition program 50 is added When the repetition program 50 is corrected by performing the above operation, the reference program 40 and the increment of the address of each circuit element are derived, and the repetition program 50 is modified.
Can be displayed in a ladder diagram 50 'as shown in FIG.

In the figure, the operator and the numerical value added to the address number of each circuit element indicate the increment amount for each copy of the address of each circuit element. FIG. 14 shows a flowchart when the ladder diagram 50 'is created.

First, it is determined whether the instruction described in the program is an instruction indicating the head position (310), and if no, it is displayed as it is (320). Next, the number of times of copying is obtained and stored in the variable A (330). Next, the last position of the repetitive program 50 is detected (340). Next, the number of command words for setting circuit elements, registers, and the like from the start position to the end position of the repetitive program 50 is obtained and stored in the variable B (350).

Next, the number of instruction words C = A / B included in the reference program 41 is calculated (360). Here, it may be determined whether or not the variable C is an integer in order to confirm an error at the time of duplication or the like. Next, for the circuit elements whose program addresses indicating the order in the repetitive program 50 of each circuit element are 1 to C, the circuit element whose program address is i (i is 1 to C) and the circuit element whose program address is i + C are The address difference D (i) is calculated (370 to 400). Here, D (i) uses an array variable whose number of elements is C. If the number of copies (A) is two, the ladder diagram 50 'is displayed here and the process ends.
If the number of times is three or more, the following operation is performed (410).

Next, when the program address is 1 + C
Calculate the address difference E (i) between the circuit element having the program address of i + C × j and the circuit element having the program address of i + C + C × j for the circuit elements from × j (j is 1 to A−2) to C + C × j. Then, it is checked whether the address difference (increment amount) is constant (420 to 46).
0). This operation is repeated until j becomes A-2 (4
70 to 480) All circuit elements are checked, and if the increment is not constant, it is displayed as it is and the process ends (500).

If the increment amount for each copy in each circuit element is constant for all circuit elements, a ladder diagram 50 'displaying the reference program 41 and the increment amount is displayed as shown in FIG. 13 (490). become.

When the program is modified, the ladder diagram shown in FIG.
By displaying 0 'and correcting the address and the increment of the address, it is possible to reduce omission of correction and the like.
If the display is switched to 0 or the entire program 60, the state of each circuit element and register at the time of program execution can be grasped on a ladder diagram, so that the state of equipment operation can be easily understood and debugging can be facilitated. Is desirable.

The third program 54 is displayed when the program is modified so that the user can know the range of similar programs. However, if the start position and the last position of the reference program 41 and the number of times of duplication can be identified, the third program 54 can be identified. The third program 54 is unnecessary when the repetitive program 50 is displayed, and may be hidden.

The third program does not always need to be inserted at the position shown in FIG. 12, but may be inserted at another position as long as the start position, the last position, and the number of times of duplication of the repetitive program 50 can be determined.

Even if the third program 54 records, for example, the start position of the repetition program 50, the start position and the end position of the reference program 41 or the copy program 42, and the number of times of duplication, the reference program It is possible to derive 41 and the increment of the address of each circuit element, and other information may be recorded as long as the reference program 40 and the increment of the address of each circuit element and the number of times of duplication can be derived.

Next, a third embodiment of the present invention will be described. FIG. 15A is a ladder diagram 70 showing an example of a program, and numerical values indicate addresses of circuit elements. The first and second stages in the figure are input devices 71 (address 000000) such as switches and relay contacts and input devices 72.
An OR circuit that turns on the relay 73 (address 00100) when any of the (address 00001) is turned on is provided. The third stage is a relay contact 73a (address 001).
00) and the input device 74 (address 00002) are turned on, and the output device 75 (address 00200) such as a relay or a lamp is turned on.

In the case of the program shown in (a), when each circuit element is turned on and off at the timing shown in (b), for example, when the program is executed, the time chart becomes as shown in (c). In (b), 1 and 0 represent ON and OFF, respectively.

FIG. 16 stores time series data of each circuit element when the program 70 is executed.
(C) is an example in which each circuit element operating at every unit time t0 is displayed on the ladder diagram so as to be distinguished, and (a) to (d) are switched by a user inputting a trigger. You can do it.

According to such a display, it is possible to judge the progress of the execution of the program, and it is not necessary to switch and display the ladder diagram and the time chart at appropriate times during debugging or the like, and to compare them with each other. It is possible.

FIG. 1 further including application instructions and registers
7 using a program example as shown in FIG.
A method for obtaining a display screen on which the operation state of each circuit element can be confirmed in time series on a ladder diagram will be described.

In FIG. 17, when one of the input devices 81 (address 00020) and 83a (address 00030) is turned on, the relay 82 (address 00010) and the relay contact 82a (address 00010) are turned on, and the output device 84 (address 000000) is turned on. ) Turns on.
At this time, when the relay contact 82a changes from off to on, the application instruction “INC” is executed. Also, the input device 83a
When (address 00010) is turned on from off, the applied instructions “XFER” and “DEC” are executed.

The application instruction “INC” increases (increments) the value of the register 86 (address 09100) by “1”.
The application instruction “XFER” is an instruction for performing a transfer from the first argument register 88 (address 09100) to the second argument register 89 (address 09200), and the application instruction “DEC” is a register. This is an instruction to decrease (decrement) the value of 91 (address 09000) by “1”.

When the bit information or the register information changes at the timing shown in FIG. 18 during such a program execution, tables as shown in FIGS. 19 and 20 are created. FIG. 19 separately shows bit information (a) and register information (b) by adding a table number t and a time series number m to the operation progress as shown in FIG. When fetching the time-series data, it is possible to retrieve the address s by retrieval. However, it is preferable to add the table number t and retrieve the table number t to retrieve the time-series data to retrieve consecutive numbers. This is desirable because the search time is reduced.

FIG. 20 compares the program addresses n and s of the circuit elements and registers in the ladder diagram 80 with the table number t. By extracting the time-series data with reference to these tables, a display screen for displaying the operation states of the programs in a time-series manner as shown in FIG. 21 is obtained by a trigger input from the user. (A) and (b) in FIG. 21 show the case where the time series number m = 0 and m = 5.
This is a display example at the time of, and the numerical value in parentheses in the figure represents the program address. FIG. 22 shows a flowchart for obtaining FIG.

First, the program address n is set to the first value (610). Next, the program address n is
If it is not a circuit element or a register, the program address n is set to the next value (620 to 630). Next, the table number t corresponding to the program address n is read (640). Next, the address s corresponding to the program address n and the table number t are registered (650), and the process is repeated until the program address n becomes the last number (660), thereby obtaining a table as shown in FIG.

Next, the time series number m is set to 0, and the program address n is set to the first value in FIG. 20 (710). Next, the value of the circuit element or the register of the table number t corresponding to the program address n is read from FIG. 19 according to the time series number m (720). Next, the state of the circuit element at the program address n or the contents of the register is displayed on the ladder diagram 80 (730), and the process is repeated until the program address n reaches the last number to obtain a ladder diagram 80 'as shown in FIG. (740-750).

Next, the program address n is set to the first value in FIG. 20 (760), until the time series number m reaches the end (770), or until the display end command is input by the user (780). The time series number m is sequentially increased by the trigger input (790) from the user during the period (800), and the state of the circuit element of the program address n or the contents of the register is ladder diagram 80 in the same manner as described above.
By displaying it on the top, it can be displayed in chronological order.

As described above, the state of the circuit element or the contents of the register at the time of program execution, which is stored in advance in time series, is extracted at an arbitrary timing by the user's trigger, and is sequentially displayed together with the ladder diagram. Since it is possible to judge the execution progress of the program while visually checking the relationship between each circuit element and register, it is possible to easily perform operations such as debugging.

[0073]

According to the first aspect of the present invention, an alarm is issued when an abnormal value is stored in the address specified by the pointer by creating and inserting a monitoring program according to the contents input on the input screen. It is also possible to stop the program and prevent destruction of important data and runaway of the program.

According to the second aspect of the present invention, a display format can be selected and created, and a monitoring program unrelated to a design circuit can be prevented from being displayed on a display screen as needed.

According to the third aspect of the present invention, when a program that repeats a similar program is used, work can be performed collectively when the program program is created / changed, and the program creation / change can be performed.
It is possible to prevent mistakes such as omission of description or omission of correction at the time of change, and to prevent the execution speed from decreasing at the time of program execution.

According to the fourth aspect of the present invention, since the entire developed program can be displayed at the time of executing the program, the state of each circuit element and register at the time of executing the program can be grasped on the ladder diagram, so that the state of the equipment operation can be easily understood. Debugging and the like can be facilitated.

According to the fifth aspect of the present invention, the memory contents indicating the states of the circuit elements or the contents of the registers stored in a time series in advance when the program is executed are taken out at an arbitrary timing by a user's trigger and sequentially displayed together with the ladder diagram. By doing so, the user can determine the execution progress of the program while visually checking the relationship between each circuit element and register, so that work such as debugging can be facilitated.

[Brief description of the drawings]

FIG. 1 is a ladder diagram showing an example of a program.

FIG. 2 is a diagram illustrating the operation of a program.

FIG. 3 is a ladder diagram showing an example of a program in which a similar program is repeated.

FIG. 4 is a time chart showing an example of an execution state of a program.

FIG. 5 is a diagram showing an input screen of a condition for creating a monitoring program.

FIG. 6 is a ladder diagram showing a program to which a monitoring program created according to the present invention is added.

FIG. 7 is a ladder diagram showing a program for performing an alarm.

FIG. 8 is a flowchart illustrating a procedure for creating a monitoring program.

FIG. 9 is a flowchart illustrating a procedure for preventing a monitoring program from being displayed.

FIG. 10 is a diagram showing a relationship between a program controller and a programming device.

FIG. 11 is a diagram showing an input screen for conditions for repeating a similar program.

FIG. 12 is a ladder diagram showing a program created by the present invention.

FIG. 13 is a ladder diagram displayed when modifying a program created by the present invention.

FIG. 14 is a flowchart showing a procedure for creating a display screen displayed when modifying a program.

FIG. 15 is a diagram showing a conventional program display screen.

FIG. 16 is a diagram showing an example of a program display screen of the present invention.

FIG. 17 is a ladder diagram showing an example of a program.

FIG. 18 is a diagram showing a state in which each circuit element and register change in a time series.

FIG. 19 is a diagram showing a table created to obtain a display screen of the present invention.

FIG. 20 is a diagram showing a table created to obtain a display screen of the present invention.

FIG. 21 is a diagram showing an example of a program display screen of the present invention.

FIG. 22 is a flowchart showing a procedure for obtaining a display screen according to the present invention.

[Explanation of symbols]

 6, 47 Input screen 43 Personal computer 44 Program creation device 45 Interface 46 Programmable controller

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Nakamura 4-133 Atobe-Honcho, Yao-shi, Osaka Sharp Manufacturing System Co., Ltd. (72) Inventor Shunsuke Nagasawa Atobe-Honcho, Yao-shi, Osaka 4-1-1-3 Sharp Manufacturing System Co., Ltd.

Claims (5)

[Claims] A means for designating an access range in which an address indirectly specified by an indirectly specifiable instruction can access, and stopping or warning of a program in accordance with a result of comparison between the address and the access range A program creation device, wherein a monitoring program for outputting a program is added so as to be executed before the instruction. 2. The program creating apparatus according to claim 1, further comprising means for not displaying only the monitoring program. 3. When creating a program in which a similar program having circuit elements and registers is repeated a plurality of times, a first reference program, the number of duplications for duplicating the first program, and the first program Means for designating a change rule for changing circuit elements and registers for each copy program obtained by copying the program;
Means for creating the second program by duplicating the program in the number of times of copying and changing circuit elements and registers in accordance with the change rule, and deriving the first program, the change rule, and the number of copies Means for recording information in a third program, when displaying a program including the second and third programs,
Means for reproducing the first program and the change rule from the first program, and first display means for displaying the first program, the change rule, and the number of copies. Program creation device. 4. The apparatus according to claim 1, further comprising second display means for displaying said second program, wherein said first display means and said second display means can be switched and displayed. 4. The program creation device according to 3. 5. A storage device for storing the contents of a memory in a time-series manner when a program of a programmable controller is executed, and sequentially extracting the contents of the memory from the storage means in a time-series at an arbitrary timing. A program monitor device for displaying the status of a register and a register together with a ladder diagram.