JPH11205099A - Pn code generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PN code (pseudo-noise code) generating circuit where an initial value setting is not required. SOLUTION: One of data of the frontmost stage D1 of an n-number stage shift register 50 or data of the third stage D3 is selected by a selector circuit 1, and an exclusive OR operation is executed in an adder 2 concerning the selected data and data of a last stage Dn. The result is inputted to the frontmost stage D1, and a PN code word is outputted from the last stage Dn. The result of the exclusive OR operation is also inputted to a PN code cycle detecting circuit 3, and a PN code cycle signal 14 is outputted to FF(flip-flop) 4, when '1' is continuously inputted with n-bit. FF 4 outputs a selecting signal 15' to the selector circuit 1 with this timing and the selector circuit 1 selects input data. Two PN code lengths are set to 2<n> -1. The initial value setting circuit is not required, since initial synchronization is obtained by continuous '1' and also the two PN code lengths are equal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a PN (Pseudo).
More particularly, the present invention relates to a PN code generation circuit that is used in a spread spectrum communication apparatus and that switches and outputs two or more different PN code words.

[0002]

2. Description of the Related Art An example of this type of PN code generating circuit is disclosed in Japanese Patent Application Laid-Open No. 63-84220. This PN
The code generation circuit includes a common shift register for generating two types of PN code words, two adders for generating respective code words, and an initial value setting circuit.

An outline of this circuit will be described. FIG. 4 is a configuration diagram of a PN code generation circuit described in Japanese Patent Application Laid-Open No. 63-84220.

The PN described in JP-A-63-84220 is disclosed.
The code generation circuit includes an n-stage shift register (n is an integer of 3 or more) 50, adders 51 and 52, a selector 53, an initial value setting circuit 54, a PN code cycle detection circuit 55, and a flip-flop (FF) ) 56.

In this circuit, an n-stage shift register 5
The output of the D1 stage and the output of the Dn stage of 0 are added by the adder 52, and the output of the D3 stage and the output of the Dn stage are added by the adder 51. One of the outputs of the adders 51 and 52 is added. Is selected by the selector 53.

The output of the selector 53 is input to the D1 stage of the n-stage shift register 50.

Thus, each time a clock is input to the n-stage shift register 50, a PN code word is output from the Dn stage.

In this circuit, since two types of PN code words are provided, one of them is selected by the selector 53.

A PN code cycle is detected by a PN code cycle detection circuit 55 from a PN code word output from the Dn stage of the n-stage shift register 50, and a predetermined PN code word is selected by a selector 53 via a flip-flop 56. Let it.

Then, the PN code cycle detection circuit 55
At the timing when the code cycle is detected, the n-stage shift register 5
An initial value setting circuit 54 is provided for setting 0 to an initial value.

The initial value setting circuit 54 is provided for adjusting the phase of the PN code when switching the PN code word.

That is, since the n-stage shift register 50 is shared and the PN code word is switched based on the arrangement of the bits of the last stage Dn of the n-stage shift register 50,
The timing at which the initial data (contents of D1 to Dn) of one PN code word is generated does not necessarily coincide with the timing at which the initial data (contents of D1 to Dn) of the other PN code word is generated. This is partly due to the fact that the code lengths of the PN code words (word lengths indicating the repetition periods of the PN code words) are different from each other.

For this reason, the initial value setting circuit 54 is required.

[0014]

As described above, Japanese Patent Application Laid-Open No.
The PN code generation circuit described in Japanese Patent Application Laid-Open No. 3-84220 requires the initial value setting circuit 54, and has a disadvantage that the circuit scale becomes large.

An object of the present invention is to provide a PN code generation circuit which does not require an initial value setting circuit.

[0016]

In order to solve the above-mentioned problems, the present invention provides an n-bit (n is an integer of 3 or more) shift register, and an output value of a first predetermined stage and a second predetermined stage of the register. Selecting means for selecting any one of them, and arithmetic means for performing a logical operation on the output value selected by the selecting means and the output value of the last stage of the register and inputting the result to the foremost stage of the register; Performs selection when the bit string output from the arithmetic means is in a predetermined sequence, and the first and second predetermined stages are arranged such that the code lengths of the PN codes output from the last stage are equal to each other. It is characterized by being selected.

According to the present invention, the code lengths of the PN codes are set to be equal to each other, and when the bit sequence of the logical operation result between the output of the first and second predetermined stages and the output of the last stage is in a predetermined sequence. Is switched to a predetermined codeword.

When the predetermined arrangement is made, the leading data of the PN code words are output from the n-bit shift register, respectively, and the code lengths of the two PN code words are set to be equal to each other. Word phases can be matched.

[0019]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a first embodiment of a PN code generation circuit according to the present invention. The same components as those in the conventional example (FIG. 4) are denoted by the same reference numerals, and description thereof will be omitted.

The PN code generation circuit according to the present invention comprises an n-stage shift register (n is an integer of 3 or more) 50, a selector circuit 1, an EXOR (exclusive OR) adder 2,
It comprises a code cycle detection circuit 3 and a flip-flop (FF) 4.

The difference between this PN code generation circuit and the prior art is that the PN code period detection circuit 3 sets the PN code word selection timing based on the bit string output from the EX / OR adder 2. And secondly two P
That is, the code lengths of the N code words are set equal.

To make the code lengths of the two PN code words equal, the number of stages n of the n-stage shift register 50 and the first and second stages
The steps may be selected appropriately. At this time, the maximum code length 2 ⁿ -1 is obtained as the code length. The reason why the value is "-1" will be described later.

For example, the number of stages is n = 7, and the first stage is the first stage D
1, the code length of two PN codewords can be made equal by setting the second stage to D3, which is two stages ahead of the foremost stage D1.

In the present invention, when the PN code word is switched, the value of the n-stage shift register 50 is all logic "1" when the PN code generation circuit is constituted by positive logic.
The timing is limited to when it is "".

That is, the initial setting value of the n-stage shift register 50 for the two PN code words is set to a common value "1".

As a result, the timings at which the initial set values are set can be matched. That is, if all the n-stage shift registers 50 are set to "1", they become the initial setting values of one PN code word and the other PN code words.

When the PN code generation circuit is configured by negative logic, the switching is limited to the timing when all logics are "0".

The positive logic and the negative logic of the PN code generation circuit will be described.
This is a PN code generation circuit that prohibits all the values of the stage shift register 50 from becoming “0”.

If all bits are "0", the n-stage shift register 5
This is because the content of 0 always becomes "0" even if shifted, and a desired PN code cannot be obtained. For this reason, as described above, the maximum code length is set to a value obtained by subtracting “−1” from 2 ⁿ .

On the other hand, the negative logic PN code circuit is a PN code generation circuit in which all the values of the n-stage shift register 50 are inhibited from becoming "1". This is because if the value is all "1", the contents of the n-stage shift register 50 are always "1" even if the contents are shifted, and the PN code cannot be obtained.

Next, the operation of the first embodiment will be described. The case where the PN code generation circuit operates in positive logic will be described. The description of the negative logic is omitted, but can be described in the same manner as the case of the positive logic.

The n-stage shift register 50 sequentially converts the binary data input to the first stage D1 into D2 to D in accordance with the clock input.
n, and the PN code is output from the last stage Dn.

An n-stage shift register 5 is connected to the selector circuit 1.
Data 11 of the first stage D1 and data 12 of the third stage D3
Is entered.

When the selector circuit 1 selects the data 11, the EX / OR adder 2 outputs the data 11 and n.
The exclusive OR operation is performed on the data 13 of the last stage Dn of the stage shift register 50.

That is, the input of the EX / OR adder 2 is "1".
"1" is output if "0" and "0", and both are "1".
In the case of “0”, “0” is output.

The result added by the EX / OR adder 2 is input to the first stage D 1 of the n-stage shift register 50.

Each time a clock is input, EX
This operation is performed by the OR adder 2, and as a result, a PN code word having a code length of 2 ⁿ -1 is output from the last stage Dn. This PN code word is represented by (n, 1).

On the other hand, when the selector circuit 1 selects the data 12, the PN code word output from the last stage Dn of the n-stage shift register 50 is represented by (n, 3). This code also has a code length of 2 ⁿ -1.

Now, the PN code cycle detecting circuit 3 is EX · O
The output of the R adder 2 is monitored, and the EX / OR adder 2
When "1" is output continuously for n more bits, the PN code cycle clock 14 is output in synchronization with the clock input timing.

On the other hand, the flip-flop 4 outputs the PN selection signal 15 at the timing when the PN code cycle clock 13 is input.
To the selector circuit 1 as a selection signal 15 '.

The selector circuit 1 selects a signal according to the selection signal 15 '.

It is assumed that data 11 is selected by the selector circuit 1. At this time, the n-stage shift register 5
The PN code word (n, 1) is output from the last stage Dn of 0.

The PN code cycle detection circuit 3 outputs a PN code cycle clock 14 to the flip-flop 4 when "1" is output continuously from the EX / OR adder 2 for n bits.

The flip-flop 4 receiving the PN code cycle clock 14 outputs a PN selection signal 15 ′ to the selector circuit 1.

The selector circuit 1 receiving the PN selection signal 15 'switches the selection signal from data 11 to data 12.

At this time, of course, "1" is set in all stages in the n-bit shift register. Therefore,
Dn outputs PN codewords (n, 3) in order from the first bit.

When the EX / OR adder 2 outputs “1” continuously for n bits again, and when the PN code cycle detection circuit 3 detects this, the selector circuit 1 changes the selection signal from data 12 to data 11. Switch. Therefore, the PN codeword (n, 1) is output from Dn in order from the first bit.

As described above, since the PN code word is sequentially output from the first bit at the time of PN code switching,
The PN codeword is output from the intermediate bits, and
It is possible to prevent a PN code word shorter than the code length from being output.

This eliminates the need for an initial value setting circuit.

Further, by making the code lengths of PN equal, even if there are two or more PN code words, EX · OR
The adder 2 can be composed of one circuit, and in this regard, the circuit scale can be made smaller than in the conventional case.

Next, a second embodiment will be described. FIG. 2 is a configuration diagram of the second embodiment. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the second embodiment, two PN code words are added to provide four types. In the second embodiment,
In addition to (n, 1) and (n, 3), the PN codeword is (n,
4) and (n, 6) are added.

That is, the first stage D of the n-stage shift register 50
The data 11 of the first stage, the data 12 of the third stage D3, the data 16 of the fourth stage D4, and the data 17 of the sixth stage D6 are input to the selector circuit 31.

On the other hand, two types of PN selection signals 21 and 22 are input to the flip-flop 34. The PN selection signals 21 and 22 form a 2-bit code, and a total of four types of selection signals are input to the flip-flop 34.

The four types of selection signals are input to the selector circuit 1.

The selector circuit 1 selects one of the data 11, 12, 16, and 17 according to the selection signal and outputs the selected signal to the EX / OR adder 2.

The EX / OR adder 2 performs an exclusive OR operation on one of the input data 11, 12, 16, and 17 and the data 13 of the last stage Dn of the n-stage shift register 50. The result is output.

The result is input to the first stage Dn of the n-stage shift register 50. Then, a PN code word is output from the last stage Dn.

As described above, as a result of adding two PN codes, the flip-flop 34 increases by one flip-flop, and furthermore, the selector circuit 3
Although it is necessary to increase the scale of the selector circuit 31 due to the addition of two signals output to 1, the other circuits can enable switching of four types of PN codewords without being changed. .

Next, a third embodiment will be described. FIG. 3 is a configuration diagram of the third embodiment.

In the third embodiment, the PN code generating circuit is used for a spread spectrum type transmitter.

Referring to FIG. 3, the transmitter of the spread spectrum system uses PSK (Phase Shift) to transmit data.
Keying) modulated primary modulator 41 and PN code generation circuit 42 described in the first and second embodiments.
And an integrator 43 for integrating the output of the primary modulator 41 and the output of the PN code generation circuit 42, and a transmitting antenna 44.

The transmission data is a binary signal, and one period of P data is transmitted at a time equivalent to transmitting one bit of the transmission data.
The code length of the PN code is set so that the N code can be accommodated.

Therefore, the transmission data is transmitted by the primary modulator 41 to P
After the SK modulation, the integrator 43 further modulates the PN code output from the PN code generation circuit 41 with the PN code, and outputs a spread spectrum wave from the transmission antenna 44.

[0065]

According to the present invention, an n-bit (n is an integer of 3 or more) shift register, and a selection means for selecting any one of the output values of the first and second predetermined stages of the register, Operating means for performing a logical operation on the output value selected by the selecting means and the output value of the last stage of the register and inputting the result to the foremost stage of the register, wherein the selecting means comprises a bit string output from the operating means Are selected when a predetermined sequence is established, and the first and second predetermined stages are selected such that the code lengths of the PN codes output from the last stage are equal to each other. Becomes unnecessary. Thereby, the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a PN code generation circuit according to the present invention.

FIG. 2 is a configuration diagram of a second embodiment of the circuit.

FIG. 3 is a configuration diagram of a third embodiment of the circuit.

FIG. 4 is a configuration diagram of a PN code generation circuit described in JP-A-63-84220.

[Explanation of symbols]

 1, 31 selector circuit 2 EX / OR adder 3 PN code cycle detection circuit 4, 34 flip-flop 41 primary modulator 42 PN code generation circuit 43 integrator 50 n-stage shift register

Claims (6)

[Claims] 1. An n-bit (n is an integer of 3 or more) shift register, selection means for selecting one of output values of a first predetermined stage and a second predetermined stage of the register, Operating means for performing a logical operation on the output value of the register and the output value of the last stage of the register and inputting the result to the foremost stage of the register, wherein the selecting means has a predetermined sequence of bit strings output from the operating means. The first and second predetermined stages are PN output from the last stage.
A PN code generation circuit, wherein the stages are selected such that the code lengths of the codes are equal to each other. 2. The PN code generation circuit according to claim 1, wherein said operation means is an exclusive OR circuit. 3. The exclusive OR circuit is configured by positive logic, and the selecting means performs selection when n bits output from the arithmetic means are "1" continuously. Item 3. A PN code generation circuit according to Item 2. 4. The PN code generating circuit according to claim 1, wherein the code length of said PN code is 2 ⁿ -1. 5. The PN code generating circuit according to claim 1, wherein said selecting means selects any one of three or more output values of said register. 6. The P according to claim 1, which is used for a transmitter of a spread spectrum system.
N code generation circuit.