JPH11205013A - Impedance matching device - Google Patents

Impedance matching device

Info

Publication number
JPH11205013A
JPH11205013A JP10008330A JP833098A JPH11205013A JP H11205013 A JPH11205013 A JP H11205013A JP 10008330 A JP10008330 A JP 10008330A JP 833098 A JP833098 A JP 833098A JP H11205013 A JPH11205013 A JP H11205013A
Authority
JP
Japan
Prior art keywords
substrate
conductor pattern
impedance matching
matching device
impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10008330A
Other languages
Japanese (ja)
Inventor
Akio Seki
昭男 関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Original Assignee
Fujitsu General Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd filed Critical Fujitsu General Ltd
Priority to JP10008330A priority Critical patent/JPH11205013A/en
Publication of JPH11205013A publication Critical patent/JPH11205013A/en
Pending legal-status Critical Current

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  • Waveguides (AREA)

Abstract

PROBLEM TO BE SOLVED: To match with the impedance of the input/output pin of IC of a small pin interval by lowering the impedance, when the conductor pattern width of a substrate is limited. SOLUTION: A conductor (ground) pattern 7 on the lower surface of the part of IC4 of the substrate 1 of a glass resin, etc., is removed, and this part is fitted to a housing 8 by inserting the substrate consisting of ceramic, etc. A substrate 10 is removed of a part corresponding to an IC4 of a conductor pattern 11 on its top surface. Thereby, the dielectric constant is increased by the total sum of the substrates 1 and 10, so that the impedance of conductor patterns 2 and 3 can be lowered, to match with the input/output impedance of IC4 even if the widths of the patterns 2 and 3 to be connected are small.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はインピーダンス整合
装置に係り、高周波回路のIC(集積回路)を基板に取
付ける場合に基板の導体パターンのインピーダンスをI
Cの入・出力インピーダンスに整合させるものに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an impedance matching device, and more particularly to an impedance matching device for mounting an IC (integrated circuit) of a high-frequency circuit on a substrate.
It relates to matching the input and output impedance of C.

【0002】[0002]

【従来の技術】衛星放送(BS)あるいは通信衛星(C
S)のコンバータ回路等では、プリント基板に機械的強
度およびコストの面から主にガラス樹脂系の材料を使用
し、回路をIC化して小型化したものが主流である。図
4は従来の高周波回路装置の一例の側断面図で、第1基
板1上にIC4を配設し筐体8に取付けたもので、2は
入力側の導体パターン、3は出力側の導体パターン、5
はIC4の入力ピン、6は出力ピンである。IC4の入
・出力インピーダンスは、例えば、それぞれ50オーム
で、信号損失を最小にするにはインピーダンスの整合が
必要で、導体パターン2、3を共に50オームにすること
が望ましい。しかし、IC4は小型化のためピン間のピ
ッチが狭く、自ずと導体パターン2、3の幅が制限さ
れ、結果としてインピーダンスは50オームより高くな
り、インピーダンスの整合がとれない。導体パターンの
インピーダンスは基板の厚みと基板の比誘電率に大きく
影響され、インピーダンスを下げるには板厚が薄くて比
誘電率の高い基板を用いればよいが、基板を薄くするの
は機械的強度等からの制限があり、比誘電率の高いセラ
ミック基板(比誘電率約10、ガラス樹脂系では約3.5 )
等はコストが高い。
2. Description of the Related Art Satellite broadcasting (BS) or communication satellite (C)
In the converter circuit and the like in S), a glass circuit material is mainly used for a printed circuit board in terms of mechanical strength and cost, and the circuit is formed into an IC to reduce the size. FIG. 4 is a side sectional view of an example of a conventional high-frequency circuit device, in which an IC 4 is disposed on a first substrate 1 and attached to a housing 8. Reference numeral 2 denotes an input-side conductor pattern, and reference numeral 3 denotes an output-side conductor. Pattern, 5
Is an input pin of the IC 4, and 6 is an output pin. The input and output impedances of the IC 4 are, for example, 50 ohms, respectively. In order to minimize the signal loss, impedance matching is required, and it is desirable that the conductor patterns 2, 3 are both 50 ohms. However, the IC 4 has a small pitch between pins for miniaturization and naturally limits the width of the conductor patterns 2 and 3, and as a result, the impedance becomes higher than 50 ohms and the impedance cannot be matched. The impedance of the conductor pattern is greatly affected by the thickness of the board and the relative permittivity of the board. To reduce the impedance, a board with a small thickness and a high relative permittivity can be used, but the thinning of the board requires mechanical strength. Ceramic substrate with high relative dielectric constant (specific dielectric constant of about 10, about 3.5 for glass resin)
Etc. are expensive.

【0003】[0003]

【発明が解決しようとする課題】本発明はこのような点
に鑑み、ガラス樹脂系等の基板の所要部分に比誘電率の
高い基板を併用し、比較的低コストでインピーダンスを
整合させることを目的とする。
SUMMARY OF THE INVENTION In view of the foregoing, the present invention has been made to use a substrate having a high relative dielectric constant in combination with a required portion of a substrate made of a glass resin or the like so as to achieve impedance matching at relatively low cost. Aim.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するた
め、本発明のインピーダンス整合装置においては、マイ
クロ波帯の信号処理回路を第1基板に配設し、第1基板
の信号処理回路部分の下面の導体パターンを除去し、当
該箇所に第1基板より比誘電率の高い第2基板を取付
け、金属製の筐体面に取付けて構成する。
In order to achieve the above object, in the impedance matching device of the present invention, a microwave signal processing circuit is provided on a first substrate, and a signal processing circuit portion of the first substrate is provided. The conductor pattern on the lower surface is removed, a second substrate having a higher dielectric constant than the first substrate is attached to the portion, and the second substrate is attached to a metal housing surface.

【0005】または、前記第1基板の信号処理回路の入
力端子部分および出力端子部分の下面の導体パターンを
除去し、これらの箇所に第1基板より比誘電率の高い第
3基板をそれぞれ取付け、金属製の筐体面に取付けるよ
うにする。
Alternatively, the conductor patterns on the lower surfaces of the input terminal portion and the output terminal portion of the signal processing circuit of the first substrate are removed, and a third substrate having a higher relative dielectric constant than the first substrate is attached to these locations. Attach it to the metal housing surface.

【0006】なお、第2基板または第3基板は、上面お
よび下面に共に導体パターンを有しないものとするか、
下面に導体パターンを有し、上面に導体パターンを有し
ないものとするか、または、下面に導体パターンを有
し、上面の第1基板の導体パターン除去部分に対応する
部分の導体パターンを除去したものとする。
The second substrate or the third substrate has no conductor pattern on both the upper and lower surfaces.
Either a conductor pattern is provided on the lower surface and no conductor pattern is provided on the upper surface, or a conductor pattern is provided on the lower surface and the conductor pattern of a portion corresponding to the conductor pattern removed portion of the first substrate on the upper surface is removed. Shall be.

【0007】そして、第2基板または第3基板の上面の
導体パターン部分を導電性接着剤で第1基板の導体パタ
ーン部分に接着するか、または、第2基板または第3基
板の下面の導体パターン部分を導電性接着剤で筐体面に
接着するようにする。
[0007] The conductive pattern portion on the upper surface of the second substrate or the third substrate is bonded to the conductive pattern portion of the first substrate with a conductive adhesive, or the conductive pattern portion on the lower surface of the second substrate or the third substrate. The part is adhered to the housing surface with a conductive adhesive.

【0008】また、前記筐体面に、第2基板または第3
基板の形状に対応する凹部を形成し、この凹部に第2基
板または第3基板を埋着し、各基板の下面が筐体面に密
着するようにする。
Further, a second substrate or a third substrate is provided on the housing surface.
A concave portion corresponding to the shape of the substrate is formed, and the second substrate or the third substrate is embedded in the concave portion so that the lower surface of each substrate is in close contact with the housing surface.

【0009】あるいは、第1基板の下面を第2基板また
は第3基板の形状に対応させて切削し、第2基板または
第3基板を嵌着し、第1基板に密着させるようにする。
Alternatively, the lower surface of the first substrate is cut in accordance with the shape of the second substrate or the third substrate, the second substrate or the third substrate is fitted, and is brought into close contact with the first substrate.

【0010】[0010]

【発明の実施の形態】発明の実施の形態を実施例に基づ
き図面を参照して説明する。図1は本発明によるインピ
ーダンス整合装置の一実施例の要部構成図で、(イ)は
上面図、(ロ)は側断面図、(ハ)は第1基板1の下面
図である。図において、1はガラス樹脂系(比誘電率約
3.5 )等の第1基板で、2は入力側導体パターン、3は
出力側導体パターンである。4はマイクロ波帯の信号処
理回路のICで、5は信号入力ピン、6は信号出力ピン
で、入・出力インピーダンスは、例えば、共に50オーム
である。7は第1基板1の下面の導体パターンである。
8は金属製の筐体、9は基板1を筐体8に取付けるネジ
である。10はセラミック基板(比誘電率約10)等の第2
基板で、11は上面の導体パターン、12は下面の導体パタ
ーンである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. 1A and 1B are main part configuration diagrams of an embodiment of the impedance matching device according to the present invention, wherein FIG. 1A is a top view, FIG. 1B is a side sectional view, and FIG. 1C is a bottom view of the first substrate 1. In the figure, reference numeral 1 denotes a glass-resin-based material (with a relative dielectric constant of about
3.5), etc., 2 is an input side conductor pattern, and 3 is an output side conductor pattern. Reference numeral 4 denotes an IC of a microwave band signal processing circuit, reference numeral 5 denotes a signal input pin, reference numeral 6 denotes a signal output pin, and the input / output impedance is, for example, 50 ohms. Reference numeral 7 denotes a conductor pattern on the lower surface of the first substrate 1.
Reference numeral 8 denotes a metal housing, and 9 denotes screws for attaching the substrate 1 to the housing 8. 10 is the second such as ceramic substrate (relative permittivity about 10)
Reference numeral 11 denotes a conductor pattern on the upper surface, and 12 denotes a conductor pattern on the lower surface.

【0011】第1基板1は、IC4(図1・ハに点線で
示す)に対応する部分の下面の導体パターン(接地パタ
ーン)7を除去し、第2基板10は、例えば、図2に示す
ようにIC4の幅に相当するAの部分の導体パターンを
除去し、下面の導体パターン(接地パターン)12は残
し、第1基板1を第2基板10を挟んで筐体8に取付け
る。これにより、IC4の入・出力ピン5、6を接続す
る部分の導体パターン2、3は導体パターン12との間に
基板1(比誘電率約3.5 )と基板10(比誘電率約10)と
が重なって入るので総合で第1基板1より高い比誘電率
となり、導体パターン2、3のインピーダンスが下が
り、IC4の入・出力インピーダンスと整合し易くな
る。
The first substrate 1 is formed by removing the conductor pattern (ground pattern) 7 on the lower surface of a portion corresponding to the IC 4 (shown by a dotted line in FIG. 1C), and the second substrate 10 is, for example, shown in FIG. Thus, the conductor pattern of the portion A corresponding to the width of the IC 4 is removed, and the conductor pattern (ground pattern) 12 on the lower surface is left, and the first substrate 1 is mounted on the housing 8 with the second substrate 10 interposed therebetween. As a result, the conductor patterns 2 and 3 of the portion connecting the input / output pins 5 and 6 of the IC 4 are located between the conductor pattern 12 and the substrate 1 (relative permittivity of about 3.5) and the substrate 10 (relative permittivity of about 10). Overlap, the relative dielectric constant becomes higher than that of the first substrate 1 as a whole, the impedance of the conductor patterns 2 and 3 decreases, and it becomes easy to match with the input / output impedance of the IC 4.

【0012】なお、第1基板1の下面の第2基板10の取
付箇所を第2基板10の形状に合わせて切削し、ここに第
2基板10を嵌着して取付け易くしてもよく、あるいは、
筐体8に第2基板10の形状に合わせて凹部を形成し、こ
の凹部に第2基板10を埋着して位置決めし易くしてもよ
い。なお、取付けの際、第2基板10の上面の導体パター
ン11の部分を導電性接着剤で第1基板1に接着してもよ
く、あるいは、第2基板10の下面の導体パターン12を導
電性接着剤で筐体8に接着してもよい。導体パターンを
導電性接着剤で接着することにより確実な導電効果が得
られる。
The mounting position of the second substrate 10 on the lower surface of the first substrate 1 may be cut in accordance with the shape of the second substrate 10, and the second substrate 10 may be fitted to the second substrate 10 for easy mounting. Or,
A recess may be formed in the housing 8 according to the shape of the second substrate 10, and the second substrate 10 may be embedded in the recess to facilitate positioning. At the time of attachment, the conductive pattern 11 on the upper surface of the second substrate 10 may be bonded to the first substrate 1 with a conductive adhesive, or the conductive pattern 12 on the lower surface of the second substrate 10 may be electrically conductive. It may be adhered to the housing 8 with an adhesive. By bonding the conductive pattern with a conductive adhesive, a reliable conductive effect can be obtained.

【0013】上記では、第2基板10は上下両面に導体パ
ターン(接地パターン)を有するもので説明したが、上
面に導体パターンのないもの、あるいは上下両面共に導
体パターンのないものを用いてもよい。これは、第2基
板10の上面に導体パターン11がなくても第1基板1の下
面の導体パターン7がこの役目を兼ねるからであり、ま
た、第2基板10の下面に導体パターン12がなくても筐体
8がこの役目をするからで、導体パターンのあるものに
比べてコストを低減できる。但し、導体パターン11ある
いは導体パターン12のあった方が安定した接地効果が得
られる。
In the above description, the second substrate 10 has been described as having a conductor pattern (ground pattern) on both upper and lower surfaces. However, a substrate having no conductor pattern on the upper surface or a substrate having no conductor pattern on both upper and lower surfaces may be used. . This is because even if there is no conductor pattern 11 on the upper surface of the second substrate 10, the conductor pattern 7 on the lower surface of the first substrate 1 also serves this role, and there is no conductor pattern 12 on the lower surface of the second substrate 10. However, since the housing 8 performs this function, the cost can be reduced as compared with the case having the conductor pattern. However, the presence of the conductor pattern 11 or the conductor pattern 12 provides a stable grounding effect.

【0014】図3は本発明によるインピーダンス整合装
置の他の実施例の要部構成側面図で、第2基板10を2つ
の第3基板21に分割し、IC4の入力ピン5の部分と出
力ピン6の部分とに別々に取付けたもので、比較的高価
なセラミック基板の使用量を節減でき、コストを低減で
きる。なお、第3基板21の上面に導体パターン22のある
もの、ないもの、下面に導体パターン23のあるもの、な
いもの、第1基板1の下面を切削する、筐体8を凹状に
切削する、導体パターンを導電性接着剤で接着する、等
の条件および効果は上記第2基板10の場合と同様であ
り、内容が重複するので説明を省略する。
FIG. 3 is a side view of a main part of another embodiment of the impedance matching device according to the present invention, in which the second substrate 10 is divided into two third substrates 21, and the input pins 5 and the output pins of the IC 4 are separated. Since it is separately attached to the portion 6, the amount of use of a relatively expensive ceramic substrate can be reduced, and the cost can be reduced. In addition, the thing with and without the conductor pattern 22 on the upper surface of the third substrate 21, the thing with and without the conductor pattern 23 on the lower surface, the lower surface of the first substrate 1 is cut, the housing 8 is cut into a concave shape, Conditions and effects such as bonding the conductor pattern with a conductive adhesive are the same as those of the second substrate 10, and the description is omitted because the contents are duplicated.

【0015】[0015]

【発明の効果】以上に説明したように、本発明によるイ
ンピーダンス整合装置によれば、ガラス樹脂系等の比誘
電率の高くない基板の裏面に部分的にセラミック等の比
誘電率の高い基板を重ねることにより総合で比誘電率を
上げ、基板の導体パターンの幅が制限される場合でもイ
ンピーダンスを低くすることができ、ピン間隔の狭いI
C等の入・出力インピーダンスと整合させることができ
る。
As described above, according to the impedance matching device of the present invention, a substrate having a high relative dielectric constant such as ceramic is partially provided on the back surface of a substrate having a low relative dielectric constant such as a glass resin. By overlapping, the relative dielectric constant can be increased as a whole, and the impedance can be reduced even when the width of the conductor pattern of the substrate is limited, and the I-pin having a narrow pin interval can be used.
It can be matched with input / output impedance such as C.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるインピーダンス整合装置の一実施
例の要部構成図である。
FIG. 1 is a main part configuration diagram of an embodiment of an impedance matching device according to the present invention.

【図2】第2基板の一例である。FIG. 2 is an example of a second substrate.

【図3】本発明によるインピーダンス整合装置の他の実
施例の要部構成図である。
FIG. 3 is a main part configuration diagram of another embodiment of the impedance matching device according to the present invention.

【図4】従来の高周波回路装置の一例の要部構成図であ
る。
FIG. 4 is a main part configuration diagram of an example of a conventional high-frequency circuit device.

【符号の説明】[Explanation of symbols]

1 第1基板 2 入力側導体パターン 3 出力側導体パターン 4 IC 5 入力ピン 6 出力ピン 7 第1基板の下面の導体パターン 8 筐体 10 第2基板 11 第2基板の上面の導体パターン 12 第2基板の下面の導体パターン 21 第3基板 22 第3基板の上面の導体パターン 23 第3基板の下面の導体パターン DESCRIPTION OF SYMBOLS 1 1st board | substrate 2 input side conductor pattern 3 output side conductor pattern 4 IC5 input pin 6 output pin 7 conductor pattern on the lower surface of a 1st board 8 housing | casing 10 2nd board | substrate 11 conductor pattern on the upper surface of a 2nd board 12 second Conductor pattern on lower surface of substrate 21 Third substrate 22 Conductor pattern on upper surface of third substrate 23 Conductor pattern on lower surface of third substrate

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 マイクロ波帯の信号処理回路を第1基板
に配設し、金属製の筐体面に取付けたものにおいて、前
記第1基板の信号処理回路部分の下面の導体パターンを
除去し、当該箇所に第1基板より比誘電率の高い第2基
板を取付けてなるインピーダンス整合装置。
1. A signal processing circuit having a microwave band disposed on a first substrate and attached to a metal housing surface, wherein a conductor pattern on a lower surface of a signal processing circuit portion of the first substrate is removed. An impedance matching device in which a second substrate having a higher dielectric constant than the first substrate is attached to the location.
【請求項2】 マイクロ波帯の信号処理回路を第1基板
に配設し、金属製の筐体面に取付けたものにおいて、前
記第1基板の信号処理回路の入力端子部分および出力端
子部分の下面の導体パターンを除去し、当該箇所にそれ
ぞれ第1基板より比誘電率の高い第3基板を取付けてな
るインピーダンス整合装置。
2. A signal processing circuit in a microwave band disposed on a first substrate and attached to a metal housing surface, wherein the lower surface of an input terminal portion and an output terminal portion of the signal processing circuit on the first substrate. An impedance matching device comprising a third substrate having a higher relative dielectric constant than the first substrate attached to a corresponding portion of the third substrate.
【請求項3】 前記第2基板または第3基板は、上面お
よび下面に共に導体パターンを有しないものでなる請求
項1または2記載のインピーダンス整合装置。
3. The impedance matching device according to claim 1, wherein the second substrate or the third substrate does not have a conductor pattern on both upper and lower surfaces.
【請求項4】 前記第2基板または第3基板は、下面に
導体パターンを有し、上面に導体パターンを有しないも
のでなる請求項1または2記載のインピーダンス整合装
置。
4. The impedance matching device according to claim 1, wherein the second substrate or the third substrate has a conductor pattern on a lower surface and does not have a conductor pattern on an upper surface.
【請求項5】 前記第2基板または第3基板は、下面に
導体パターンを有し、上面の前記第1基板の導体パター
ン除去部分に対応する部分の導体パターンを除去してな
る請求項1または2記載のインピーダンス整合装置。
5. The second substrate or the third substrate has a conductor pattern on a lower surface, and a conductor pattern in a portion corresponding to a conductor pattern removed portion of the first substrate on the upper surface is removed. 3. The impedance matching device according to 2.
【請求項6】 前記第2基板または第3基板の上面の導
体パターン部分を導電性接着剤を用いて前記第1基板の
導体パターン部分に接着するようにした請求項5記載の
インピーダンス整合装置。
6. The impedance matching device according to claim 5, wherein the conductive pattern portion on the upper surface of the second substrate or the third substrate is bonded to the conductive pattern portion of the first substrate using a conductive adhesive.
【請求項7】 前記第2基板または第3基板の下面の導
体パターン部分を導電性接着剤を用いて前記筐体面に接
着するようにした請求項4または5記載のインピーダン
ス整合装置。
7. The impedance matching device according to claim 4, wherein the conductive pattern portion on the lower surface of the second substrate or the third substrate is bonded to the housing surface using a conductive adhesive.
【請求項8】 前記筐体面に前記第2基板または第3基
板の形状に対応する凹部を形成し、該凹部に第2基板ま
たは第3基板を埋着するようにした請求項1、2、3、
4、5、6または7記載のインピーダンス整合装置。
8. A method according to claim 1, wherein a concave portion corresponding to the shape of said second substrate or said third substrate is formed in said housing surface, and said second substrate or said third substrate is embedded in said concave portion. 3,
8. The impedance matching device according to 4, 5, 6, or 7.
【請求項9】 前記第1基板の下面を前記第2基板また
は第3基板の形状に対応させて切削し、第2基板または
第3基板を嵌着するようにした請求項1、2、3、4、
5、6または7記載のインピーダンス整合装置。
9. The method according to claim 1, wherein the lower surface of the first substrate is cut in accordance with the shape of the second substrate or the third substrate, and the second substrate or the third substrate is fitted. 4,
The impedance matching device according to 5, 6, or 7.
JP10008330A 1998-01-20 1998-01-20 Impedance matching device Pending JPH11205013A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10008330A JPH11205013A (en) 1998-01-20 1998-01-20 Impedance matching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10008330A JPH11205013A (en) 1998-01-20 1998-01-20 Impedance matching device

Publications (1)

Publication Number Publication Date
JPH11205013A true JPH11205013A (en) 1999-07-30

Family

ID=11690188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10008330A Pending JPH11205013A (en) 1998-01-20 1998-01-20 Impedance matching device

Country Status (1)

Country Link
JP (1) JPH11205013A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165755A (en) * 2005-12-16 2007-06-28 Matsushita Electric Ind Co Ltd Wiring board and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165755A (en) * 2005-12-16 2007-06-28 Matsushita Electric Ind Co Ltd Wiring board and method for manufacturing the same

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