JPH11196373A - Information processing unit, information processing method and computer readable storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the user to easily grasp an error state of data in a VTR on recording side in dubbing. SOLUTION: Transmission data sent from a transmitter side VTR 101 via an interface 102 and an IEEE 1394 cable 103 are given to a receiver side interface 104, where the data are separated into data D and an error signal err and they are given to a receiver side VTR 105. The data D are processed and recorded by a data decode section 106. The error signal err is counted by an error counter 107 in the unit of frame or field and the count value is displayed on an error display device 108.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to an information processing apparatus, an information processing method, and a computer-readable storage medium.

[0002]

2. Description of the Related Art In recent years, with the development of digital technology, various devices have been developed which are capable of transmitting a data at a relatively low transmission rate by encoding a large amount of data to reduce the amount of data. .

For example, in a digital VTR for recording image data on a recording medium such as a magnetic tape, a 124M
Input image data of about bps is reduced to 1/5 of 25Mbps
Standards for recording on a magnetic tape after compression to a certain degree have been established. Digital VT based on such a standard
In R, data compression is performed by subjecting input data to DCT transform, quantizing the data, and subjecting the quantized data to variable-length coding by Huffman coding or the like. further,
The quantization step at the time of quantization is varied based on various parameters, and rate control is performed so that the data amount after variable length encoding becomes constant. The above processing data is subjected to processing for error detection / correction using, for example, a Reed-Solomon code via a memory, to which an inner code and an outer code are added, and recorded on a recording medium such as a magnetic tape. .

In the above digital VTR, the IEEE standard is used.
Digital dubbing using a digital data transfer format (hereinafter referred to as IEEE 1394) established in E is possible. The configuration will be described with reference to FIG. In FIG. 4, reference numeral 200 denotes a digital VTR (hereinafter, DVC) on the transmitting side in digital dubbing.
R1), and digital data that has been rate-controlled so that the data amount after the variable-length encoding is constant becomes a digital interface unit (hereinafter, DIF1).
To be described) 202.

[0005] As shown in FIG.
One block is composed of 80 bytes in which 3 bytes of ID data are added to 7 bytes of valid data. ID0 in FIG.
Is the data type (header, subcode, video AUX,
Indicates either audio or video data) and ID
1 is a track number (NTSC is 0-9, PAL is 0-1)
1), ID2 is assigned a block number. These data are composed of one header block, two subcode blocks, three video AUX blocks, nine audio blocks, and 135 video blocks for each track.

Normally, the DVCR1 (200) on the transmitting side
For example, the above-described block data is sequentially transmitted to the DIF 1202 as six packets (480 bytes) as one packet.
In the transmission side DIF1 (202), communication is performed in a predetermined communication cycle (125 μs), and data having a time axis such as the above header data, subcode data, video AUX data, video data, and audio data are: Iso with guaranteed transfer bandwidth at a fixed data rate
Control data such as a control command is transmitted asynchronously (synchronously).
on (asynchronous) communication.

The packet format of the above isochronous (synchronous) transfer is 1 in total as shown in FIG.
It is composed of 2 + 4 × N bytes. In FIG. 6, a is a length field, which defines the byte length of the data field following the header. b is a channel number field, which gives a logical number to the transfer of packet data using an 8-bit value. The receiving side refers to the channel number and fetches necessary isochronous data. c is a tCode field, which indicates that this packet is an isochronous (synchronous) transfer.

[0008] d is a sy field, which is used by application software. Used to exchange synchronization information between source and destination. e is a header CRC field, and is an error detection code for a, b, c, and d. f is a data field for storing the above isochronous data. g is a data CRC, which is an error detection code of the packet data.

The packetized data is serially transferred to the receiving side using the IEEE 1394 cable 204 shown in FIG. The digital interface unit (hereinafter, referred to as DIF2) 206
After receiving the onous data and performing predetermined processing, the video data and the like are extracted from the data field shown in FIG. 6 and output to a digital VTR (hereinafter, referred to as DVCR2) 208 on the transmission side. And outputs an error signal indicating the presence or absence of. DVCR2
In (208), an error correction code is added to the received data and recorded on the magnetic recording medium. The error signal is detected by an error detection code added in the packet to generate the error signal.

Next, referring to FIG. 7, the DVCR1 (200)
The data transfer on the side will be described. In FIG. 7, 50
Reference numeral 0 denotes a main memory for storing the various data described above, which has a three-bank configuration. A CPU 502 controls the entire system, and controls a bank of each processing block that accesses the main memory 502 based on the supplied vertical synchronization signal.

Reference numeral 504 denotes a switch for switching banks on the writing side, and a bank signal (hereinafter, referred to as a bank signal) from the CPU 502.
W_Bank). Similarly, 5
Reference numeral 06 denotes a read-side bank switching switch, which is switched by a bank signal (hereinafter, referred to as R_Bank) from the CPU 502. Reference numerals 508 and 510 denote frequency divider circuits. In this example, the 13.5 MHz line clock is frequency-divided by 1800 to generate 7.5 KHz (133.3 μs), and then frequency-divided by 2 to generate a frequency of 133.3 μs Generate a signal to be inverted.

Next, the system clock (67.
5 MHz) and the exclusive OR 5
14, both falling and rising edges (hereinafter referred to as Nominal_Timing) of the inverted signal are generated every 133.3 μs. Although not shown, the transmitting side reads one packet worth of data from the main memory every Nominal_Timing, and
Transfer to F1 (202). Here, Nominal_
The reason why the timing period is 133.3 μs is as follows.
According to the standard for transferring data to IF1 (202), 1
This is because it is necessary to transfer 250 packets of data per frame on average.

FIG. 8 is a time chart of the above operation.
a is VD of approximately 30 Hz (33.3 ms period), b is No
minal_Timing, 2 per frame
Generated 50 times. c is a bank signal controlled by the CPU 502, and switches periodically to VD. d is packet data, and there are 250 packets of data per frame. "e" is a packet data error signal indicating presence or absence of an error in the packet data detected from the data CRC for each packet data.

[0014]

In the above conventional example, the DVCR2 (20) is used based on the error information of the packet error signal.
8) In the internal signal processing, processing such as outputting no error data of the previous frame without updating data is performed. However, the user is not notified of the above-described error information, so that there is a problem that the user cannot grasp the error state during dubbing.

[0015]

According to the present invention, there is provided an information processing apparatus, comprising: input means for inputting information data; detecting means for detecting an error in the information data input by the input means; There are provided counting means for counting the number of errors detected by the means at predetermined time intervals, and display means for displaying an error state of the information data based on the count result of the counting means.

According to a tenth aspect of the present invention, in the information processing apparatus, input means for inputting information data, recording means for recording the information data input by the input means on a recording medium, and input means for inputting the information data by the input means Detecting means for detecting an error in the information data; counting means for counting the number of errors detected by the detecting means at predetermined time intervals; and controlling a recording operation of the recording means based on a count result of the counting means. Control means.

In the information processing method according to the present invention, an input step of inputting information data, a detecting step of detecting an error of the input information data, and a method of determining the number of detected errors at predetermined time intervals And a display step of displaying an error state of the information data based on the count result.

In the information processing method according to the nineteenth aspect, an input step of inputting information data, a recording step of recording the input information data on a recording medium, and detecting an error of the input information data And a control step of controlling a recording operation of the recording step based on the count result.

According to a twentieth aspect of the present invention, in a computer-readable storage medium, a detection process for detecting an error in input information data, a count process for counting the number of the detected errors at predetermined time intervals, A display process for displaying an error state of the information data based on the count result.

In a computer-readable storage medium according to the present invention, a recording process for recording input information data on a recording medium, a detection process for detecting an error in the input information data, A program for executing a count process for counting the number of errors performed at predetermined time intervals and a control process for controlling a recording operation in the recording step based on the count result is stored.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a digital V on the data transmission side.
TR (DVCR1), 102 is a transmitting digital interface (DIF1), 103 is an IEEE 1394 cable, 104 is a receiving digital interface (DIF2), 105 is a receiving digital VTR (DVDV).
CR2) and 106 are a data decoding unit, 107 is an error counter, and 108 is an error display device.

Next, the operation will be described. DVCR1
The digital data reproduced by (101) is
F1 (102), and IEEE1
It is converted to the 394 transfer format. DIF1 (10
The output of 2) passes through the IEEE1394 cable 103,
The data is transferred to DIF2 (104).

The DIF 2 (104) separates and outputs the digital data D and an error signal err indicating data error information in the packet. Digital data D output from DIF2 (104), error signal err
Is input to the DVCR2 (105). DVCR2
In (105), the digital data D is input to the data decoding unit 106, decoded into a video signal and output, or recorded on a magnetic tape by the DVCR 2 (105). DIF2 (1
04) output error signal err is DVCR2
An error counter (107) in (105) counts the number of error packets in a reference unit time such as one frame, one field, etc.
08. It is not necessary to display the count value itself on the error display device 108, and the display may be performed in accordance with the count value.

FIG. 2 shows a second embodiment of the present invention.
The receiving digital VTR (DVCR2 (1
FIG. 05)) is a block diagram according to the present embodiment. FIG.
In the figure, 701 is an error counter, 702 is a data decoding unit, 703 is a comparator, and 704 is an error processing unit.

The received data is separated into digital data D and an error signal err by the DIF 2 (104), and the digital data D is subjected to data processing by the data decoding unit 702 as in the first embodiment. The error counter 701 counts the error packet amount within the reference time for the error signal err as in the first embodiment.

The comparator 703 compares the count value of the error counter 701 with the threshold value TH, and the result of the comparison is input to the error processing unit 704. Error processing unit 704
The processing for stopping / stopping the recording operation during dubbing recording of the reproduction data of the DVCR1 (101) by the DVCR2 (105) according to the comparison result, and the DV during the still image transmission.
The main memory in the CR2 (105) executes a write-inhibit signal output process and the like.

FIG. 3 shows a third embodiment of the present invention.
It is a block diagram of a receiving side digital VTR (DVCR2 (105)). 3, reference numeral 801 denotes an error counter; 802, a data decoding unit; 803, a comparator;
Reference numeral 4 denotes a viewfinder (EVF).

The received data is separated into digital data D and an error signal err by the DIF 2 (104), and the digital data D is processed by the data decoder 802. The error signal err is also counted by the error counter 801 in the error packet amount within the reference time. The comparator 803 includes an error counter 80
The count value of 1 is compared with the threshold value TH, and the comparison result is displayed on the EVF 804 together with the decoded video signal. The display contents in the EVF 804 may be not only “error information (presence or absence of an error)” but also information such as “treatment means (for example, review of cable connection)”.

The system of the DVCR 2 shown in FIGS. 1, 2 and 3 may be configured as hardware, or may be configured as a microcomputer system including a CPU, a memory, and the like. When configured in a microcomputer system, the memory constitutes a storage medium according to the present invention.
The storage medium stores a program for executing the processing described above with reference to FIGS. In addition, as the storage medium, semiconductor memories such as ROM and RAM,
An optical disk, a magneto-optical disk, a magnetic medium, or the like may be used, and these may be used as a CD-ROM, a floppy disk, a magnetic tape, a nonvolatile memory card, or the like.

[0030]

As described above, according to the present invention,
By counting the error signal and displaying the error state based on the count result, the user can know the error level accurately, and take necessary measures according to the error state, for example, during dubbing of input data. Can be taken.

According to the present invention, the error signal is counted, and the recording operation is controlled in accordance with the count result, so that necessary processing can be automatically performed when there are many errors during dubbing. .

Further, by displaying the error state together with information data (for example, video data) corresponding to the error state, the error state during dubbing can be grasped together with the image using the viewfinder. Necessary actions can be taken according to the error condition.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a configuration diagram when digital dubbing is performed.

FIG. 5 is a configuration diagram of block data.

FIG. 6 is a configuration diagram showing a transfer format on a serial bus.

FIG. 7 is a configuration diagram of a conventional memory access.

FIG. 8 is a timing chart in FIG. 7;

[Explanation of symbols]

104 Receiver digital interface (DIF
2) 105 Reception-side digital VTR (DVCR2) 106, 702, 802 Data decoding unit 107, 701, 801 Error counter 108 Error display device 703, 803 Comparator 704 Error processing unit 804 Viewfinder (EVF)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/91 H04N 5/91 P

Claims (21)

[Claims] An input unit for inputting information data; a detection unit for detecting an error in the information data input by the input unit; and a count for counting the number of errors detected by the detection unit at predetermined time intervals. Means for displaying an error state of the information data based on a count result of the counting means. 2. The information processing apparatus according to claim 1, wherein the information data is image data, and the predetermined time is one screen period. 3. The apparatus according to claim 2, wherein said input means inputs said information data in a packet unit consisting of a plurality of blocks each having a predetermined data length, and said detecting means detects an error of said packet. 3. The information processing device according to 1 or 2. 4. The information processing apparatus according to claim 1, further comprising a recording unit that records information data input by said input unit on a recording medium. 5. The information processing apparatus according to claim 1, wherein the information data input by the input means is displayed on the display means. 6. A control device comprising: a comparing unit that compares a count value with a predetermined threshold value by the counting unit; and a control unit that controls a recording operation of the recording unit according to a comparison result of the comparing unit. The information processing apparatus according to claim 4, wherein 7. The information processing apparatus according to claim 1, wherein the information data is encoded data, and further includes a decoding unit that decodes the encoded data. 8. The information processing apparatus according to claim 1, wherein said detection means detects an error using an error check code included in said information data. 9. The information processing apparatus according to claim 1, wherein said input means is a digital interface conforming to IEEE 1394. 10. An input unit for inputting information data, a recording unit for recording the information data input by the input unit on a recording medium, and a detection unit for detecting an error in the information data input by the input unit. And counting means for counting the number of errors detected by the detecting means at predetermined time intervals, and control means for controlling a recording operation of the recording means based on a count result of the counting means. Information processing device. 11. The information data is image data,
The information processing apparatus according to claim 10, wherein the predetermined time is one screen period. 12. The apparatus according to claim 1, wherein said input means inputs said information data in a packet unit consisting of a plurality of blocks each having a predetermined data length, and said detection means detects an error of said packet. 12. The information processing apparatus according to 10 or 11. 13. The information processing apparatus according to claim 10, further comprising display means for displaying an error state of said information data based on a count result of said counting means. 14. An information processing apparatus according to claim 10, wherein information data input by said input means is displayed on said display means. 15. The apparatus according to claim 10, wherein said control means compares said count value with a predetermined threshold value by said counting means, and controls the recording operation of said recording means according to the comparison result. 15. The information processing apparatus according to 14. 16. The information processing apparatus according to claim 10, wherein said detecting means detects an error using an error check code included in said information data. 17. The information processing apparatus according to claim 10, wherein said input means is a digital interface based on IEEE1394. 18. An input step of inputting information data, a detecting step of detecting an error of the input information data, a counting step of counting the number of the detected errors at predetermined time intervals, and the counting result. A displaying step of displaying an error state of the information data based on the information processing method. 19. An input step of inputting information data, a recording step of recording the input information data on a recording medium, a detection step of detecting an error of the input information data, and the detected error An information processing method, comprising: a counting step of counting the number of times at predetermined time intervals; and a control step of controlling a recording operation of the recording step based on the count result. 20. A detection process for detecting an error in the input information data, a count process for counting the number of detected errors at predetermined time intervals, and an error state of the information data based on the count result. A computer-readable storage medium storing a program for executing a display process for performing a display. 21. A recording process for recording input information data on a recording medium; a detection process for detecting an error in the input information data; and a count for counting the number of detected errors at predetermined time intervals. A computer-readable storage medium storing a program for executing a process and a control process for controlling a recording operation of the recording step based on the count result.