JPH07326127A - Control signal generating circuit - Google Patents

Abstract

PURPOSE:To control reading at a desired timing by producing a read-out timing when a data packet and the like are received to write in an FIFO and to read out at a different speed and the output value of a counter circuit reaches a predetermined value. CONSTITUTION:A counter 13 counts a clock CLK during a period of a cycle through a cycle number and cycle offset circuit 2 receiving a data packet to which a cycle start pulse and a cycle data comprising a successive data packet from a transmitter VTR side are added, and is reset every time when it reaches the maximum value, and the received data are written in an FIFO 8. At that time, when the output value of the counter 13 reaches a target value +2alpha correction value, a switch 16 is turned on by a counter value detection circuit 14 to generate the read-out timing signal c of the FIFO 8. Therefore, even when the target value is smaller than the count output, a desired timing signal in response to a next cycle is generated.

Description

Detailed Description of the Invention

[0001]

The present invention relates to time-series data such as video data and audio data, for example, IEEE-
Serial bus compliant with P1394 (hereinafter "P1394
And a communication control bus such as "serial bus").

[0002]

2. Description of the Related Art A system for connecting a plurality of devices by a communication control bus capable of mixing control signals and information signals, such as a P1394 serial bus, and communicating information signals and control signals between these devices is considered. Has been.

FIG. 9 shows an example of such a system. This system includes devices A, B, C, D and E. And between the devices A-B, between A-C, between C-D, and C-E
The parts are connected by a twisted pair cable of P1394 serial bus. These devices are, for example, digital VTRs, tuners, monitors and the like. Since each device has a function of relaying information signals and control signals input from the twisted pair cable, this system is equivalent to a system in which each device is connected to a common communication control bus as shown in FIG. .

Data transmission between the devices A to E sharing the communication control bus is performed by time division multiplexing every predetermined communication cycle (for example, 125 μsec) as shown in FIG. The management of the communication cycle on the communication control bus is performed by a predetermined device that manages the communication system, for example, device A.
Is the synchronization of communication, that is, by transmitting a synchronization packet (cycle start packet: hereinafter referred to as “CSP”) indicating that it is the start of a communication cycle to another device on the communication control bus, data transmission in the communication cycle is performed. Be started.

Time information on the communication control bus is managed by a clock register of each device. The clock register of each device generates time information by counting its own clock. This time information is 125μ
It is reset every sec. In addition, it is corrected by the time information given to the CSP.

The data format transmitted in one communication cycle is 2 types of synchronous type data such as video data and audio data and asynchronous type data such as connection control commands.
It is a kind. Then, the synchronous data packet is transmitted before the asynchronous data packet. By assigning channel numbers 1, 2, 3, ... N to each synchronous data packet, a plurality of synchronous data can be distinguished. After the transmission of the synchronous data packet of all channels is completed, the period until the next CSP is used for the transmission of the asynchronous data packet.

In the communication system configured as described above, when the communication cycle is ideally repeated every 125 μsec, the timing at which the clock register of each device is reset matches the timing of the CSP. However, for example, when the transmission time of asynchronous data becomes long, the timing at which the next communication cycle starts is delayed, so that the timing of CSP is delayed from the timing at which the clock register of each device is reset.

[0008]

In the communication system described above, the video data and audio data (hereinafter referred to as "A") output by the digital VTR are used as synchronous data.
V data) will be transmitted to another digital VTR.

When synchronous data such as AV data is transmitted through a transmission line having a speed different from that of the data, the transmitting side adjusts the AV data generated by the digital VTR to the transmission speed of the transmission line. Moreover, in order to restore the received AV data to the data rate of the digital VTR, the receiving side needs a FIFO for temporarily holding the data.

According to the present invention, in such a case, the FI on the receiving side is
An object of the present invention is to provide a circuit that generates a control signal for reading the data held in the FO at a desired timing.

[0011]

In order to solve the above problems, the present invention receives a packet indicating the start of a communication cycle and a data packet, writes the received data packet in a temporary storage means, and writes the data at a writing speed. A circuit that generates a signal that controls the read timing in a device that reads at a different speed, and the count value changes in a sawtooth shape and is corrected by the time information that is added to the packet that indicates the start of the communication cycle. A circuit, and a circuit that obtains a target value of the time to read the data packet based on the time information given to the data packet at every predetermined time;
A circuit for comparing the target value with the output value of the counting circuit, and generating a signal for controlling the read timing when the output value of the counting circuit exceeds the target value and becomes the closest value. To do.

Here, the generation of the signal for controlling the read timing falls within the range of the output value of the counting circuit, for example, between the target value and the target value plus twice the maximum correction value of the counting circuit. It is preferable to do it at the same time.

Further, when the target value is smaller than the output value of the counting circuit when the target value is obtained, a signal for controlling the read timing is output when the target value is exceeded again after the counting circuit is reset. Configure to occur. It is preferable to detect that the counting circuit has been reset because the output value of the counting circuit has changed more than the maximum correction value.

[0014]

According to the present invention, the target value is compared with the output value of the counter circuit, and when the output value of the counter circuit exceeds the target value and becomes the closest value, a signal for controlling the read timing is generated. To do. Therefore, even if the target value is smaller than the output value of the counting circuit when the target value is obtained, the signal for controlling the read timing is not immediately generated. Further, even if the count value is corrected at the moment when the output value of the counting circuit exceeds the target value and the count value changes discontinuously, a signal for controlling the read timing can be generated at a desired timing.

In the present invention, by detecting the reset because the output value of the counting circuit has changed more than the maximum correction value, the reset can be detected even if the count value is corrected at the moment of the reset.

[0016]

Embodiments of the present invention will be described in detail below with reference to the drawings. In the embodiment of the present invention, P1394
AV data is transmitted between digital VTRs connected by a serial bus. At this time, one-track AV data of the digital VTR is divided into 25 packets and transmitted. In the case of the 525/60 system, one frame of AV data is divided into 10 tracks (10 segments) and recorded. In the following description, digital V
TR is simply called VTR.

First, the format of a packet transmitted in the embodiment of the present invention will be described. Figure 1 is CS
FIG. 2 shows the format of P, FIG. 2 shows the first data packet in the segment, and FIG. 3 shows the second to 25th data packets.

The CSP has a width of 33 bits (1 quadlet) and a length of 5 quadlets. The first quadlet of the CSP contains the destination ID and tco
de is written. The destination ID is the ID of the destination of the packet. And tcod
e is a value indicating the type of packet, and is 8 in the case of CSP
Is written. Source for the second quadlet
e ID is written. This is the source I of the packet
It is D.

A cycle number and a cycle offset are written in the fourth quadlet. This is the absolute time at the sender when the packet is sent. In this way, the absolute time is expressed by both the cycle number and the cycle offset. Cycle offset is 40.7
It is counted up in nsec and reset to 0 at 3072. Therefore, it takes 125 μsec for the cycle offset to make one round. Then, the cycle number is incremented each time the cycle offset makes one round. The cycle number is reset to 0 at 8000. Therefore, the cycle number is 1s per turn.
It takes ec. However, the cycle number may be configured so as to make one round in a shorter time, for example, about 1/60 sec. The receiving side can correct the deviation from the absolute time of the transmitting side by taking in these values.

A CRC is written in the fifth quadlet. This is a bit string for error detection of this packet. The dc bit is 1 only at the beginning and the end of the packet, and is 0 elsewhere. This is used to establish frame synchronization.

Next, the data packet will be described.
As shown in FIGS. 2 and 3, the data length is written in the first quadlet of the data packet, and 484, which is the length obtained by subtracting 8 bytes from the total length of the packet, is written. Next is the channel number. This is used to distinguish between a plurality of types of data when they are transmitted on the same transmission path. After this, two reserved bits are entered, and tcode is written after that. 10 is written in the data packet.

The track number is written in the second quadlet. As mentioned above, 25 data packets
One track is one track. Therefore, the track number is incremented by 1 for every 25 packets. Further, since one frame of AV data is divided and recorded in 10 tracks, a value of 0 to 9 is periodically entered in the track number. The packet number is written next, and a value from 0 to 24 is periodically entered for each packet. Further, the sync time is written following the 7 reserved bits. The sync time is, for example, an absolute time at which a packet is transmitted, and the VT of the receiving side is determined by a method described later
R is used to create the timing for reading data from the FIFO.

AV data is written from the next quadlet to 120 quadlets, and a CRC for error detection at the time of transmission is written in the last quadlet. From the second data packet to the 25th data packet, the format is the first packet with the sync time removed.

(First Embodiment) FIG. 4 is a diagram showing how packets are input and output and how a counter is changed in the first embodiment of the present invention.

As shown in (a) of this figure, P1394
Packets on the serial bus are alternately CSP and data packets. Then, from the received packet group, CS
P is deleted and only data packets are written to the FIFO.

FIG. 4 (b) shows the timing of packets input to the FIFO, and FIG. 4 (c) shows the timing of packets output from the FIFO. And FIG.4 (d) has shown a mode that the output of a counter changes.

In the present embodiment, the rate at which packets are input to the FIFO is slower than the rate at which packets are output from the FIFO, so it is necessary to temporarily store the input packets in the FIFO and read them after a fixed time. As the timing of reading, the sync time written in the packet with the packet number 0 is used. As described above, the sync time is the absolute time when the packet is transmitted, and the transmission time on the P1394 serial bus can be ignored, so it can be regarded as the absolute time when the packet arrives at the FIFO on the receiving side. On the receiving side, a fixed time (FIFO
(delay) is added to read the data. Hereinafter, this time will be referred to as a target value.

The receiving side has a counter, and the reading of the FIFO is started when the output of the counter exceeds the target value. The output N of the counter is always corrected by the cycle number and cycle offset written at the head of each CSP so as to be synchronized with the absolute time on the transmission side. This is because the sink time is written in the second quadlet of the data packet transmitted by the packet transmission circuit by referring to the output of the counter that is running by the clock in the packet transmission circuit (not shown) during packet transmission. This is because if the output value of the counter deviates from the value of the counter on the transmission side, it may not be possible to read the packet from the FIFO at the correct timing.

In FIG. 4D, the solid line indicates the output value N of the counter, and the upper and lower dotted lines indicate that the output value N of the counter is C.
This is the range corrected by the cycle number and cycle offset written at the beginning of the SP. The corrected range is ± m at maximum. In the case of this figure, at time t1, the output value of the counter is corrected so as to increase the counter value. Then, thereafter, the counter value is corrected to decrease at time t4, and the counter value is corrected to increase slightly after time t5. Thus, the output value N of the counter when a packet is received may be discontinuous.

Further, in FIG. 4 (d), n is a target value. Then, when the counter value N enters the detection range from the target value n to n + 2m obtained by adding twice the maximum correction value m to this target value, the reading of packets from the FIFO is started.
In the case of this figure, the time t when the counter value N exceeds the target value n
Packets are starting to be read from 3.

The reason for providing this detection range is as follows. If the target value n obtained by adding a fixed time (FIFO delay) to the sync time of the first data packet is smaller than the output of the counter at time t1 when the first packet is received (that is, in the example of FIG. 4), If the above-mentioned detection range is not provided, the output value N of the counter exceeds the target value n at the time when the target value n is obtained, so the read timing is output immediately and the target value has no meaning. This is because it will end up.

Further, the reason why the signal for controlling the timing of reading the packet is not generated by judging whether the counter value N is equal to the target value n is as follows. The counter value N is corrected every time the CSP is received so as to be synchronized with the counter value of the circuit that transmits the packet. Therefore, the counter value N is corrected at the moment when the counter value N matches the target value n, and becomes a discontinuous value. Because there is a possibility.

A block diagram for realizing the above operation is shown in FIG. The packet transmitted on the P1394 serial bus 1 has its cycle number and cycle offset a extracted by the cycle number / cycle offset extraction circuit 2 and output to the counter 13.

The counter 13 continues to increase the output value N by the clock CLK and resets the output value N to 0 when the maximum value MAX is reached. In the case of FIG. 4, it is reset at time t2 and time t5. However, when the cycle number and the cycle offset a are written, the values are set as the output value N of the counter, and thereafter, the values continue to increase from the values of the cycle number and the cycle offset a.

The cycle number / cycle offset extraction circuit 2 deletes the CSP from the input packets and outputs only the data packet to the packet writing circuit 3.

The packet writing circuit 3 writes the input data packet d in the FIFO 8 as it is, and outputs a quadlet to the detection circuit 4 as a timing signal b for writing the packet in the FIFO 8.

The quadlet detection circuit 4 reads the second quadlet from the data packet d and outputs it to the packet number extraction circuit 5 and the sync time extraction circuit 6. The packet number extraction circuit 6 extracts the 5-bit packet number c from the second quadlet, and the packet number determination circuit 1
Output to 0.

The packet number judging circuit 10 judges whether or not the packet number c = 0, and outputs the judgment result to the memory circuit 11. The sync time extraction circuit 6 extracts the lower 16 bits of the second quadlet, adds the value indicated by the register 7, and then outputs it to the storage circuit 11. FI for register 7
Since FO delay is written, the output of the adder 9 becomes the target value n.

The storage circuit 11 is a packet number determination circuit 10.
The value input from the sync time extraction circuit 6 is stored when the determination result of is true. Because the packet number =
This is because 0, that is, the sync time is written only in the first packet.

The target value n stored in the storage circuit 11 is output to the counter output determination circuit 12 where <target value <counter output. Target value <
The counter output determination circuit 12 compares the target value n with the output value N of the counter 13, and a signal e indicating “true” when the output value N of the counter is larger and “false” when it is not larger. Is output to the switch 15.

The switch 15 is controlled by the counter value detection circuit 14. The counter value detection circuit 14 receives the output value N of the counter 13 and the target value n output from the storage circuit 11. Then, the switch 15 is closed when it is detected that the output value N of the counter 13 is between the target value n and n + 2m, which is a value obtained by adding a value obtained by doubling the maximum correction value m to the target value n. .

As a result, the target value <the output signal e of the counter output determination circuit 12 is output to the VTR 17 as a read timing signal. When receiving the read timing signal, the VTR 17 outputs a read signal f to the packet read circuit 16. When the packet read circuit 16 receives the read signal f, the FIFO
The data g is read from 8 and output to the VTR 17 as it is.

By the above operation, it is possible to write a packet at a low speed to the FIFO 8 and read it at a high speed.

(Second Embodiment) FIGS. 6 and 7 are views showing how a packet is input and output and how a counter is changed in the second embodiment of the present invention, and FIG. 8 is for realizing it. It is a block diagram of. Here, the same numbers are assigned to the portions corresponding to those in the first embodiment. The following description will focus on the parts that differ from the first embodiment.

In the operation example of FIG. 6, the target value n obtained by adding the FIFO delay to the sync time of the first packet
Is larger than the counter value N at time t6 when the first packet is received. Therefore, the counter value N is the target value n
It is possible to make a timing for reading a packet from the FIFO by determining whether or not the packet has been exceeded.
In the case of this figure, reading is started from time t7. As described above, since there is a possibility that the counter value N is corrected by the CSP at the moment when it coincides with the target value n and becomes a discontinuous value, it is possible to judge whether the counter value N and the target value n are equal to each other. It is not possible to create a signal that controls when to read a packet.

Next, a case where the target value n is smaller than the counter value N at the time t6 when the first packet is received will be described with reference to FIG. In the example of FIG. 7, the packet read timing cannot be created by simply comparing the magnitude relationship between the counter value N and the target value n.
This is because if a packet read timing is simply created by a method similar to the example of FIG. 6, the counter value N when the first packet is received at time t8 is already larger than the target value n, so the first packet is received. This is because the packet reading timing is created at the moment when the packet is read.

Therefore, in the example of FIG. 7, after the target value n is received, waiting for the counter to be reset is performed at time t9.
After being reset by, the counter value N is reset as in the example of FIG.
And the target value n are compared, and when the counter value N exceeds the target value n at time t10, a packet read timing is created.

Whether or not the counter has been reset can be detected by detecting that the counter value N has changed more than the maximum correction value m. The clock that operates the counter of the packet transmission circuit and the clock CLK that operates the counter of the reception side have the same frequency, although there is a slight error. Therefore, in the actual circuit, the correction maximum value m is 1 at most. It is about 2. When the counter is reset, it changes from the maximum value MAX to about 0 or 1 or 2. Therefore, by detecting whether the counter value N has changed more than the correction maximum value m as described above, the counter can be It can detect whether it has been reset.

FIG. 8 shows a block diagram for realizing the above operation. As is clear from comparison between FIG. 5 and FIG. 8, in this embodiment, the counter value detection circuit 1 of the first embodiment is
4, a reset detection circuit 18 and a read timing control circuit 19 are provided.

The reset detection circuit 18 constantly monitors the output value N of the counter 13 to check whether the change exceeds the maximum correction value m. If a change exceeding the maximum correction value m is detected, the detection result is read out and timing control is performed. Circuit 1
Output to 9.

Read timing control circuit 19
Determines whether the packet read timing is output after the counter 13 is once reset by checking the output of the target value <counter output determination circuit 12 at the same timing as the timing at which the second quadlet is detected. To do. If the target value <the output e of the counter output determination circuit 12 is “true”, the output value of the counter 13 has already exceeded the target value n, so the read timing control circuit 19 first opens the switch 15, Switch 1 after the counter 13 is reset once
5, the target value <the output of the counter output determination circuit 12 is output to the VTR 17 as a read timing signal.

If the target value <the output of the counter output determination circuit 12 is “false”, the read timing control circuit 19 does not exceed the target value n because the output value N of the counter 13 does not exceed the target value n. Closes switch 15. As a result, when the target value <the output e of the counter output determination circuit 12 becomes “true”,
This is used as it is as a read timing signal in VTR1.
Output to 7.

Although each of the embodiments described above writes a packet to the FIFO at a slow speed and reads it at a high speed, the present invention can also be applied to a case of writing at a high speed and reading at a slow speed.

Further, in each of the above-described embodiments, the FIFO de is set on the receiving side at the sync time written in the data packet.
The target value is obtained by adding lay, but the sync time to write in the data packet is the FIFO de on the receiving side.
The time including lay, that is, the sync time can be configured to be the target value as it is.

Further, in each of the above embodiments, the case where the reproduction data of the VTR of the 525/60 system is transmitted to another VTR via the P1394 serial bus has been described.
The present invention can also be applied to a 625/50 system, an HD system, a system for transmitting data other than video data and audio data, for example, computer data.

[0056]

As described above in detail, according to the present invention, the signal for controlling the timing for reading the data packet received and written in the temporary storage means exceeds the target value and is the closest timing. Can occur in.

When the target value at the time of reading is obtained, even if the target value is smaller than the output value of the counting circuit,
It does not immediately generate a signal for controlling the read timing.

Further, even if the count value is corrected at the moment when the output value of the counting circuit exceeds the count value and the count value changes discontinuously, a signal for controlling the read timing can be generated at a desired timing.

Furthermore, by detecting the reset because the output value of the counting circuit has changed more than the maximum correction value, it is possible to detect the reset even if the count value is corrected at the moment of resetting.

Therefore, when the present invention is applied to a system for transmitting AV data between VTRs connected by the P1394 serial bus, a timing signal for the VTR on the receiving side to read the data held in the FIFO at a desired timing. Can be created.

[Brief description of drawings]

FIG. 1 is a diagram showing a format of a cycle start packet.

FIG. 2 is a diagram showing a format of a first data packet in a segment.

FIG. 3 is a diagram showing a format of second and subsequent data packets in a segment.

FIG. 4 is a diagram showing how a packet is input / output and how a counter is changed in the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 6 is a diagram showing an example of how packets are input and output and how a counter is changed in the second embodiment of the present invention.

FIG. 7 is a diagram showing another example of how a packet is input / output and how a counter is changed in the second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 9 is a diagram showing an example of a communication system using a P1394 serial bus.

10 is a diagram equivalently describing the system of FIG. 9. FIG.

FIG. 11 is a diagram showing an example of a communication cycle in a communication system using a P1394 serial bus.

[Explanation of symbols]

2. Cycle number, cycle offset detection circuit,
3 ... Packet writing circuit, 4 ... Quadlet detection circuit, 5 ... Packet number extraction circuit, 6 ... Sync time extraction circuit, 7 ... Register, 8 ... FIFO, 9 ... Addition circuit, 1
0 ... Packet number determination circuit, 11 ... Storage circuit, 12 ... Target value <Counter output determination circuit, 13 ... Counter, 14 ...
Counter value detection circuit, 15 ... Switch, 16 ... Packet reading circuit, 17 ... VTR, 18 ... Reset detection circuit, 19 ... Read timing control circuit

Claims (4)

[Claims] 1. A circuit for receiving a packet indicating a start of a communication cycle and a data packet, writing the data packet in a temporary storage means, and generating a signal for controlling read timing in a device for reading at a speed different from the write speed. A count circuit that changes in a sawtooth shape and is corrected by the time information added to the packet indicating the start of the communication cycle; and a count circuit that is added to the data packet at predetermined time intervals. A circuit that obtains a target value at the time of reading the data packet based on time information is compared with the output value of the counting circuit, and the output value of the counting circuit exceeds the target value and is closest. A circuit for generating a signal for controlling the read timing when the value is reached, and a control signal generating circuit. 2. A signal for controlling read timing is generated when the output value of the counting circuit falls within a range between a target value and a value obtained by adding twice the maximum correction value of the counting circuit to the target value. The control signal generation circuit according to claim 1. 3. When the target value is smaller than the output value of the counting circuit when the target value is obtained, the reading timing is controlled when the target value is exceeded again after the counting circuit is reset. The control signal generating circuit according to claim 1, which generates a signal. 4. When the output value of the counting circuit changes more than the maximum correction value, it is reset.
The control signal generation circuit described.