JP4061731B2 - Signal processing circuit and method thereof - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a signal processing circuit used in a digital serial interface and a method thereof.
[0002]
[Prior art]
In recent years, IEEE (The Institute of Electrical and Electronic Engineers) 1394 and High Performance Serial Bus that realize high-speed data transfer and real-time transfer have been standardized as interfaces for multimedia data transfer.
[0003]
In the data transfer of the IEEE1394 serial interface, a transfer operation performed in the network is called a subaction and two subactions are defined.
One is conventional Asynchronous transfer for request / acknowledge request and reception confirmation, and the other is isochronous transfer for sending at least one packet every 125 μs per channel. Isochronous transfer has an advantage that the data transmission speed is guaranteed.
[0004]
  By the way, in isochronous transfer, when an isochronous communication packet is transmitted via the IEEE1394 serial bus, a jitter generated in the application interface on the transmission side or the IEEE1394 serial bus is generated.TIf the transmission time of the isochronous communication packet exceeds the allowable maximum delay time specified by the DV protocol, the isochronous communication packet is not processed effectively on the receiving side, for example, in time for display timing. Such a situation will occur.
[0005]
  Therefore, when transmitting a packet for isochronous communication, the transmitting side determines whether the transmission timing does not exceed the allowable maximum delay time, and if it determines that the allowable maximum delay time is exceeded, Then, a rate process that does not transmit the isochronous communication packet is performed.
  Conventionally, transmission data is sent to the application on the transmission side.I / FThe timing to input from is fixedYes,Since the earliest time during which an isochronous communication packet to be transmitted can be transmitted is regularly determined, the rate processing is performed at regular time intervals. For example, applicationI / FWhen the transmission data input from is a video signal, the rate processing is performed in units of frames with reference to the frame synchronization signal.
[0006]
[Problems to be solved by the invention]
  However, on the transmission side, the transmission dataI / FWhen the input timing fluctuates, the earliest time at which an isochronous communication packet can be transmitted is irregularly determined, and the conventional method described above has a problem that the rate processing cannot be performed appropriately.
[0007]
  The present invention has been made in view of the above-described problems of the prior art, and uses transmission data as an application.I / FAn object of the present invention is to provide a signal processing circuit that can perform rate processing appropriately even when the input timing of the input signal fluctuates.
[0008]
[Means for Solving the Problems]
  In order to solve the above-described problems of the prior art and achieve the above-described object, the signal processing circuit according to the first aspect of the present invention is connected to another node connected via a serial interface bus from its own node. In a signal processing circuit that transmits packets at time intervals ofA timer for determining a reference time and transmission data whose input timing is variable are input, and writing and reading are performed in units of a plurality of second blocks obtained by dividing the first block defined in the transmission data. First storage means to be performed and a synchronization signal indicating a break of the first block in the transmission dataEnter the relevantBased on a synchronization signal and a reference time indicated by the timer, a reference timing signal for transmitting the second block as a packet is generated, and a predetermined delay time is added to the reference timing signal to obtain a time stamp Transmission time instruction data generating means for generating data and outputting it as transmission time instruction data;A rate determining circuit for determining whether or not the latest time at which transmission of the packet is permitted has elapsed when the packet is transmitted; andCompare the reference time and the transmission time instruction data,If it is determined that the latest time has not passed,The packet having the second block stored in the first storage means;When transmitted to the other node via the serial interface bus and the late determination circuit determines that the latest time has elapsed,FirstStorage meansThe packet having the second block stored inIs transmitted to the other node via the serial interface bus.
[0009]
In the signal processing circuit according to the first aspect of the present invention, first, in the rate determination circuit, when transmitting a packet, it is determined whether or not the latest time at which transmission of the packet is permitted has elapsed. .
When the late determination circuit determines that the latest time has not elapsed, the packet is transmitted to the other node via the serial interface bus by the transmission determination unit, and the late determination circuit When it is determined that the latest time has elapsed, the transmission determination unit does not transmit the packet to the other node via the serial interface bus.
[0010]
  The signal processing circuit according to the second aspect of the present invention receives a timer for determining a reference time and transmission data whose input timing is variable, and is obtained by dividing the first block defined in the transmission data. A first storage means for writing and reading in units of a plurality of second blocks, a synchronization signal indicating a break of the first block in the transmission data, and the synchronization signal and the timer Based on the reference time indicated by the reference signal, a reference timing signal for transmitting the second block as a packet is generated, and a predetermined delay time is added to the reference timing signal to generate time stamp data. , Transmission time instruction data generating means for outputting as transmission time instruction data, andReference timing signalAnd when the second block is read from the first storage means, the second block corresponding to the read second blockReference timing signalReading means for reading from the second storage means;The transmission time instruction data andA reference time indicated by the timer;CompareThe firstofTransmission determining means for determining whether or not to transmit the second block read from the storage means.
[0011]
  In the signal processing circuit according to the second aspect of the present invention, transmission data is read after being written in the first storage means in units of the first block, and is output to the transmission determination means.
  At the same time, a block identification signal indicating the delimiter of the first block in the transmission data is input to the transmission time instruction data generating means, and based on the block identification signal and the reference time indicated by the timer Transmission time instruction data indicating the earliest time at which transmission of the second block is permitted is generated for each second block.
  next,Reference timing signal corresponding to the second blockIs stored in the second storage means, and when the second block is read from the first storage means, the second block corresponding to the read second block is stored.Reference timing signalIs read from the second storage means and output to the transmission determining means.
  Next, in the transmission determining means,The transmission time instruction data andA reference time indicated by the timer;CompareThe firstofDecide whether to transmit the second block read from the storage meansDo.
[0012]
  The signal processing method of the present invention is a signal processing method in which packets are transmitted from a local node to another node connected via a serial interface bus at predetermined time intervals, and transmission data with variable input timing is input. Writing to the first storage means in units of a plurality of second blocks obtained by dividing the first block defined in the transmission data, and delimiting the first block in the transmission data Input a synchronization signal indicatingBitBased on the reference time indicated by the timer, a reference timing signal for transmitting the second block as a packet is generated, and a predetermined delay time is added to the reference timing signal to generate time stamp data. Outputting as transmission time instruction data, andReference timing signalIn the second storage means, and when the second block is read from the first storage means, the second block corresponding to the read second blockReference timing signalReading from the second storage means, and the second blockTheWhen transmitting as the packet, the step of determining whether or not the latest time at which transmission of the packet is permitted has elapsed has been compared with the reference time and the transmission time indication data, and the latest When it is determined that the time has not elapsed, the packet is transmitted to the other node via the serial interface bus, and when it is determined that the latest time has elapsed, the packet is transmitted to the serial interface bus. And not transmitting to the other nodes via the network.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
A signal processing circuit for DVCR (Digital Video Cassette Recorder) according to an embodiment of the present invention will be described below.
The DVCR signal processing circuit according to the present embodiment has a main feature in the rate processing circuit of the link layer circuit.
[0014]
FIG. 1 is a configuration diagram of a DVCR signal processing circuit 1.
As shown in FIG. 1, the DVCR signal processing circuit 1 includes, for example, a link layer circuit 10, a physical layer circuit 20, and a microcomputer 30.
The link layer circuit 10 is connected to the digital video cassette recorder 40, and the physical layer circuit 20 is connected to the IEEE 1394 serial bus BS.
[0015]
The link layer circuit 10 performs control of asynchronous transfer and isochronous transfer and control of the physical layer circuit 20 under the control of the microcomputer 30.
As shown in FIG. 1, the link layer circuit 10 includes, for example, a link core 101, a microcomputer I / F (Interface) 102, a transmission FIFO memory (AT-FIFO) 104, and a reception FIFO memory (AR-FIFO). 105, outbound circuit 106, auto response circuit 107, transmission link FIFO memory (LAT-FIFO) 108, inbound circuit 109, demultiplexer 110, configuration register (Configuration Register, hereinafter referred to as CFR) group 111, transaction register (Transaction Register) ), A digital video camera I / F 120, a rate processing circuit 121, an isochronous communication FIFO memory (I-FIFO) 122, and a pre-reception / post-transmission processing circuit 123.
[0016]
In the DVCR signal processing circuit 1, the link core 101, microcomputer I / F 102, transmission FIFO memory 104, reception FIFO memory 105, outbound circuit 106, auto response circuit 107, transmission link FIFO memory 108 and demultiplexer 110 are used. Asynchronous communication system circuits are configured.
The demultiplexer 110, the link core 101, the digital video cassette recorder I / F 120, the rate processing circuit 121, the isochronous communication FIFO memory 122, and the pre-reception / post-transmission processing circuit 123 constitute an isochronous communication system circuit. The
[0017]
  Asynchronous communication system circuit
  [Microcomputer I / F102]
  The microcomputer I / F 102 mainly arbitrates writing and reading of asynchronous communication packets between the microcomputer 30 and the transmission FIFO memory 104 and the reception FIFO memory 105, and the microcomputer 30 and the CFR group 111. Arbitrary transmission / reception of various data.
  For example, the microcomputer 30 receives a nominal signal in the late processing circuit 121 as will be described later.・A nominal initial value and a nominal step value used for generating a timing (NT) signal are set in predetermined registers of the CFR group 111 via the microcomputer I / F 102.
[0018]
[Transmission FIFO Memory 104 and Reception FIFO Memory 105]
The transmission FIFO memory 104 stores an asynchronous communication packet to be transmitted to the IEEE 1394 serial bus BS, and the reception FIFO memory 105 stores an asynchronous communication packet transmitted through the IEEE 1394 serial bus BS.
[0019]
[Inbound circuit 109]
The inbound circuit 109 outputs the asynchronous communication packet input from the demultiplexer 110 to the auto response circuit 107 when the auto response is specified by a predetermined register of the CFR group 111. On the other hand, the inbound circuit 109 outputs the asynchronous communication packet input from the demultiplexer 110 to the reception FIFO memory 105 when the auto response is not specified by a predetermined register of the CFR group 111.
[0020]
[Auto response circuit 107]
The auto response circuit 107 performs predetermined auto response processing on the asynchronous communication packet input from the inbound circuit 109, and outputs the asynchronous communication packet that is the processing result to the outbound circuit 106.
Here, the auto-response process is not performed by outputting the asynchronous communication packet transmitted through the IEEE 1394 serial bus BS to the microcomputer 30 but processing it in the link layer circuit 10. The result is a process of transmitting the IEEE 1394 serial bus BS.
[0021]
[Outbound circuit 106]
The outbound circuit 106 outputs the asynchronous communication packet input from the auto response circuit 107 to the transmission link FIFO memory 108 when the auto response is designated by a predetermined register of the CFR group 111. On the other hand, the outbound circuit 106 outputs the asynchronous communication packet input from the transmission FIFO memory 104 to the transmission link FIFO memory 108 when the auto response is not specified by the predetermined register of the CFR group 111.
[0022]
[Transmission link FIFO memory 108]
The transmission link FIFO memory 108 is a ring buffer that stores the asynchronous communication packet input from the outbound circuit 106.
[0023]
[Demultiplexer 110]
The demultiplexer 110 refers to the t-code (not shown in FIG. 2) existing in the 1394 header of the communication packet input from the link core 101, and the asynchronous communication packet and the isochronous communication packet The self-uro packet is identified, and if it is an asynchronous communication packet, it is output to the inbound circuit 109, and if it is an isochronous communication packet, it is output to the pre-reception / post-transmission processing circuit 123.
[0024]
[Link Core 101]
The link core 101 has a transmission circuit and a reception circuit for asynchronous communication packets and isochronous communication packets, an interface circuit with the physical layer circuit 20 that directly drives the IEEE 1394 serial bus BS of these packets, and a cycle time that is reset every 125 μs. Is composed of a cycle timer, a cycle monitor and a CRC circuit.
The link core 101 transmits / receives a CS (Cycle Start) packet indicating whether transmission / reception is possible or not every 125 μs to / from a transmission / reception destination signal processing circuit via the physical layer circuit 20 and the IEEE 1394 serial bus BS.
For example, time data such as cycle time and the presence / absence of transmission / reception of a CS packet are supplied and instructed to the isochronous communication processing circuit through a predetermined register of the CFR group 111.
[0025]
Isochronous communication system circuit
Before describing the components of the isochronous communication system circuit, the format of the packet for isochronous communication will be described.
[Packet format for isochronous communication]
FIG. 2 is a diagram showing a basic configuration example of an isochronous communication packet.
As shown in FIG. 2, in the isochronous communication packet, the first quadlet has a 1394 header (Header), the second quadlet has a header CRC (Header-CRC), the third quadlet has a CIP header 1 (CIP-Header1), and the fourth quadlet. The quadlet is a CIP header 2 (CIP-Header2), and the fifth and subsequent quadlets are a data area (Data). The last quadlet is data CRC (Data-CRC).
[0026]
The 1394 header includes a data-length indicating a data length, a channel indicating a channel number (any one of 0 to 63) to which the packet is transferred, a tcode indicating a processing code, and a synchronization code sy defined by each application. It is configured.
The header CRC is an error detection code of the packet header.
[0027]
The CIP header 1 includes a SID (Source node ID) area for a transmission node number, a DBS (Data Block Size) area for the length of a data block, and an FN (Fraction Number) for the number of data divisions in packetization. Area, QPC (Quadlet Padding Count) for padding data quadlet number, SPH area for flag indicating presence / absence of source packet header, DBC (Data Block Continuty Counter) for counter to detect number of isochronous packets It is composed of areas.
The DBS area represents the number of quadlets transferred in one isochronous packet.
[0028]
The CIP header 2 includes an FMT area for a signal format indicating the type of data to be transferred, an FDF (Format Dependent Field) area used corresponding to the signal format, and SyncTime for time stamp information of the frame pulse signal FR. It is comprised by.
[0029]
The data CRC is a data field error detection code.
[0030]
Hereinafter, each component of the isochronous communication system circuit will be described in detail.
[Digital Video Cassette Recorder I / F120]
At the time of transmission, the digital video cassette recorder I / F 120 converts the DVCR data having a 4-bit data width input from the digital video cassette recorder 40 into DVCR data having a 32-bit data width, and the converted DVCR data. Is output to the rate processing circuit 121. This is because the minimum data unit of DVCR data input from the digital video cassette recorder 40 is 4 bits, whereas in the IEEE 1394 standard, the minimum data unit handled is 32 bits (= 1 quadlet). That's why.
[0031]
Also, the digital video cassette recorder I / F 120 outputs the frame pulse signal FR input from the digital video cassette recorder 40 to the rate processing circuit 121 at the time of transmission. The frame pulse signal FR is a signal for generating a pulse at the head of a frame of DVCR data input from the digital video cassette recorder 40.
By the way, in this embodiment, the digital video cassette recorder 40 controls the output timing of DVCR data to the digital video cassette recorder I / F 120 based on an output control signal input from the controller 210 described later. is doing.
Therefore, the input timing of DVCR data input from the digital video cassette recorder 40 to the digital video cassette recorder I / F 120 may fluctuate irregularly.
The control of the DVCR data output timing is performed in units of DVCR data for one isochronous communication packet.
[0032]
Also, the digital video cassette recorder I / F 120 converts the DVCR data having a 32-bit data width input from the rate processing circuit 121 into DVCR data having a 4-bit data width at the time of reception, and the converted DVCR data is converted into the DVCR data. Output to the digital video cassette recorder 40.
[0033]
[FIFO memory 122 for isochronous communication]
As illustrated in FIG. 3, the isochronous communication FIFO memory 122 includes, for example, a controller 210 and a RAM (Random Access Memory) 211.
RAM 211 is bank PB₁, PB₂, PB_ThreeAnd PB_Four4 banks, and one switch for writing DVCR data from the digital video cassette recorder I / F 120 is switched based on the switching signal for writing._ThreeAnd the transmission decision circuit 205 selects one bank from which DVCR data is read based on the read switching signal.
Here, bank PB₁, PB₂, PB_ThreeAnd PB_FourEach has a storage capacity of 480 bytes capable of storing DVCR data for one isochronous communication packet shown in FIG.
In the case of the NTSC system, one frame of DVCR data is divided into 250 isochronous communication packets.
[0034]
The controller 210 monitors the storage state of the RAM 211 and generates an output control signal for controlling the output of DVRC data from the digital video cassette recorder 40 shown in FIG. 1 so that the RAM 211 does not become full.
Further, the controller 210 monitors the head flag of DVCR data for one isochronous communication packet input from the digital video cassette recorder I / F 120, so that DVCR data for one packet is written to each bank of the RAM 211. If it is determined that data has been written, it is instructed to switch to the next bank by a write switching signal.
In addition, the controller 210 completes the writing of the bank PB for which one packet of DVCR data has been written.₁~ PB_FourA switching signal for reading for sequentially reading DVCR data for one packet is generated.
The controller 210 refers to the presence / absence of transmission / reception of a CS packet obtained through a predetermined register of the CFR group 111 when generating the output control signal, the write switching signal, and the read switching signal.
[0035]
[Late processing circuit 121]
As shown in FIG. 3, the late processing circuit 121 includes, for example, a nominal timing (NT) generation circuit 200, a sampling circuit 201, a register NT-reg.₁, NT-reg₂, NT-reg_Three, NT-reg_Four, Switch SW₁, SW₂, A memory 202, an adding circuit 203, a rate determining circuit 204, and a transmission determining circuit 205.
[0036]
  The nominal timing generation circuit 200 inputs the frame pulse signal FR from the digital video cassette recorder I / F 120 and the nominal initial value and nominal step value read from a predetermined register of the CFR group 111. These are used to generate a nominal timing (NT) signal. In order to reduce the capacity of the RAM 211, the NT signal determines a reference timing (nominal timing) at which isochronous communication packets obtained by dividing one frame of DVCR data are temporally equalized and transmitted.
  Here, the nominal initial value is set so that no pulse is generated in the NT signal before DVCR data for the first one isochronous communication packet input from the digital video cassette recorder I / F 120 is written to the RAM 211. It is used to control the time from when a pulse is generated in the synchronization signal FR to when the first pulse is generated in the NT signal.
  For example, in the WWW system, the nominal step value is not fixed in the number of clocks (time) of one frame.ToSince it depends, it is used to specify and control the time interval for generating a pulse in the NT signal for each frame.
[0037]
The sampling circuit 201 generates a pulse in the NT signal using the NT signal input from the nominal timing generation circuit 200 and the cycle time generated by the link core 101 and input from a predetermined register of the CFR group 111. At the timing, the time indicated by the cycle time is sampled, and the switch SW₁Output to.
Here, the cycle time consists of 32 bits, the lower 12 bits are incremented every 40.69 ns, the upper 13 bits are incremented every 125 μs, and the upper 7 bits indicate the count value in seconds. .
[0038]
Register NT-reg₁, NT-reg₂, NT-reg_ThreeAnd NT-reg_FourSwitch SW₁The NT time from the sampling circuit 201 is written and stored when selected by the switch SW.₂Is selected, the stored NT time is read and output to the adder circuit 203.
Here, register NT-reg₁, NT-reg₂, NT-reg_ThreeAnd NT-reg_FourIs the bank PB of the RAM 211.₁, PB₂, PB_ThreeAnd PB_FourThe NT time of the DVCR data for one isochronous communication packet stored in is stored. The NT time indicates the earliest time at which transmission of DVCR data for one corresponding isochronous communication packet stored in the RAM 211 is permitted.
Switch SW₁And SW_ThreeSwitches in conjunction with the switch SW₂And SW_FourIt switches in conjunction with both.
[0039]
The adder circuit 203 includes a switch SW₂Is added to the NT time input from the memory 202 and 450 μs, which is the allowable maximum delay time read from the memory 202, and the result of the addition is output to the rate determination circuit 204 as a time stamp.
Here, the time stamp indicates the latest time when transmission of the corresponding isochronous communication packet is permitted.
Further, the allowable maximum delay time is predetermined in the system so that the isochronous communication packet transmitted from the transmission side can be effectively processed (for example, display processing) on the reception side. In this state, the isochronous communication packet is output from the transmission-side isochronous communication FIFO memory 122 to the reception-side application I / F (corresponding to the digital video cassette recorder I / F 120). It is determined on the basis of the time.
In the present embodiment, the allowable maximum delay time is 450 μs based on the IEC61883 standard. The allowable maximum delay time is arbitrarily determined according to the type of system.
[0040]
The late decision circuit 204 compares the time indicated by the cycle time with the time indicated by the time stamp at the timing when the upper 13 bits of the cycle time are counted up (counts up every 125 μs), If it is later than the time indicated by the time stamp, it is determined to be late, otherwise it is determined not to be late, and the rate determination result is output to the transmission decision circuit 205.
Here, it is determined that the rate is from the timing at which a pulse corresponding to the NT signal output from the nominal timing generation circuit 200 is generated until DVCR data for one packet corresponding to the pulse is read from the RAM 211. In the case where the allowable time exceeds the allowable maximum delay time of 450 μs.
[0041]
When the rate determination result input from the rate determination circuit 204 indicates a rate, the transmission decision circuit 205 switches the switch SW_FourThe DVCR data for one isochronous communication packet input from is not output to the pre-reception processing / post-transmission processing circuit 123 shown in FIG. Thereafter, the transmission decision circuit 205 switches the switched switch SW._FourThrough the next bank PB₁, PB₂, PB_ThreeAnd PB_FourWhether or not to transmit the DVCR data input from is determined based on the rate determination result.
In this case, the transmission decision circuit 205 sends the next bank PB₁, PB₂, PB_Three, PB_FourIs empty, or the register NT-reg corresponding to the next bank₁, NT-reg₂, NT-reg_Three, NT-reg_FourIf the NT time is not stored, the dummy packet is output to the pre-reception processing / post-transmission processing circuit 123.
Here, the dummy packet is a packet composed of a 1394 header, a header CRC, a CIP header 1, a CIP header 2, and a data CRC, excluding data, among the isochronous communication packets shown in FIG.
[0042]
On the other hand, if the rate determination result input from the rate determination circuit 204 does not indicate a rate, the transmission determination circuit 205 switches the switch SW_FourThe DVCR data for one isochronous communication packet input from is output to the reception pre-processing / post-transmission processing circuit 123 at the subsequent stage.
[0043]
[Pre-reception / post-transmission processing circuit 123]
The pre-reception processing / post-transmission processing circuit 123 sets DVCR data in the data area (Data) shown in FIG. 2 at the time of transmission, adds a 1394 header, a CIP header 1, a CIP header 2 and a data CRC, and performs isochronous communication. A packet is generated and output to the link core 101.
Here, the transmission decision circuit 205 of the rate processing circuit 121 assigns the DBC number by skipping one to the isochronous communication packet next to the isochronous communication packet that was determined to be late and was not transmitted.
[0044]
The pre-reception processing / post-transmission processing circuit 123 receives the isochronous communication packet transmitted through the IEEE 1394 serial bus BS via the link core 101 at the time of reception, and receives the 1394 header, the CIP header 1, 2 and the like of the received packet. The contents are analyzed, the data is restored, and the DVCR data is stored in the FIFO memory 122 for isochronous communication.
[0045]
Operation when sending packets for isochronous communication
The operation of the DVCR signal processing circuit 1 when transmitting an isochronous communication packet will be described below.
Based on the output control signal from the controller 210 of the isochronous communication FIFO memory 122 shown in FIG. 3, DVCR data having a 4-bit data width is sent from the digital video cassette recorder 40 to the digital video cassette recorder I / F 120. Is output.
The DVCR data is converted into DVCR data having a data width of 32 bits in the digital video cassette recorder I / F 120, and the converted DVCR data is output to the FIFO memory 122 for isochronous communication.
The frame pulse signal FR is output from the digital video cassette recorder 40 to the nominal timing generation circuit 200 of the late processing circuit 121 via the digital video cassette recorder I / F 120 in synchronization with the DVCR data.
[0046]
The DVCR data for one isochronous communication packet is sent to the switch SW based on the write switching signal from the controller 210._ThreeSelected by the bank PB of the RAM 211₁~ PB_FourIs written to any bank.
Bank PB₁~ PB_FourThe DVCR data written to the switch SW is based on the read switching signal from the controller 210._FourIs output to the transmission decision circuit 205.
[0047]
In parallel with the above-described DVCR data processing, the following rate determination processing is performed in the rate processing circuit 121.
That is, using the frame pulse signal FR from the digital video cassette recorder I / F 120 and the nominal (Nominal) initial value and nominal step value read from a predetermined register of the CFR group 111, the nominal timing generation is performed. The circuit 200 generates a nominal timing (NT) signal and outputs the NT signal to the sampling circuit 201.
Next, in the sampling circuit 201, the time indicated by the cycle time is sampled at the timing when the pulse is generated in the NT signal, and the sampled time is set as the NT time and the switch SW.₁Is output.
Next, switch SW₁NT time output to the switch SW based on the switching signal for writing from the controller 210₁Selected NT-reg₁~ NT-reg_FourIs written to.
At this time, switch SW₁And switch SW_ThreeAre switched in conjunction with each other based on a switching signal for writing.
Therefore, register NT-reg₁~ NT-reg_FourIn each bank PB₁~ PB_FourNT time corresponding to the DVCR data stored in is stored.
[0048]
Next, register NT-reg₁~ NT-reg_FourThe NT time written to the switch SW is changed based on the read switching signal from the controller 210.₂Is read out and output to the adder circuit 203.
Then, the adding circuit 203 adds the read NT time and the allowable maximum delay time 450 μs read from the memory 202, and outputs the result of the addition to the rate determining circuit 204 as a time stamp.
[0049]
Next, the rate determination circuit 204 compares the time indicated by the cycle time with the time indicated by the time stamp every 125 μs at the timing when the upper 13 bits of the cycle time are counted up, and the time indicated by the cycle time is time stamped. If the time is later than the time indicated by, it is determined to be late, otherwise it is determined not to be late, and the rate determination result is output to the transmission decision circuit 205.
[0050]
Next, in the transmission determination circuit 205, when the rate determination result input from the rate determination circuit 204 indicates a rate, the switch SW_FourThe DVCR data for one isochronous communication packet input from is not output to the pre-reception / post-transmission processing circuit 123 shown in FIG. Thereafter, in the transmission decision circuit 205, the switched switch SW_FourThrough the next bank PB₁, PB₂, PB_ThreeAnd PB_FourWhether or not to transmit the DVCR data input from is determined based on the rate determination result.
In this case, the transmission decision circuit 205 sends the next bank PB₁, PB₂, PB_Three, PB_FourIs empty, or the register NT-reg corresponding to the next bank₁, NT-reg₂, NT-reg_Three, NT-reg_FourIf the NT time is not stored, the dummy packet is output to the pre-reception processing / post-transmission processing circuit 123.
[0051]
On the other hand, in the transmission determination circuit 205, when the rate determination result input from the rate determination circuit 204 does not indicate a rate, the switch SW_FourThe DVCR data for one isochronous communication packet input from is output to the reception preprocessing / posttransmission processing circuit 123 at the subsequent stage.
The 1394 header, CIP header 1 and CIP header 2 and data CRC shown in FIG. 2 are added to the DVCR data to generate an isochronous communication packet. The isochronous communication packet is linked to the link core 101, the physical layer circuit 20 And output to the destination node via the IEEE 1394 serial bus BS.
[0052]
Operation when receiving packets for isochronous communication
When the DVCR signal processing circuit 1 receives the isochronous communication packet, the received isochronous communication packet is output to the pre-reception processing / post-transmission processing circuit 123 via the link core 101 and the demultiplexer 110 shown in FIG. The
Then, in the pre-reception / post-transmission processing circuit 123, the contents of the isochronous communication packet such as the 1394 header and the CIP headers 1 and 2 are analyzed and restored, and the DVCR data is stored in the isochronous communication FIFO memory 122. Later, it is output to the digital video cassette recorder 40 via the digital video cassette recorder I / F 120.
[0053]
As described above, according to the DVCR signal processing circuit 1, when transmitting an isochronous communication packet, the earliest time at which transmission of the DVCR data is permitted for each DVCR data for one isochronous communication packet. Is generated using the nominal timing generation circuit 200 and the sampling circuit 201, and an allowable maximum delay time of 450 μs is added to the NT time, thereby obtaining the latest time at which the transmission of the DVCR data is permitted. Generate the timestamp shown. And the bank PB of the RAM 211₁~ PB_FourBy comparing the time stamp corresponding to the read DVCR data with the cycle time at the timing when the DVCR data for one isochronous communication packet is read out, the transmission of the isochronous communication packet including the DVCR data is delayed. The DVCR data is output to the pre-reception / post-transmission processing circuit 123 shown in FIG. 1 only when the rate is not reached.
Therefore, according to the DVCR signal processing circuit 1, the rate determination can be performed not in units of frames but in units of DVCR data for one isochronous communication packet. As described above, the controller shown in FIG. Even when the output timing of the DVCR data from the digital video cassette recorder 40 varies based on the output control signal from 210, the rate can be determined accurately.
[0054]
Further, according to the DVCR signal processing circuit 1, the controller 210 shown in FIG. 3 controls the output of the DVCR data of the digital video cassette recorder 40 using the output control signal so that the RAM 211 does not overflow. The RAM 211 can be prevented from overflowing.
[0055]
The present invention is not limited to the embodiment described above.
For example, in the above-described embodiment, the case where transmission data is input from the digital video cassette recorder 40 shown in FIG. 1 is exemplified. However, the application for outputting the transmission data is not particularly limited. This is particularly effective when using an application whose output timing varies.
[0056]
In the above-described embodiment, as shown in FIG. 1, the DVCR signal processing circuit 1 provided with the asynchronous communication system circuit is illustrated in addition to the isochronous communication system circuit. It does not have to be provided. In this case, in FIG. 1, the isochronous communication packet from the link core 101 is unconditionally output to the pre-reception processing / post-transmission processing circuit 123.
[0057]
In the above-described embodiment, in the late processing circuit 121 shown in FIG. 3, the adding circuit 203 for adding the allowable maximum delay time is added to the register NT-reg.₁~ NT-reg_FourThe adder circuit 203 is added to the register NT-reg.₁~ NT-reg_FourIt may be provided in the previous stage.
[0058]
In the present invention, IEEE 1394 is exemplified as the communication bus. However, as long as the communication bus has an isochronous communication mode, the present invention can be applied to other communication buses.
[0059]
【The invention's effect】
  As described above, according to the signal processing circuit and the method of the present invention, for example, an applicationI / FEven when the timing for inputting the transmission data fluctuates from the above, the rate processing can be appropriately performed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a DVCR signal processing circuit according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a basic configuration example of an isochronous communication packet.
FIG. 3 is an internal configuration diagram of the late processing circuit and the isochronous communication FIFO memory shown in FIG. 1;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... DVCR signal processing circuit, 10 ... Link layer circuit, 20 ... Physical layer circuit, 30 ... Microcomputer, 40 ... Digital video cassette recorder, 101 ... Link core, 102 ... Microcomputer I / F, 104 ... FIFO memory for transmission, 105 ... FIFO memory for reception, 106 ... Outbound circuit, 107 ... Auto response circuit, 108 ... FIFO memory for transmission, 109 ... Inbound circuit, 110 ... Demultiplexer, 111 ... CFR group, 112 ... Link Core 113 113 TSR group 120 Digital video cassette recorder I / F 121 Late processing circuit 122 Isochronous FIFO memory 123 123 Pre-reception / post-transmission processing circuit 200 Nominal timing generation Circuit, 2 1 ... sampling circuit, 202 ... memory, 203 ... adder circuit, 204 ... rate determination circuit, 205 ... transmission decision circuit, 211 ... RAM, 210 ... controller

Claims (7)

In a signal processing circuit that transmits a packet at a predetermined time interval from its own node to another node connected via a serial interface bus,
A timer for determining a reference time;
First storage means to which transmission data whose input timing is variable is input, and writing and reading are performed in units of a plurality of second blocks obtained by dividing the first block defined in the transmission data; ,
A reference timing signal for inputting a synchronization signal indicating a break of the first block in the transmission data and transmitting the second block as a packet based on the synchronization signal and a reference time indicated by the timer A transmission time instruction data generating means for generating a time stamp data by adding a predetermined delay time to the reference timing signal, and outputting it as transmission time instruction data;
A rate determining circuit that determines whether or not the latest time at which transmission of the packet is permitted has elapsed when transmitting the packet;
When the late determination circuit compares the reference time with the transmission time instruction data and determines that the latest time has not elapsed, the second block stored in the first storage means is The second packet stored in the first storage means when the late determination circuit determines that the latest time has passed, and transmits the packet to the other node via the serial interface bus. And a transmission decision circuit that does not transmit the packet having a block to the other node via the serial interface bus. The transmission time instruction data generating means includes a second memory means for storing said reference timing signal,
The reference timing signal corresponds to a plurality of second blocks stored in the first storage unit, and indicates the earliest time at which transmission of the packet is permitted for each packet. Signal processing circuit. A timer for determining a reference time;
First storage means to which transmission data whose input timing is variable is input, and writing and reading are performed in units of a plurality of second blocks obtained by dividing the first block defined in the transmission data; ,
A reference timing signal for inputting a synchronization signal indicating a break of the first block in the transmission data and transmitting the second block as a packet based on the synchronization signal and a reference time indicated by the timer A transmission time instruction data generating means for generating a time stamp data by adding a predetermined delay time to the reference timing signal, and outputting it as transmission time instruction data;
Second storage means for storing the reference timing signal ;
Reading means for reading out the reference timing signal corresponding to the read second block from the second storage means when reading the second block from the first storage means;
It is compared with the reference time indicated by the transmission time instruction data and the timer, signal processing circuit and a transmission determining means for determining whether to transmit the first and the second read from the storage means of the block . The first storage means has a plurality of banks each storing the second block,
The second storage means has a plurality of registers respectively corresponding to the plurality of banks,
4. The signal according to claim 3, further comprising a control unit configured to control the switching of the bank and the switching of the register in association with each other during a write operation and a read operation of the first storage unit and the second storage unit. Processing circuit. The transmission data is a video signal,
The synchronization signal is a frame synchronization signal;
The first block is a frame;
The signal processing circuit according to claim 3, wherein the second block is a video signal set in each isochronous communication packet. In a signal processing method for transmitting packets at a predetermined time interval from a local node to another node connected via a serial interface bus,
A step of inputting transmission data whose input timing is variable, and writing to the first storage means in units of a plurality of second blocks obtained by dividing the first block defined in the transmission data;
Reference when you enter a synchronization signal indicating a break of the first block in said transmission data, the synchronization signal and the timer on the basis of the reference time indicated by the transmit and the second block to the packet Generating a timing signal, adding a predetermined delay time to the reference timing signal to generate time stamp data, and outputting as transmission time instruction data;
Storing the reference timing signal in a second storage means;
Reading the reference timing signal corresponding to the read second block from the second storage means when reading the second block from the first storage means;
When transmitting the second block as the packet, and determining whether or not elapsed the latest time that the transmission of the packet is permitted,
When comparing the reference time and the transmission time indication data and determining that the latest time has not elapsed, the packet is transmitted to the other node via the serial interface bus, and the latest time And a step of not transmitting the packet to the other node via the serial interface bus when it is determined that elapses. The signal according to claim 6, wherein, for each packet, the transmission time indication data of the packet is compared with a reference time to determine whether or not the latest time at which transmission of the packet is permitted has elapsed. Processing method.

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