JP3854697B2 - Receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a preferred receiving apparatus used in a digital video camera.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the development of digital technology, various devices have been developed to reduce the data amount by encoding various types of data and transmit at a relatively low transmission rate. . For example, in a digital VTR that records image data on a storage medium such as a magnetic tape, there is a standard for compressing input image data of about 124 Mbps to about 1/5 of 25 Mbps, and recording and reproducing the data on the magnetic tape. It has been enacted.
[0003]
In a digital VTR based on such a standard, the input data is quantized after DCT conversion, and the quantized data is subjected to variable length coding by Huffman coding or the like, thereby compressing the data and further quantizing the data. The quantization step at that time is varied based on various parameters, or rate control is performed so that the amount of data after variable length coding is constant. The processed data is subjected to error detection / correction processing using, for example, a Reed-Solomon code, via a memory, and an inner code and an outer code are added and recorded on a storage medium such as a magnetic tape. The
[0004]
The digital VTR can perform digital dubbing using a digital data transfer format established in IEEE (hereinafter referred to as IEEE 1394). The configuration will be described with reference to FIG. In FIG. 5, a transmission-side digital VTR (hereinafter referred to as DVCR1) 200 in digital dubbing receives digital data whose rate is controlled so that the amount of data after the variable length coding is constant as a digital interface unit ( (Hereinafter referred to as DIF1) 202. As shown in FIG. 6, these data constitute one block of 80 bytes in which 3-byte ID data is added to 77-byte valid data. In FIG. 6, ID0 is a data type (header, subcode, video AUX, audio, or video data), ID1 is a track number (0 to 9 for NTSC, 0 to 11 for PAL), and ID2 is a block number. Is attached.
[0005]
The first 1 byte of the valid data 77 bytes includes a STA flag indicating error correction and error correction status in the upper 4 bits, and a QNo. Indicating the quantization level in the lower 4 bits. Is written. These data are composed of one header block, two subcode blocks, three video AUX blocks, nine audio blocks, and 135 video blocks for each track. Usually, the DVCR1 (200) on the transmission side transmits, for example, the block data as a DIF block and sequentially transmits the 6DIF block (480 bytes) as one packet to the DIF1 (200).
[0006]
In the transmission side DIF1 (200), communication is performed in a predetermined communication cycle (125 us), and data having a time axis such as the header data, subcode data, video AUX data, video data, and audio data is constant. Isochronous (synchronous) communication in which the transfer bandwidth is guaranteed at the data rate, and control data such as a control command is asynchronously (asynchronously) communicated irregularly as necessary.
[0007]
The packet format of the isochronous transfer is composed of 12 + 4 × N bytes in total as shown in FIG. a is a length field, which defines the byte length of the data field following the header. Reference numeral b denotes a channel number field, which gives a logical number to packet data transfer using an 8-bit value. On the receiving side, necessary isochronous data is fetched by referring to the channel number. c is a tCode field indicating that this packet is an isochronous transfer. d is a sy field, which is used for exchanging synchronization information between the source and destination used by the application software.
[0008]
e is a header CRC field, which is an error detection code for a, b, c, and d. f is a data field that stores the isochronous data and header data called a CIP header. g is a data CRC, which is a packet error detection code. The packetized data is serially transferred to the receiving side using the IEEE 1394 cable 204 of FIG. A receiving-side digital interface unit (hereinafter referred to as DIF2) 206 receives the isochronous data, performs predetermined processing, extracts the video data from the data field of FIG. (Hereinafter referred to as DVCR2) 208. In DVCR2 (208), an error correction code is added to the received data and recorded on the magnetic storage medium.
[0009]
FIG. 8 shows a detailed circuit configuration on the receiving side. A is DIF2 (206) shown in FIG. 5, and B is DVCR2 (208). Reference numeral 1 denotes a serial data input terminal from the IEEE 1394 cable 204, 3 denotes an S / P conversion circuit for converting the serial data into parallel data, and the conversion timing is controlled by the first control circuit 13. Reference numeral 5 denotes a random access memory, in which received data output from the S / P conversion circuit 3 is written in units of packets by the write enable control from the first control circuit 13. Reference numeral 7 denotes an error detection circuit for the received data, which performs error detection using the 4-bit CRC data shown in g of FIG. Reference numeral 9 denotes a delay circuit for synchronizing the error detection result with the timing at which the packet data is read out. A delay circuit 11 delays the write enable output from the first control circuit 13 until the packet data writing is completed. A first control circuit 13 is controlled by the main microcomputer 15 to control the circuit A. A main microcomputer 15 controls the entire system.
[0010]
Reference numeral 17 denotes a latch which delays the signal supplied from the delay circuit 11 by one cycle and supplies the signal to the random access memory 5 as a read enable and supplies the random access memory 23 as a write enable to the mask circuit 19. The mask circuit 19 is supplied with an error signal from the delay circuit 9 at the same time, and if there is an error in the packet data read from the random access memory 5 (not shown), the write enable of the random access memory 23 is masked. Then, writing to the random access memory 23 is prohibited. Reference numeral 21 denotes a latch for matching the data sent from the random access memory 5 with the write enable timing supplied from the mask circuit 19.
[0011]
The random access memory 23 has a capacity of, for example, three frames, and is bank-controlled by the second control circuit 25 so that writing and reading do not cause overtaking. The second control circuit 25 is controlled by the main microcomputer 15 similarly to the first control circuit 13. A recording / reproduction processing circuit 27 is controlled by the second control circuit 25 and supplies a read enable to the random access memory 23 to read data. Since the read data is DIF-transferred data and has already been compression-encoded, no new encoding process is performed. Although not shown, encoding for error detection and correction, formatting for recording, 24/25 modulation, electromagnetic conversion processing, and the like are performed by the recording / reproducing processing circuit 27 and recorded on the magnetic tape 29.
[0012]
Here, the operation of writing the data transferred by DIF into the random access memory 23 will be described with reference to FIGS. FIG. 9 shows a screen image, which is divided into five (i = 0, 1, 2, 3, 4) in the horizontal direction and 10 (j = 0, 1, 2,..., 9) in the vertical direction. . Here, j represents the track number on the recording tape. Each of the divided blocks is called a super macro block (hereinafter referred to as SMB), and its detailed configuration is shown in FIG.
[0013]
In FIG. 10, the SMB is composed of 27 DIF blocks (k = 0, 1, 2,..., 26) excluding ID data. Therefore, the position of each DIF block in FIG. 9 can be represented by a macroblock B (i, j, k). Here, since the DIF-transferred data is in the order of shuffling at the time of compression encoding, for example, {B (2, 2, 0), B (1, 6, 0), B (3 , 8, 0), B (0, 0, 0), B (4, 4, 0)} are written in the black portion of FIG. Hereinafter, {B (2, 2, 1), B (1, 6, 1), B (3, 8, 1), B (0, 0, 1), B (4, 4, 1)}, ... Are accessed in units of 5 DIF blocks. The data thus written is read in the order of track numbers without being shuffled, processed by the recording / reproducing processing circuit 27, and recorded on the magnetic tape 29.
[0014]
On the other hand, FIG. 11 shows the configuration and operation during playback. In FIG. 11, the same components as those in FIG. In FIG. 8, the reproduction data from the magnetic tape 29 is supplied to the recording / reproduction processing circuit 27. The recording / playback processing circuit 27 performs deformatting and 25/24 demodulation, and writes to the random access memory 23 under the control of the second control circuit 25. The decoding processing circuit 31 performs decompression / decoding processing of the reproduced compressed data. As described with reference to FIG. 9, the processing here is performed in units of five consecutive macroblocks obtained in the order in accordance with the same shuffling rules as in the compression / encoding processing. The data subjected to the decompression / decoding process is supplied from the image data output terminal 33 to the external output device. The main microcomputer 15 controls the entire system as described above.
[0015]
[Problems to be solved by the invention]
As described above in the conventional example, the processing unit for DIF transmission / reception data is 6 DIF blocks, whereas the processing unit for decoding is 5 macroblocks (corresponding to 5 DIF blocks). For this reason, when an error is mixed in the transmission path, the following problem occurs due to the write control of the random access memory 23 when the error is detected.
[0016]
FIG. 12 explains the operation in which this problem occurs. i is the DIF reception data or the decoding processing unit for the reproduction data once recorded and then reproduced, and j is the DIF reception data or recording / reproduction data. k is a processing unit of the DIF reception data, m is an error flag obtained as a result of CRC error check of the DIF reception data in units of one packet, and “L” indicates that an error is mixed. Show. In this case, data 0 to 5 is the latest data, and the data in the random access memory 23 is updated. However, since data 6 to 11 is an error packet, writing to the random access memory 23 is prohibited. Old data at least several frames ago remains unupdated. For this reason, when the decoding process is performed in the decoding processing unit i, new data and old data are mixed in the decoding periods Dec1 and Dec2, and the continuity of encoding / decoding is lost, and decoding is performed. This causes the image data to deteriorate significantly.
[0018]
[Means for Solving the Problems]
Receiving apparatus according to the present invention, for example, to detect an error in the packets received and receiving means, by said receiving means for receiving a packet having a plurality of block data including the first data indicating the state of the error correction The first data in the block data included in the packet received by the receiving means is determined in accordance with whether or not an error has occurred in the packet received by the detecting means and the receiving means . Replacement means for replacing the data with the data, and decoding means for performing decoding processing using a number of block data different from the number of block data included in the packet, wherein the decoding means When the second data is included in at least one block data of a plurality of block data necessary for processing, it is necessary for the decoding processing And performing said decoding using the other plurality of block data in place of several block data.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows an embodiment of the present invention. The same components as those in FIG. 8 are denoted by the same reference numerals and the same operations are performed, so that the description thereof is omitted.
First, the STA replacement circuit indicated by 35 is a circuit that best represents the feature of the present invention, and is supplied with DIF reception data from the circuit A, an error flag, and a read enable. Next, the configuration and operation of the STA replacement circuit 35 will be described with reference to FIG. In FIG. 2, a terminal 3051 is a read enable signal terminal supplied via the latch 17 in FIG. 1, and this enable signal is supplied to the edge detection circuit 3503. An edge detection circuit 3503 detects the falling edge of the enable signal and supplies it to the counter 3505. The counter 3505 operates with an internal clock and is reset in synchronization with the falling edge of the enable signal.
[0022]
The decoder 3507 decodes the counter value, outputs a signal indicating the position of the STA in FIG. 6 in the input data string, and supplies the signal to the OR circuit 3511. A terminal 3509 is an input terminal for a transfer error flag signal for each packet, and this flag signal is input to the OR circuit 3511. The OR circuit 3511 is configured to output the “L” signal only when there is a transfer error and the position of the STA in the data string, and the output is supplied to the switch 3515. When the supplied signal is at the “L” level, a pattern indicating that there is an error in the upper 4 bits of bit 7 to bit 4 corresponding to the STA position in the received data 1 byte is selected, for example, 1 byte data in which “1110” is replaced ( The switch 3515 is connected to the b side), and the others (the switch 3515 is connected to the a side) operate so that the received data itself is selected. The selected data is supplied to the data output terminal 3517.
[0023]
FIG. 3 is a timing chart of the operation described in FIG.
In FIG. 3, a is an internal clock. b is an enable signal supplied from the latch 17 of FIG. 1, and is asserted to "L" in units of one packet. c is a falling edge of the enable signal having a width of 1 clock, and is output from the edge detection circuit 3503. d is a counter value of the counter 3505, and 80 bytes of one DIF block are repeated and counted for 6 DIF blocks. e indicates the timing at which the above-described counter value is decoded by the decoder 3507, the STA data position for each DIF block is detected, and "L" is output.
[0024]
f is an error signal, and the presence / absence of an error is determined for each packet. f indicates “H” indicating no error and “L” indicating an error. h represents the data supplied to the data output terminal 3517 in FIG. 2 when the above error occurs, where RP is the STA position, and the error pattern because an error has occurred. STA data indicating
Since the data processed as described above is naturally the same data once recorded and then reproduced, the same processing is performed as the operation of the expansion / decoding processing.
[0025]
Next, the configuration and operation of the data decompression / decryption processing unit will be described with reference to FIG.
In FIG. 4, a terminal 1201 is an input terminal to which data output from the data output terminal 3517 of FIG. 2 is input. This input data is supplied to the decryption processing circuit 1205 and the STA check circuit 1203. Further, the third control circuit 1207 issues a request for reading data to the random access memory 23 of FIG. 1 and supplies the request to the second control circuit 25 of FIG. 1, and arbitration including requests from other processing circuits is performed. Only when the access to the random access memory 23 is supplied, an acknowledge (hereinafter referred to as Ack) is returned. Terminal 1213 is the Ack input terminal.
[0026]
The third control circuit 1207 can know the timing of the STA check because the data arrival timing is constant from the returned Ack. By supplying the STA check timing to the STA check circuit 1203, the STA check is executed. This STA check result is supplied to the decryption processing circuit 1205 and the third control circuit 1207. The decoding processing circuit 1205 stops the operation of the decoding processing circuit 1205 and inputs the next 5 macroblock data when the STA of any of the macroblocks in the consecutive 5 macroblocks has an error pattern. Wait for. If the STA has an error pattern, the third control circuit 1207 regenerates an address indicating the same location of the previous frame or field and issues a request to access the random access memory 23 again. As a result, interpolation is performed with 5 macroblock data of the previous frame or field.
[0027]
Of course, in this embodiment, when there is an error, the STA of the DIF received data is replaced with an error pattern, and then all data is written to the random access memory 23 in units of DIF blocks. However, the same effect as described above can be obtained even if only the STA data of the block data corresponding to the DIF block data in the memory area at the time of writing is rewritten.
[0028]
Further, the data written from the STA replacement circuit 35 to the random access memory 23 can be directly read and decoded without being recorded or reproduced.
[0029]
The functional blocks such as the circuits in FIGS. 1, 2, and 4 may be configured in hardware, or may be configured in a microcomputer system including a CPU, a memory, and the like as illustrated in the drawings. When configured in a microcomputer system, the memory constitutes a storage medium according to the present invention, and a program for executing the processing of each block described above is stored in the storage medium.
As the storage medium, a semiconductor memory such as ROM or RAM, an optical disk, a magneto-optical disk, a magnetic medium, or the like may be used, and these are used as a CD-ROM, a floppy disk, a magnetic tape, a nonvolatile memory card, or the like. May be.
[0030]
As described above, according to the embodiment of the present invention , packet data including information data and error data indicating an error state of the information data is input, a packet data transmission error is detected, and the detection result Accordingly, the error data in the packet data is converted into data of a predetermined error pattern, so that a packet having an error can be known. Thereby, data processing can be performed appropriately. For example, by taking appropriate measures such as not processing a packet with an error, it is possible to reduce degradation of signal quality. This is particularly effective when data processing is performed in units of data length shorter than that of the packet when the packet data is composed of a plurality of predetermined fixed-length block data and each block data includes the error data. is there. Also, for example, when image data is handled as information data, if an error pattern is detected in the input image data, processing is performed with the image data of the previous frame or field period to prevent image deterioration due to transmission errors. You can
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a configuration diagram of the STA replacement circuit in FIG. 1;
FIG. 3 is a timing chart showing the operation of the STA replacement circuit.
FIG. 4 is a block diagram illustrating a configuration of a decoding processing unit.
FIG. 5 is a block diagram showing a configuration of a dubbing system of a VTR that transmits / receives digital data via a conventional digital interface.
FIG. 6 is a block diagram of block data.
FIG. 7 is a configuration diagram showing a transfer format on a serious bus.
FIG. 8 is a block diagram showing a configuration of a receiving side in the system.
FIG. 9 is a configuration diagram for explaining a shuffling order in a screen image at the time of compression / decompression.
FIG. 10 is a configuration diagram showing a configuration of a super macroblock and a write processing timing of DIF received data.
FIG. 11 is a block diagram illustrating a configuration of a reproduction processing unit in the system.
FIG. 12 is a configuration diagram for explaining a processing unit for transmission / reception data and a processing unit for decoding processing;
[Explanation of symbols]
15 Main microcomputer 23 Random access memory 25 Second control circuit 27 Recording / reproduction processing circuit 29 Magnetic tape 35 STA replacement circuit 1203 STA check circuit 1205 Decoding processing circuit 1207 Third control circuit 3503 Edge detection circuit 3505 Counter 3507 Decoder 3511 OR circuit 3515 switch

Claims (4)

Receiving means for receiving a packet having a plurality of block data including first data indicating an error correction state;
Detecting means for detecting an error in the packet received by the receiving means ;
Depending on whether or not an error in the packet received is generated by the receiving means, replacing said first data in the block data included in the packet received by the receiving means to the second data Replacement means to
Decoding means for performing a decoding process using a number of block data different from the number of block data included in the packet;
In the decoding means, when the second data is included in at least one block data of a plurality of block data necessary for the decoding process, a plurality of block data necessary for the decoding process are stored. Instead, the decoding apparatus performs the decoding process using a plurality of other block data.   The receiving apparatus according to claim 1, wherein the first data is a STA flag. It said second data receiving device according to claim 1 or 2, characterized in that indicating that there is error. Said another plurality of block data, the receiving apparatus according to either the claim 1, wherein 3 in that also other frames is a block data field.

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