JP2898212B2 - Image decoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image decoding circuit, and more particularly to a moving image decoding circuit which considers data errors and code errors.
e Expert Group, an international standard for media-integrated moving image compression) 2.

[0002]

Description of the Related Art: Technical Report of the Institute of Television Engineers of Japan, Vol. 1
8, No. 39, pages 37 to 42, "International Standardization Trends in Multimedia Multiplexing", describe system streams in MPEG2, which is an international standard for video coding.

[0003] In relation to the operation when an error occurs in the transmission path, FIG. 4 in the above-mentioned document shows an MPEG2 transport stream (Stream).
Is described. A transport error indicator (Transport error) is added to a link header (Link Header) in FIG.
(1) is set in the field of “indicator”. There is no literature describing how to handle a packet in which the transport error indicator field is set to '1'.

On the other hand, in the moving picture coding system based on MPEG2, a unique word called a start code is periodically provided in order to shorten the time during which decoding becomes impossible due to the occurrence of an error. It does not occur except at the position. According to this rule, even if the decoding circuit temporarily makes decoding impossible due to an error, a correct decoding operation can be performed from the next start code. Since a moving image signal generally has a strong temporal correlation, a relatively good image can be generated by interpolation of a part that could not be decoded and a part that could be decoded correctly.

[0005] However, when data containing an error is input to the decoding circuit, the decoding circuit may generate a wrong image with extremely deteriorated image quality. From these facts, if an error is detected on the transmission path, it is useful to transmit the occurrence of the error to the decoding circuit and not to input the data containing the error to the decoding circuit to improve the image quality.

In MPEG2, when "1" is set in the transport error indicator field, the occurrence of an error is notified to a decoding circuit, and PES (packetized elementary stream) packet data of the packet is transmitted. Discarding the image without inputting it to the decoding circuit improves the image quality of the decoded image.

FIG. 2 is a block diagram of a conventional moving picture decoding circuit. This video decoding circuit includes a system decoder 201,
It comprises a video decoder 202 and an interface circuit 203. The interface circuit 203 includes the memory 20
4. Write address counter 205, read address counter 206, latch circuit 207, match circuit 208
Consists of The memory 204 is a FIFO (Fast In Fast Out) memory required to absorb a speed difference between a system decoder and a video decoder due to a difference in the amount of compression-encoded data for each picture.

[0008] From the input terminal 209 to the system decoder 20
In the transport error indicator field of the packet input to 1, "1" is set if the packet contains an error, and "0" is set if the packet does not contain an error. This system decoder 201
Is different depending on the value of the transport error indicator field.

When the transport error indicator field is "0", the payload of the packet is written to the memory 204. The memory 204 operates as a FIFO memory together with the write address counter 205 and the read address counter 206. If the transport error indicator field is "1", the system decoder 201 discards the payload of the packet and generates an error notification signal. The error notification signal is input to the latch circuit 207, and the value of the write address counter at the time when the error notification signal occurs is held in the latch circuit 207.

When the value of the read address counter matches the value of the latch circuit 207, the coincidence circuit 208 outputs a control signal to the video decoder 202 and a reset signal to the latch circuit 207. Upon receiving the control signal, the video decoder 202 does not perform a decoding operation, including searching for a start code, until a start code is found. As a result, only error-free data is decoded.
Thus, the quality of the output decoded image is improved.

[0011]

However, in the above-described circuit configuration, a circuit for generating an error notification signal for the system decoder 201, a latch circuit 207 and a coincidence circuit 208 for the interface circuit 203, and a circuit for the video decoder 202 A circuit for receiving a control signal is required, and the circuit configuration is complicated.

Further, when the system decoder 201 and the video decoder 202 are realized by LSI, there is a problem that the number of input / output pins increases.

[0013]

SUMMARY OF THE INVENTION Accordingly, the present invention provides a system decoder for analyzing input image encoded data, an interface means comprising a memory circuit for temporarily holding the analyzed image encoded data, and a memory circuit for holding the analyzed image encoded data. An image decoding circuit including a video decoder that decodes encoded moving image encoded data solves the above problem with the following characteristic configuration.

That is, when a data error is detected from the input image coded data, the system decoder does not output the image coded data to the interface means.
An error notification unit is provided for outputting the error notification unique word to the memory circuit of the interface unit.

[0015]

According to the image decoding circuit of the present invention, when a data error is detected in the input image coded data, the image signal is not generated by controlling the interface circuit by generating an error notification signal as in the related art. Instead of outputting coded data to the interface means, it outputs a unique word for error notification and stores it in the memory circuit. This unique word for error notification is given to the video decoder, so the configuration of the interface circuit is simpler than in the past. Can be

There is no need to provide the error notification signal to the interface circuit separately from the image encoded data as in the prior art. Moreover, since a unique word for error notification is notified instead of the image encoded data, there is no need to provide a complicated generating circuit, so that the configuration is simplified.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment in which the present invention is applied to a moving picture decoding circuit will be described with reference to the drawings.

FIG. 1 is a functional block diagram of the moving picture decoding circuit of the embodiment. In FIG. 1, a system decoder 102 on the input side and a video decoder 104 on the output side are connected via an interface circuit 103. The interface circuit 103 includes a memory circuit 106 including a FIFO memory, a write address counter 107, and a read address counter 108.

The system decoder 102 includes an error detection circuit 102a comprising a microprocessor or the like.
The packet data input from the input terminal 101 is decoded, and when a data error is detected, a unique word for error notification is output. When no data error is detected, a payload is provided to the video decoder 104 via the interface circuit 103. . The video decoder 104 also includes an error notification detection circuit 104a including a microprocessor or the like for controlling the internal video decoder. The video decoder 104 outputs the decoded image data to an output terminal 105.

(Description of Operation) Packet data obtained by packetizing compressed image data is input to the input terminal 101. FIG. 3 is a diagram showing an example of the format of input packet data. In FIG. 3, one frame of the transport packet stream is 188 frames.
One frame is composed of a header part and a payload part.

The header part is a synchronization byte 31 (8 bits)
And a transport error indicator 32 (1 bit) and a payload unit start indicator 3
3 (1 bit) and transport priority 34
(1 bit) and PID (packet identification information) 35 (1
3 bits), a transport scrambling control 36 (2 bits), an adaptation field control 37 (2 bits), a continuity counter 38 (4 bits), and an adaptation field 39.

This adaptation field 39
An adaptation field length of 40 (8 bits),
Discontinuity indicator 41 (1 bit), random access indicator 42 (1 bit), elementary stream priority indicator 43 (1 bit), 5 flag 44 (5 bits), optional field 45, and stuffing byte 46.

Further, this optional field 45
Is a PCR (Program Clock Referer)
ence: system time reference value) 47 (42 bits) and OPCR (Original PCR) 48
(42 bits) and a splice countdown 49 (8
Bit) and the transport private data length 50
(8 bits) and transport private data 5
1, an adaptation field extension length 52 (8 bits), a 3 flag 53 (3 bits), and an optional field 54.

The optional field 54 contains I
tw valid flag 55 (1 bit), Itw offset 56 (15 bits), empty 57 (2 bits),
Piecewise 58 (22 bits), splice type 59 (4 bits) and DTS (Decoding
Time Stamp: decryption time management information) ne
xt au60 (33 bits).

The transport packet stream is a sequence of packets consisting of a header and a payload, and the header has a transport error indicator field indicating whether or not the payload contains an error. In this field, '1' is set when there is an error in the payload, and '0' is set when there is no error. The payload contains the compressed image data.

FIG. 4 is an operation flowchart of the error detection circuit 102a of the system decoder 102. The system decoder 102 first reads the packet (step S
1) Separate the header and the payload. Then read the transport error indicator field of the header,
If the transport error indicator is '0' (step S2), the payload is output (step S3)
If the transport error indicator is '1' (step S2), the payload is discarded without being output,
Instead, an error notification unique word is output (step S4). The error notification unique word is a bit string that does not appear in the compressed image data.

For example, if moving picture encoding is ISO / MPEG
2, the unique word for error notification is DIS (Draf) issued in May 1994.
At the stage of (tInternational Standard), reserved 0x000001B0 and the like are candidates. The system decoder 102 outputs data to the memory circuit 106 in synchronization with the write clock.
The address of the memory to be written is controlled by the write address counter 107. The data stored in the memory circuit 106 is input to the video decoder 104 in synchronization with a read clock output from the video decoder 104. The read address is controlled by a read address counter 108.

Although FIG. 4 is shown as an operation flowchart, it can be understood as a functional block configuration of the system decoder 102.

FIG. 5 is an operation flowchart of the error notification detection circuit 104a of the video decoder 104. This figure 5
In the video decoder 104, the memory circuit 10
6 is read (step S10), and it is determined whether the read data is a unique word for error notification (step S11). If it is not an error notification unique word, the data is decoded as usual (step S
12) Read the next data. If the read data is an error notification unique word, the decoding of the data is stopped (step S13), and the data is read continuously until the next start code is found (steps S14 to S1).
5). When the start code is found, the next data is read (step S10).

The video decoder 104 outputs the image signal of the normally decoded portion from the output terminal 105 as it is. Since the data has disappeared in the section from the time when decoding is stopped to the time when the next start code is detected, the image signal of this part is, for example, an image of the part at the same position of the image one frame before in time. Is what you do. As a result, a high-quality image can be continuously output without interruption of the output image.

Although FIG. 5 described above is shown as an operation flowchart, it can be understood as a functional block configuration of the video decoder 104.

(Effects of Embodiment) According to the moving picture decoding circuit of the above embodiment, the error notification from the system decoder 102 to the video decoder 104 is performed by the error notification unique word. The video decoder 104 can detect in which part of the input data an error has occurred without configuring a simple interface circuit 103.

If the error occurrence position can be detected, the video decoder 104 does not erroneously decode the data containing the error, so that the quality of the decoded image output from the output terminal 105 is improved. Further, since there is no need to provide a conventional error notification signal line, when the system decoder 102 and the video decoder 104 are configured by an LSI, the number of pins can be reduced as compared with the conventional case, so that the manufacturing process is simplified. In addition, it can contribute to improvement in reliability and downsizing.

Further, the present invention is very effective when applied as a moving picture decoding circuit for transmitting coded moving picture data at a low bit rate.

(Other Embodiments) (1) The above embodiment is applicable to, for example, MPEG2 image signal transmission via an ATM network.

FIG. 6 is a layer model diagram of the communication protocol. The PH 61 is a physical layer interface and receives a bit string from the transmission path 60. ATM layer 62
Receives a bit string as a cell. AAL63 is AT
M adaptation layer, collectively receives several cells, detects errors, and transmits the error detection result and the received data to H.264. Send to 22X specific layer 64. This H. The 22X specific layer 64 sets “0” or “1” in the transport error indicator of the packet header according to the error detection information.

The MPEG2 system 65 and the MPEG2 video 66 correspond to the system decoder 10 described in the above embodiment.
2. The video decoder 104 operates to output an image signal to the display device 67.

In the above embodiment, the interface circuit 1
03 has an independent configuration, but when the memory capacity is small, it is also preferable for the miniaturization that the interface circuit 103 be built in or combined with either the system decoder 102 or the video decoder 104 for miniaturization. .

(2) Also, the above-mentioned embodiment is based on MPEG2
In addition to application to storage media (MPEG1), the present invention can also be applied. In addition, still image decoding (JPE
G), and is also effective when applied to decoding of a high-definition binary image (JBIG).

(3) Further, if the transport error indicator is included in the transport packet stream of FIG. 3, there is an effect that it can be applied to other formats.

(4) In addition to the above-mentioned 0x000001B0 as a unique word for error notification, a plurality of such words may be prepared, and one of them may be selectively used to achieve the above-described effect. is there.

[0042]

As described above, according to the present invention, when a data error is detected from the input image coded data, the system decoder does not output the image coded data to the interface means but notifies an error. Error notification means for outputting a unique word for use to the memory circuit of the interface means, thereby performing a decoding operation in the case where a data error is included in the input image coded data with a very simple configuration and a good image quality. An image decoding circuit can be realized.

Therefore, the present invention is very effective when applied as an image decoding circuit for transmitting image encoded data at a low bit rate.

[Brief description of the drawings]

FIG. 1 is a functional configuration diagram of a moving image decoding circuit according to an embodiment.

FIG. 2 is a functional configuration diagram of a conventional moving picture decoding circuit.

FIG. 3 is a format diagram of packet data according to the embodiment;

FIG. 4 is an operation flowchart of the system decoder of the embodiment.

FIG. 5 is an operation flowchart of the video decoder of the embodiment.

FIG. 6 is an explanatory diagram of a use form of the moving picture decoding circuit of the embodiment.

[Explanation of symbols]

101: input terminal, 102: system decoder, 103
... Interface circuit, 104 ... Video decoder, 10
5 output terminal, 106 memory circuit, 107 write address counter, 108 read address counter.

Claims (3)

(57) [Claims] 1. A system decoder for analyzing input image encoded data, an interface means including a memory circuit for temporarily storing the analyzed image encoded data, and decoding from the image encoded data held in the memory circuit. An image decoding circuit comprising: a video decoder, wherein when the system decoder detects a data error from the input image encoded data, the system decoder does not output the image encoded data to the interface means, but outputs an error notification unique word to the interface means. An image decoding circuit comprising: an error notifying unit that outputs an error to a memory circuit of the unit. 2. The video decoder according to claim 1, further comprising an error notification detecting means for stopping a decoding operation until a next start code is detected when the data supplied from the interface means is an error notification unique word. The image decoding circuit according to claim 1, wherein: 3. The image decoding circuit according to claim 2, wherein said video decoder includes output means for outputting decoded image data of a previous frame in a section where decoding is stopped.