JP2000308052A - Method and device for receiving data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly process received data when the transmission of a program is performed by using the transmission packet of a serial/digital transfer interface by constituting a content package. SOLUTION: In a step ST1, whether or not a range is a correctable range is discriminated by performing ECC decoding. When the range is correctable, the process advances to a step ST2 and, when an ECC on/off flag is in an 'ON' state, it is discriminated that ECC is in an 'ON' state and CRC is in an 'OFF state in a step ST3. When no error is detected when the even parity of 'CRC flag' or the CRC of header data are used even when the process advances to a step ST5 from the step ST1, whether or not the 'CRC flag' is in an 'ON' state is discriminated in a step ST6. When the 'CRC flag' is the 'ON' state, it is discriminated that the ECC is in an 'OFF' state and the CRC is in an 'ON' state in a step ST7. When the 'CRC flag' is not in the 'ON', state, it is discriminated that the ECC is in an 'ON' state and the CRC is in an 'OFF' state. Therefore, the process can be carried out by accurately discriminating the 'ON' and 'OFF' states of the ECC and CRC even when the 'CRC flag' becomes erroneous information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a data receiving method and a data receiving apparatus. Specifically, when receiving a transmission packet to which either the data for error detection or the data for error detection and correction and the information indicating the use status of the data for error detection and the data for error detection and correction are added,
Information indicating the usage status of the error detection data and the error detection and correction data, an error detection result performed assuming that the error detection data is added, and an error correction performed with the error detection and correction data added Based on the processing result, it is correctly determined whether the data for error detection or the data for error detection and correction is added.

[0002]

2. Description of the Related Art Conventionally, SMPTE (Society of Motion)
The Picture and Television Engineers (American Motion Picture and Television Engineers) and the European Broadcasting Union (EBU) are studying the exchange of programs between broadcasting stations, and as a result, the EBU / SMPTE Task F
orce for Harmonized Standards for the Exchange ofP
rogramme Material as Bitstreams "has been announced.

In this announcement, essential data of a program, for example, video or audio material is regarded as essence, and information on the content of the essence, for example, the title of the program, the video system (NTSC or PAL), and the audio sampling frequency are meta-data. Data (Metadata).

Next, a content element (Content Element) is formed from the essence and the metadata, and a video or audio content item (Content item) is generated using a plurality of content elements. For example, a video clip useful as an image index collection corresponds to this. Further, a content package (Content Package) is configured from a plurality of content items and content elements. This content package corresponds to one program, and a set of content packages is called a wrapper (Wrappe
r). A proposal has been made to facilitate program exchange by standardizing means for transmitting and storing the wrapper between broadcast stations.

[0005]

In the above-mentioned announcement, only the concept of program exchange is described, but no specific method for transmitting a program is specified. For this reason, the program could not be actually transmitted as a content package as described above.

Accordingly, the present invention provides a data receiving method and a data receiving apparatus capable of correctly processing received data when a content package is formed and a program is transmitted using a transmission packet of a serial digital transfer interface. To provide.

[0007]

According to the data receiving method of the present invention, each one-line section of a video frame is divided into an end synchronization code area in which an end synchronization code is inserted, and an auxiliary data area in which auxiliary data is inserted. And a start synchronization code area into which a start synchronization code is inserted, and a payload area into which data including data of video and / or audio items is inserted, and data for error detection or error detection and correction. And a data reception method for receiving a transmission packet of a serial digital transfer interface to which information indicating the use status of the error detection data and the error detection and correction data is added. Information indicating the usage status of the error data, and errors performed with the error detection data added And output a result, on the basis of the error correction processing result performed as the error detection and correction data is added, it is to determine which of the data correction error detection data or error detection is added.

Further, the data receiving apparatus inserts a section of each line of the video frame into an end synchronization code area in which an end synchronization code is inserted, an auxiliary data area in which auxiliary data is inserted, and a start synchronization code. And a payload area into which data including video and / or audio item data is inserted. Either error detection data or error detection and correction data, and error detection data A data receiving apparatus for receiving a transmission packet of a serial digital transfer interface to which information indicating the use state of the error detection and correction data is added, and information indicating the use state of the error detection data and the error detection and correction data, The result of error detection performed assuming that the data for error detection is added, and the data for error detection and correction Determining means for determining which of the error detection data or the error detection and correction data has been added based on the result of the error correction processing performed as added, and decoding means for performing the error correction processing; And signal switching means for supplying the received data to the decoding means when the means has determined that the data for error detection and correction has been added.

According to the present invention, the result of the error correction processing performed assuming that the data for error detection and correction such as ECC is added to the received data is the correctable range, and the information indicating the use status of the data for error detection and correction. When it is determined that the data for error detection and correction is used, it is determined that the data for error detection and correction is added. Also, the result of the error correction processing performed on the assumption that the data for error detection and correction has been added cannot be corrected, and
If the result of the error detection performed assuming that the error detection data is added is correct, and if it is determined that the error detection data is being used by the information indicating the use status of the error detection data, an error occurs. When it is determined that the data for detection is added, and when it is determined that the data for error detection is not used by the information indicating the use status of the data for error detection, it is determined that the data for error detection and correction is added. Is determined.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. In the present embodiment, data such as video and audio materials are packaged and each content item (for example, a picture item (Picture Item) or an audio item (Audio Item)) is packaged.
m)), as well as packaging information about each content item, metadata about each content, and the like to form one content item (system item (S
ystem Item)), and make each of these content items a content package. Further, a transmission packet is generated from the content package and transmitted using a serial digital transfer interface.

As the serial digital transfer interface, for example, SMPTE-259M "10-bit 4: 2: 2" standardized by SMPTE
Component and 4fsc Composi
te Digital Signals -Seria
l Digital Interface ”(hereinafter“ Serial Digital Interface SDI (Serial Digita
l Interface) format) and the SMPTE-305M “Seri” standard for transmitting packetized digital signals.
al DataTransport Interface
e "(hereinafter referred to as" SDTI format ") to transmit the above-mentioned content package.

First, when the SDI format standardized by SMPTE-259M is arranged in a video frame, the digital video signal of the NTSC 525 system is
1716 (4 + 268 + 4 +) per line in the horizontal direction
1440) The word is composed of 525 lines in the vertical direction. Also, a digital video signal of the PAL625 system is 1728 (4 + 28) per line in the horizontal direction.
(0 + 4 + 1440) words and 625 lines in the vertical direction. However, it is 10 bits / word.

[0013] For each line, four words from the first word to the fourth word are used as a video signal area 144.
Indicates the end of the 0-word active video area, and is used as an area for storing a code EAV (End of Active Video) for separating the active video area and an ancillary data area described later.

Further, for each line, 268 words from the fifth word to the 272th word are used as an ancillary data area, and header information and the like are stored. Four words from the 273rd word to the 276th word indicate the start of the active video area, and a code SA for separating the active video area from the ancillary data area.
It is used as an area for storing V (Start of Active Video), and the 277th word and subsequent words are used as an active video area.

In the SDTI format, the above-mentioned active video area is used as a payload area, and the codes EAV and SAV indicate the end and start of the payload area.

Here, the data of each item is inserted into the payload area of the SDTI format as a content package and the code EAV of the SDI format is inserted.
And SAV are added to form data in a format as shown in FIG. When data in the format shown in FIG. 1 (hereinafter referred to as "SDTI-CP format") is transmitted, P / S conversion and transmission path encoding are performed and transmitted as serial data, as in the SDI format and SDTI format. You. In FIG. 1, the numbers in parentheses indicate the numerical values of the PAL625 video signal, and the numbers without the parentheses indicate the numerical values of the NTSC 525 video signal. Hereinafter, only the NTSC system will be described.

FIG. 2 shows the structure of the code EAV and the header data included in the ancillary data area.

The code EAV is 3FFh, 000h, 000
h, XYZh (h indicates hexadecimal notation, and the same applies to the following description).

In "XYZh", the bit b9 is set to "1" and the bits b0 and b1 are set to "0". Bit b8 is a flag indicating whether the field is the first field or the second field.
Is a flag indicating a vertical blanking period. Bit b6 is a flag indicating whether the 4-word data is EAV or SAV. The flag of the bit b6 is set to "1" for EAV and "0" for SAV. Bits b5 to b2 are data for performing error detection and correction.

Next, at the beginning of the header data, data for header data recognition "ADF (Ancillary data flag)"
Are fixed patterns 000h, 3FFh, 3FFh. Following this fixed pattern, “DID (Data ID)” and “S” indicating the attributes of the ancillary data area
DID (Secondary data ID) ", and fixed patterns 140h and 101h indicating that the attribute is a user application are provided.

"Data Count" is "Line Count".
Number-0 ”to“ Header CRC1 ”
This indicates the number of words up to 46 words, and the number of words is 46 words (22Eh).

"Line Number-0, Line
"Number-1" indicates the line number of the video frame. In the NTSC 525 system, these two words indicate the line numbers from 1 to 525. In the PAL system 625 system, line numbers from 1 to 625 are indicated.

"Line Number-0, Line
Number-1 followed by Line Number
er CRC0, Line Number CRC1 "
Are arranged, and this “Line Number CR”
C0, Line Number CRC1 ”is“ DI
D ”to“ Line Number-1 ”, CRC (cyclic redundancy check) for 5-word data
codes), which are used for checking transmission errors.

"Code & AAI (Authorized addr
ess identifier) indicates information such as what the word length of the payload area from the SAV to the EAV is set and what data format is used for the addresses of the sending side and the receiving side. .

[Destination Addresses]
"s" is the address of the data receiving side (transmission destination), and "S
"source Address" is the address of the data transmission side (transmission source).

The "Block Type" following the "Source Address" indicates the format of the payload area, for example, whether the payload area has a fixed length or a variable length. Compressed data is inserted. Here, SDTI-C
In the P format, for example, when a content item is generated using compressed video data (video data), a variable length block (Variable Block) is used because the data amount differs for each picture. For this reason, SD
"Block Type" in TI-CP format
Is fixed data 1C1h.

"CRC Flag" indicates whether a CRC is placed in the last two words of the payload area.

Further, "Da" following "CRC Flag"
“ta extension flag” indicates whether or not the user data packet is extended.

"Data extension fla
Following "g", a 4-word "Reserved" area is provided. Next "Header CRC 0, Head
erCRC 1 ”is a CRC for data from“ Code & AAI ”to“ Reserved 4 ”.
(Cyclic redundancy check codes), which are used for checking transmission errors. The next "Check Su
“m” is a Check Sum code for all header data, and is used for checking transmission errors.

In the payload area shown in FIG. 1, data of items such as video and audio is packaged as a variable-length block in SDTI format. FIG. 3 shows the format of a variable-length block. "Separator" and "End Cod"
"e" indicates the start and end of the variable-length block,
The value of “Separator” is “309h”, and “End”
The value of “Code” is set to “30 Ah”.

The “Data Type” indicates what item the packaged data is, and the value of the “Data Type” is, for example, “04h” in the system item (System Item). "05h" for picture items, "06h" for audio items, and "07h" for AUX items that are other data.
It is said. Note that one word is 10 bits as described above. For example, when the word is 8 bits as indicated by “04h”, the 8 bits correspond to bits b7 to b0. Further, by adding even parity of bits b7 to b0 as bit b8 and adding logically inverted data of bit b8 as bit b9, data of 10 bits is obtained. The 8-bit data in the following description is similarly converted into 10 bits.

In "Word Count", "Data
The “Dat” indicates the number of words of “Block”.
"a Block" is the data of each item. Here, the data of each item is packaged in picture units, for example, frame units, and in the NTSC system, the program switching position is set to the position of 10 lines. Therefore, in the NTSC system, as shown in FIG. 1 in
From the third line, system items, picture items,
Audio items and AUX items are transmitted in this order.

FIG. 4 shows the structure of a system item. "System ItemType" and "Wor
“d Count” is “Data Ty” of the variable-length block.
pe "and" Word Count ".

One-word "System Item B"
FECActive Fl of bit b7 of "itmap"
“ag” (ECC on / off flag) indicates whether the ECC is turned on, an error correction code such as a Reed-Solomon code is added, and the reception side performs error detection and correction processing using the error detection and correction code. This flag indicates whether or not the error detection / correction code is added when the flag is set to “1”, indicating that the error detection / correction process is performed on the receiving side using the error detection / correction code. FIG. 5 shows a case where the ECC is in the ON state. As shown by hatching, 6 bits are indicated for every 234 words of data in the payload area.
Parity, which is an error detection and correction code for words, is added, and error correction can be performed for up to three words out of 234 words. Since the parity is added in this manner, the payload area is in a vertically divided state. In addition, EC
Either C or CRC can be selected, but not both.

Here, when the data in the payload area does not have internal redundancy, for example, such as encoded data of long GOP (long GOP) or MPEG-2 or an important IT data file, the ECC is turned on. Is done. Further, for example, in the case of video data or audio data that is not compressed or has a low compression ratio and a data amount close to the original data, the ECC is turned off.

The bit b6 is a flag indicating whether or not there is information on the SMPTE Label. Here, when “1” is set, it indicates that the information of the SMPTE Label is included in the system item. Bits b5 and b4 are set to Reference Date /
Time stamp, Current Date / T
This is a flag indicating whether or not "im stamp" exists in the system item. This Reference Date
/ Time stamp indicates, for example, the time or date when the content package was first created. In the Current Date / Time stamp, the time or date when the data of the content package was last corrected is indicated.

Bit b3 is a picture item, bit b
2 is an audio item, and bit b1 is a flag indicating whether or not the AUX item is after the system item. When "1" is set, it indicates that the item exists after the system item.

The bit b0 is the control element (C
ontrol Element).
When "1" is set, it indicates that the control element exists. In addition, although not shown, the bit b
8, b9 are added as described above and transmitted as 10-bit data.

One-word “Content Packa”
bits b7 to b6 of "ge Rate" are undefined areas (Res
erved), and the bits b5 to b1 indicate the package rate which is the number of packages per second in the 1 × speed operation.
(Package Rate) is displayed. Bit b0 is a 1.001 flag. When the flag is set to "1", it indicates that the package rate is (1 / 1.001) times.

One word "Content Packa"
Bits b7 to b5 of “ge Type” are “Stream States” flags for identifying the position of the picture unit in the stream. This 3
The following eight types of states are indicated by the bit flags.

0: The picture unit is a pre-roll (pr
e-roll) section, editing section, post-roll
It does not belong to any of the sections. 1: This picture unit is a picture included in the pre-roll section, and is followed by an editing section. 2: This picture unit is the first picture unit of the editing section. 3: This picture unit is a picture unit included in the middle of the editing section. 4: This picture unit is the last picture unit of the editing section. 5: This picture unit is a picture unit included in the post-roll section. 6: This picture unit is the first and last picture unit of the editing section (the state where the editing section has only one picture unit). 7: Not defined

The bit b4 is an undefined area (Reserved), and the bits b3 and b2 of "Transfer Mod"
"e" indicates the transmission mode of the transmission packet. Also, the transmission timing mode when transmitting the transmission packet is indicated by “Timing Mode” of bits b1 and b0. Here, when the value indicated by the bits b3 and b2 is “0”, the synchronous mode (Synchronous mode)
When "1", isochronous mode,
When it is "2", it is set to an asynchronous mode (Asynchronous mode). When the value indicated by the bits b1 and b0 is “0”, the transmission of the content package for one frame is started at a timing of a predetermined line of the first field (Normal timing mode).
Advanced timing mode in which transmission is started at the timing of a predetermined line in the second field when "1"
(Advanced timing mode), when "2", a dual timing mode in which transmission is started at a timing of a predetermined line in each of the first and second fields (Dual timing mode)
mode).

"Content Package Ty"
"Channel" followed by two words "Channel Handl"
"e" is used to determine the content package of each program when the content packages of a plurality of programs are multiplexed and transmitted, and are identified by identifying the values of bits H15 to H0. Content packages can be separated for each program.

The two-word "Continuity Co"
"unt" is a 16-bit modulo counter. This counter is counted up for each picture unit, and is independently counted for each stream. Therefore, when a stream is switched by a stream switcher or the like, the value of this counter becomes discontinuous, and a switching point (editing point) can be detected. Since this counter is a 16-bit modulo counter as described above and has a very large value of 65536, the probability that the value of the counter coincidentally coincides at the switching point between the two switched streams is extremely low. In addition, practically sufficient accuracy can be provided for detecting the switching point.

After “Continuity Count”, the above-mentioned SMPTE Label or Refer
ence Date / Time and Current
"SMPTE Universal" indicating Date / Time
sal Label "," Reference Dat "
e / Time stamp "," Current Da
A "te / Time stamp" area is provided.

After that, "Package Meta"
data Set ”or“ Picture Metada ”
ta Set "," Audio Metadata Se "
t "" Auxiliary Metadata Se
A "t" region is provided. In addition, "Picture Me
tadata Set "," Audio Metadat "
a Set "," Auxiliary Metadata "
Set ”indicates that the corresponding item is“ System I
It is provided when it is indicated that the content is included in the content package by the flag of “tem Bitmap”.

The above-mentioned “Time stamp” is allocated 17 bytes, and the first 1 byte is “Time stamp”.
e stamp ", and the remaining 16 bytes are used as a data area. here,
The first 8 bytes of the data area are, for example, SMPTE12
A time code (Time code) standardized as M is shown, and the subsequent 8 bytes are invalid data.

As shown in FIG. 6, the 8-byte time code includes "Frame", "Seconds", and "Minute".
s "," Hours "and 4-byte" Binary "
Group Data ”.

Bits b5 and b4 of "Frame" indicate the tens place of the frame number, and bits b3 to b0 indicate the place of the first place. Similarly, “Secons” and “Minute”
s ”,“ Hours ”, each bit b6 to b0 indicates seconds,
Minutes and hours are shown.

Bit b7 of "Frame" is a color frame flag (Color Frame Flag), and indicates whether the frame is the first color frame or the second color frame. Bit b6 is a drop frame flag (Drop Frame flag).
Flag), which is a flag indicating whether or not the video frame inserted in the picture item is a drop frame. Bit b7 of “Seconds” is, for example, NTSC
In the case of the system, a field phase (Field Phase), that is, whether the field is the first field or the second field is indicated. In the case of the PAL method, the field phase is indicated by the bit b6 of “Hours”.

3 bits B0 of bit b7 of "Minutes" and bits b7 and b6 of "Hours"
B3 (In the PAL system, “Seconds” and “Mini
tes ”and“ Hours ”, each bit b7) indicates whether or not there is data in each of BG1 to BG8 of“ Binary Group Data ”. In this “Binary Group Data”, for example, the Gregorian calendar (GregorianCalender) and the Julian calendar (Julian calendar)
Calender) can be displayed in two digits.

FIG. 7 shows the structure of "Metadata Set", in which one word "Metadata Co."
"metadata Bl" in the set
The number of “ocks” is indicated. In addition, "Metadata
When the value of “Set” is 00h, “Metadata
Since there is no "Block", "Me
“tadata Set” is one word.

Here, "Metadata Bloc
“k” indicates “Package Metadata Set” indicating content package information such as a program title.
In the case of, the one-word "Metadata Type
"e", a two-word "Word Count", and an information area "Metadata" is provided.
If the number of words of this “Metadata” is “Word C
"out" is indicated by bits b15 to b0.

"Picture Metadata Set", "A" indicating information related to packaged items such as video, audio or AUX data.
audio Metadata Set "and" Auxili
The “ary MetadataSet” further includes “Element Type” and “Element” of one word.
“Element Number” is provided, and “Element Data” of items such as video and audio described below is provided.
"Element Type" and "E"
element Number ", and is linked to" Element Data Block ".
Metadata can be set for each time. After these “Metadata Set”, “Cont.
A "rollElement" region can be provided.

Next, a block of each item such as video and audio will be described with reference to FIG. Block of each item such as video and audio "Item Type
"e" indicates the type of item as described above,
It is set to "05h" for a picture item, "06h" for an audio item, and "07h" for an AUX data item. “Item Word Count” indicates the number of words up to the end of this block (corresponding to “Word Count” of a variable-length block). "I
“Item H Count” followed by “Item H
"Element Data Bl"
The number of “ocks” is indicated. Here, "Item Hea
Since “der” is 8 bits, “Element”
The number of “DataBlock” ranges from 1 to 255 (0 is invalid). The “Element Data Block” following the “Item Header” is the data area of the item.

[Element Data Bloc]
k "means" Element Type "and" Element
t Word Count "," Element Num "
ber "and" Element Data ", and" Element Type "and" Element ".
Word Count "by" Element
The type and amount of data of “Data” are shown.
The “Element Number” indicates the number of the “Element Data Block”.

Next, the structure of “Element Data” will be described. MPEG, one of the elements
The -2 picture element is an MPEG-2 video elementary stream (V-ES) of any profile or level. Profiles and levels are defined in the decoder template document. FIG. 9 is a format example of the MPEG-2 V-ES in the SDTI-CP element frame. This example is a V-ES bitstream that specifies a key, ie, an MPEG-2 start code (according to SMPTE recommended practices). MPEG
The -2 V-ES bitstream is simply formatted into data blocks as shown in FIG.

Next, metadata for a picture item, for example, MPEG-2 picture image editing metadata will be described. This metadata is a combination of edit and error metadata, compression encoded metadata, and source encoded metadata. These metadata can be inserted mainly in the system items described above, as well as in auxiliary data items.

FIG. 10 shows “Picture Editing Bitm” provided in the MPEG-2 picture editing metadata inserted in the “Picture Metadata Set” area of the system item shown in FIG.
An “ap” area, a “Picture Coding” area, and an “MPEG User Bitmap” area are shown. Further, the MPEG-2 picture editing metadata includes a “Profile / Level” area indicating the profile and level of MPEG-2, and an SMPTE1
It is also conceivable to provide video index information defined in 86-1995.

One word "Picture Edit"
ng Bitmap ”bits b7 and b6 are“ Ed
It flag ", which is a flag indicating editing point information. The following four types of states are indicated by the 2-bit flag.

00: No editing 01: The editing point is before the picture unit with this flag (Pre-picture edit) 10: The editing point is after the picture unit with this flag (Post-picture edit) -picture edit) 11: Only one picture unit is inserted, and the edit point is before and after the picture unit with this flag (single
le frame picture)

That is, a flag indicating whether the video data (in picture units) inserted in the picture item is before the edit point, after the edit point, or sandwiched between two edit points is set to “Picture”. Metadata
Set ”(see FIG. 4),“ Picture Edit ”
ing Bitmap "region.

Bits b5 and b4 are set to "Error"
flag ". This "Error flag"
Whether the picture contains an uncorrectable error, the picture contains a concealment error, the picture contains no errors,
Furthermore, it indicates whether it is in an unknown state. Bit b3 is "P
Picture Coding ”is the“ Picture
This is a flag indicating whether or not it is in the “MetadataSet” area. Here, when “1” is set, “P”
icture coding ”is included.

The bit b2 is “Profile / Lev”
"el". here,
When it is set to “1”, the “Metadata
The “Block” includes “Profile / Level”. This “Profile / Level” is M
MP @ ML or HP indicating PEG profile or level
＠ Indicates HL or the like.

The bit b1 is a flag indicating whether or not "HV Size" exists. Here, when “1” is set, “HV Size” is included in the “Metadata Block”. Bit b0 is
This flag indicates whether or not “MPEG User Bitmap” is present. Here, when “1” is set, “MPE” is added to the “Metadata Block”.
G User Bitmap "is included.

One word "Picture Codin"
“Closed GOP” is provided in bit b7 of “g”. This “Closed GOP” indicates that the GOP (Group Of Picture) when MPEG-compressed is Closed.
d Indicates whether this is a GOP.

Bit b6 contains “Broken Lin”.
k ”is provided. This "Broken Link"
Is a flag used for reproduction control on the decoder side.
That is, each picture of MPEG is arranged like a B picture, a B picture, an I picture, etc., but when there is an editing point and a completely different stream is connected, for example, the B picture of the stream after switching is There is a possibility that decoding is performed with reference to the P picture of the stream before switching. By setting this flag, it is possible to prevent the decoding as described above on the decoder side.

Bits b5 to b3 contain "Picture"
“Coding Type” is provided. This "Pi
"cure Coding Type" is a flag indicating whether the picture is an I picture, a B picture, or a P picture. Bits b2 to b0 are undefined areas (Reserved).

One word "MPEG User Bit"
"History dat" is set in bit b7 of "map".
a "is provided. This "History dat"
“a” indicates that the encoded data such as the quantization step, the macro type, and the motion vector, which are necessary for the encoding of the previous generation, are stored in the user data area existing in “Metadata” of “Metadata Block”, for example. , History data, or not. Bit b6 contains “Anc
data ”is provided. This "Anc dat
"a" is the data inserted in the ancillary area (for example,
This is a flag indicating whether or not data necessary for MPEG compression is inserted as Anc data in the user data area.

The bit b5 contains “Video inde
x "is provided. This "Video inde
“x” is a video index in the video index area.
This is a flag indicating whether index information is inserted. The video index information is inserted into a 15-byte video index area. In this case, the insertion position is determined for each of the five classes (1.1, 1.2, 1.3, 1.4, and 1.5). For example, the video index information of the 1.1 class is inserted into the first three bytes.

Bit b4 contains “Picture or
der "is provided. This "Picture o
“rder” is a flag indicating whether or not the order of each picture of the MPEG stream has been changed. In addition, MPE
Changing the order of the pictures in the G stream is required for multiplexing.

Bits b3 and b2 contain "Timecod
e2 "and" Timecode1 ". This "Timecode2", "Timecode1"
Is in the area of Timecode2, 1
ical Interval Time Code), LTC (Longitudinal Ti)
me Code) is inserted. Bits b1 and b0 include “H-Phase” and “V
-Phase "is provided. This "H-Phas
"e" and "V-Phase" are flags indicating which horizontal pixel and vertical line are being encoded at the time of encoding, that is, whether or not the information of the frame actually used is in the user data area.

Next, the audio item will be described. The audio item "Element Dat
“a” is “Element Dat” as shown in FIG.
"a" is "Element Header", "Audio"
“Sample Count”, “Stream Val”
id Flags "and" Data Area ".

The one-word “Element Head”
The bit b7 of “r” is “FVUCPVValid Fla.
g), and FVUCP defined in the AES-3 format standardized by the AES (Audio Engineering Society) is the AES of “Data Area”.
-3 format audio data (audio data)
Indicates whether or not it has been set. Bits b6 to b3
Is an undefined area (Reserved), and bits b2 to b0
Sequence number of 5-frame sequence (5-sequ
ence counter) is indicated.

Here, the five-frame sequence will be described. One frame is composed of 525 scanning lines (30/1.
001) synchronized with the video signal of frame / second,
When an audio signal having a sampling frequency of 48 kHz is divided into blocks of each frame of a video signal,
The number of samples per video frame is 1601.6 samples / frame, which is not an integer value. For this reason,
A sequence in which two frames of 1601 samples are provided and three frames of 1602 samples are provided so that five frames have 8008 samples is called a five-frame sequence.

The 5-frame sequence is synchronized with the reference frame signal shown in FIG. 12A. For example, as shown in FIG. 12B, the frames of sequence numbers 1, 3, and 5 are 1602 samples, and the frames of sequence numbers 2 and 4 are 1601 samples. The sequence number is represented by bit b2
Ｂb0.

A two-word "Audio Sample"
"Count" includes bits c15 to c15 as shown in FIG.
This is a 16-bit counter in the range of 0 to 65535 using 0, and indicates the number of samples of each channel. Note that all channels have the same value in the element.

One-word “Stream Valid”
"Flags" indicates whether or not each stream of eight channels is valid. Here, when significant audio data is included in the channel, the bit corresponding to this channel is set to “1”, and otherwise, the bit is set to “0” and the bit is set to “1”. Only the audio data of the channel set to "" is transmitted.

"S2-s0" of "Data Area"
Is a data area for identifying each stream of eight channels. “F” indicates the start of a subframe.
“A23 to a0” are audio data, and “P,
"C, U, V" are channel status, user bit, V
The parity bits include parity bits, parity bits, and the like.

Next, the metadata for the audio item will be described. Audio editing metadata (Aud
io Editing Metadata) is a combination of editing metadata, error metadata, and source coding metadata. As shown in FIG. 13, the audio editing metadata includes one word “Field / Frame fl”.
ags ", 1-word" Audio Editing "
Bitmap ", 1-word" CS Valid Bi
tmap "and" Channel Status "
Data ”.

The number of valid audio channels is determined by the “Stream Val” shown in FIG.
id Flags ". If the flag of “Stream Valid Flags” is set to “1”, “Audio E
"Diting Bitmap" becomes effective.

[0082] "Audio Editing Bitm"
“first editing flag” of “ap” is the first field, “Second editing flag”.
“lag” indicates information on the editing status in the second field, and indicates whether the editing point is before or after the field with this flag. "Error
“lag” indicates whether or not an error that cannot be corrected has occurred.

“CS Valid Bitmap” is
"Ch" of n (n = 6, 14, 18, or 22) bytes
"annule Status Data" header, which indicates which of the 24 channel status words is present in the data block. Here, "CS
Valid1 ”is“ Channel Status ”
This is a flag indicating whether or not there is data in 0 to 5 bytes of “Data”. "CS Valid2"-"CS
Valid4 ”is“ Channel Status ”
This is a flag indicating whether or not there is data in 6 to 13 bytes, 14 to 17 bytes, and 18 to 21 bytes of “Data”. In addition, "ChannelStatus
Data ”is set to 24 bytes, and 2
Depending on the data of the 22nd byte, whether or not there is data from 0 to 21 bytes is indicated.
The 3-byte data is used as a CRC from 0 to 22 bytes. In addition, "Fielded / Frame flag
The flag "s" indicates whether the audio data of eight channels is packed in frame units or field units.

A general-purpose data format (General Data
Format) is used to carry all freeform data types. However, this free form data type does not include special auxiliary element types such as IT nature (word processing, hypertext, etc.).

Next, the configuration of a data transmission system for transmitting data in such an SDTI-CP format will be described.

As shown in FIG. 14, AUX such as video data and audio data of a program and information related to the program.
When transmitting data to a data recording / reproducing device 10 such as a server or a video tape recorder, a program from a plurality of data output devices 14-1 to 14-n is switched by using a matrix switcher 12 such as a router. To be stored in the data recording / reproducing device 10.

At the time of transmission of this program, for example, a stream of video data DVC-1 or uncompressed audio data DAU-1 compressed by the MPEG2 method is transmitted from the data output device 14-1 to the data transmission device 20T- After packaging in frame units by the above 1, the SDTI-
This data is converted into serial data CPS-1 as data in a CP format and output. Similarly, data from another data output device 14-n is packaged in frame units by the corresponding data transmission device 20T-n, and is converted into serial data CPS data as data in the SDTI-CP format.
Convert to -n and output. The signals SC-1 to SC-n are reference timing signals, for example, reference frame pulse signals. The video data is transmitted by the data transmission devices 20-1 to 20-n based on the reference timing signals SC-1 to SC-n. DV
Input processing such as C is performed.

The data transmission device 20R on the receiving side separates packaged video data and audio data from the serial data CPS selected by the matrix switcher 12, and separates one frame of compressed video data and uncompressed audio data. The data is supplied to the data recording / reproducing device 10 and accumulated. The signal S
CR is a reference timing signal like the signal SC. Based on the reference timing signal SCR, output processing of the video data DVC or the like from the data transmission device 20R is performed.

Next, the outline of the configuration of the data transmission apparatus is shown in FIG.
5 will be described. The transmission-side data transmission device 20T and the reception-side data transmission device 20R have the same configuration. CPU interface unit 20 of data transmission device 20
1 is connected to a CPU (Central Processing Unit) 240. The CPU interface unit 201 has a plurality of registers. The plurality of registers are sequentially designated by the address signal SAD from the CPU 240, and the data signal SDT is supplied to the designated register to set “System Item Type” or “System Item Type”. System
m Item Bitmap "FEC Active
Flag, SMPTE Label and RefDate
/ Time, Current Date / Time, and a flag indicating the presence or absence of Control;
t Package Rate ”to“ Current
Data up to “Date / Time stamp” are stored. These registers are connected to an SDTI core unit 222 described later.

Further, the CPU interface unit 201 has a memory control unit 211 of the memory management unit 210.
Is provided. This register is a storage location of data to be written to an SDRAM unit 250 described later, and is stored in “Package MetaDa”.
ta Set ”to“ Control Element ”
When the data up to "t" is stored in this predetermined register,
The stored data is sequentially written to the SDRAM unit 250 via the memory control unit 211 and the like.

The compressed video data DVC is supplied to the memory control unit 211 via the interface unit 202. The uncompressed audio data DAU is supplied to the memory control unit 211 via the interface unit 203. When the AUX data DSX is supplied, the memory control unit 21
1 is supplied.

Here, the interface units 202 and 20
In step 3204, the number of words of the input data is counted in frame units, and not only the data but also the respective word count values VC, AC, XC are stored in the memory controller 211.
To supply. Also, the interface units 202, 203, 2
In step 04, a clock transfer process is performed, and data input from the outside at different frequencies is converted to an SDR to be described later.
The data is replaced with the clock frequency data of the AM unit 250.
In this clock transfer process, the data of each item is written to the memory in each interface unit based on the clock signal on the data output device side, and the data written to the memory is read by the clock signal of the SDRAM unit 250. , The clock is changed. For example, 8-bit video data DVC having a transmission rate of 27 MHz, 36 MHz or 54 MHz or 16-bit audio data DAU having a sampling frequency of 48 kHz is written in the memory and read at 81 MHz or 108 MHz which is the frequency of the clock signal of the SDRAM section 250. The clock is changed.

Further, the interface unit 203 performs serial-parallel conversion, converts serial audio data into parallel data having a bit number corresponding to the bus width of the SDRAM unit 250, and supplies the parallel data to the memory control unit 211.
The interface units 202 and 204 also convert the input data into a bit number corresponding to the bus width of the SDRAM unit 250 and supply the converted data to the memory control unit 211. Similarly, the CPU interface unit 201 counts the number of words for one frame of data to be written to the SDRAM unit 250, and outputs the word count value MC to the memory control unit 211.
And performs a clock changeover process and a conversion process to the number of bits according to the bus width.

The memory control unit 211 includes the SDRAM unit 2
50 to store data to be written,
Unit 2 for temporarily storing data read from
12 are connected. Here, when the SDRAM unit 250 can perform data transfer or read with maximum transfer efficiency by performing burst transfer with, for example, 32 bits and 16 words, the memory unit 212 stores a system item, a picture item, and an audio item. 32 bits 16 words for each of the AUX items
It is configured to have the memory capacity of the bank. By configuring the memory unit 212 in this manner, by performing data transmission while performing bank switching, while writing data supplied from the interface unit to one bank, the data of each item of the other bank is written in 32 bits. 1
The data can be supplied to the SDRAM unit 250 by burst transfer in six words.

In the memory control unit 211, the SDRAM unit 2
Memory unit 21 configured for data transfer with
When the number of input ports is one, the arbitration of the writing of the data DSY, the video data DVC, the audio data DAU and the AUX data DSX of the system item supplied via the interface units 201 to 204 is performed, and each data is sequentially transmitted. It is stored in the memory unit 212.
Thereafter, when data for burst transfer is stored in the memory unit 212, a write request signal WQ for writing the data to the SDRAM unit 250 is generated and supplied to the arbiter unit 213. Further, the interface unit 20
The word count values MC, VC, AC, and XC supplied from 1, 202, 203, and 204 are stored in the word count table unit 214 for each frame.

In the arbiter 213, the memory controller 21
Arbitration of a write request based on a write request signal WQ from the CPU 1 or a read request based on a read request signal RQ from the memory control unit 215 described later is performed. Here, the signals AKA and AKB indicating that the request has been accepted are transmitted to the memory control units 211 and 215.
Is supplied from the memory unit 212 to the SDRAM.
The data transfer to the unit 250 and the data transfer from the SDRAM unit 250 to the memory unit 216 are prevented from being performed simultaneously, and the data transfer is performed sequentially. Also, based on the word count value stored in the word count table unit 214, a control signal for writing and reading data to and from the SDRAM unit 250 is generated and supplied to the SDRAM control unit 220, so that each item can be controlled. Data of SDRAM section 250
Can be written correctly, and the written data can be read correctly.

The SDRAM control section 220 writes and reads data to and from the SDRAM section 250 by burst transfer based on a control signal from the arbiter section 213, and performs processing such as refresh operation of the SDRAM section 250.

The arbiter unit 213 has an SDRA
A memory unit 216 for temporarily storing data read from the M unit 250 by burst transfer is connected. This memory unit 216 is, like the memory unit 212, an SDRAM
It is configured to be able to write and read data with the maximum transfer efficiency with the unit 250.

Writing and reading of data in the memory unit 216 are controlled by the memory control unit 215,
Data is written at the clock frequency of the DRAM unit 250, and read is performed so that the written data is converted into serial data and output at the transmission frequency (for example, 270 Mbps) of the serial digital transfer interface. This memory unit 216
Is supplied to the SDTI core unit 222.

[0100] The memory control unit 215 uses an SDT described later.
A read request signal RQ is generated based on the data request signal DQ from the I core unit 222 and supplied to the arbiter unit 213. Data is read based on the read request signal RQ and supplied to the SDTI core unit 222 via the memory unit 216. Further, the amount of data stored in the memory unit 216 is determined, and if the amount of data decreases, the SDRAM unit 250
And a read request signal RQ for reading data from the arbiter unit 213. The SDTI core unit 222
Data based on the data request signal DQ from the memory unit 2
16 is written in the memory unit 216
Is supplied to the SDTI core unit 222.

In the SDTI core unit 222, the memory unit 21
The 8-bit item data read from 6 to 32 bits in 1-word units is converted into 10 bits. Also, CP
A system item is generated using information stored in a register of the U interface unit 201, or a picture item or an audio item is generated by adding header information or the like to video data or audio data. In the generation of each item, a CRC for error detection and an ECC for error detection and correction are added. Furthermore, "S
A fixed value such as "eparator" or "End Code" is generated and added, and codes EAV, SAV and header data are added. SD generated in this way
The data in the TI-CP format is converted into serial data CPS by the signal converter 260 and transmitted as a transmission packet of the serial digital transfer interface.

When this data transmission apparatus is used on the receiving side, the processing is performed in a manner reverse to that on the transmitting side.
That is, the serial data C
Convert PS to 10-bit parallel data and convert to SDTI
It is supplied to the core part 222. In the SDTI core unit 222,
An error detection process based on CRC and an error detection and correction process based on ECC are performed. Furthermore, "Separator"
The data of each item of the content package is separated using data such as “Item Type” and written into the memory unit 216. Further, the word count value included in the content package is extracted and stored in the word count table unit 214. Further, information on system items is supplied to the CPU interface unit 201,
Retrieve information about each item. Here, for example, information on an audio item, for example, “Elemen
t Header ”,“ 5-sequence cou ”
nt "and" Audio Sample Count "are taken out, and the interface unit 2
03.

The memory section 216 is controlled by the memory control section 215 as described above, and the memory control section 2
At 15, the amount of data written to the memory unit 216 is determined. Here, when the data for the burst transfer to the SDRAM unit 250 is stored in the memory unit 216, a write request signal WQ for writing the data stored in the memory unit 216 to the SDRAM unit 250 is transmitted to the memory control unit 215.
From the arbiter unit 213.

In the arbiter 213, the memory controller 2
In response to the write request from the memory control unit 211 and the write request from the memory control unit 211, the data stored in the memory unit 216 is written to the SDRAM unit and stored in the word count table unit 214. The video data and audio data for one frame of each item are transferred to the SDRAM unit 2 based on the information on the number of words and the read request.
The data is read from the memory 50 and supplied to the memory unit 212.

The data written in the memory unit 212 is
The data is sequentially read out by the memory control unit 211 and supplied to the corresponding interface units 201 to 204. In each of the interface units 201 to 204, the clock is switched by a process reverse to that at the time of transmission, and the SDRAM unit 250
Is output as data having a clock frequency corresponding to the data recording / reproducing apparatus 10.

The timing generator 225 generates various timing signals based on a reference timing signal supplied from the outside and the received serial data CPS. The timing signal generated by the timing generator 225 is , Each interface section and arbiter section 2
13 and supplied to the SDTI core unit 222 and the like, and the operation of each unit is performed at a predetermined timing.

Next, the transmission operation of a program will be described with reference to FIG. For the sake of simplicity, it is assumed that the transmitting side and the receiving side operate in synchronization with the reference timing signal SCM shown in FIG. 16A. At time t1, the data V1 for one frame of the compressed video data DVC shown in FIG. 16B is output from the data output device 14 in synchronization with the fall of the frame pulse. The enable signal VE indicating that the video data DVC is valid is
As shown in FIG. 16C, the video data DVC is kept at the low level “L” during the valid period. The data output device 14 outputs uncompressed audio data DAU as shown in FIG. 16D. Here, audio data for one frame period from the time point t1 is defined as data A1.

When the output of one frame of video data is completed at time t2, the signal level of the enable signal VE is set to the high level "H".

At time t3 after one frame period has elapsed from time t1, data V2 for the next one frame is output from data output device 14, and audio data for one frame period from time t3 is data A2. Is done.

The data transmission device 20T on the transmitting side packs the data V1 and A1 supplied during one frame period from the time point t1 to the time point t3 into the SDTI-CP format, and then converts the serial data C1 shown in FIG.
It is converted to PS and transmitted within one frame period from time t3.

The data transmission device 20R on the receiving side separates the packed video data and audio data from the received serial data CPS as shown in FIG. 16F. Note that the signal EN shown in FIG.
During the period in which the data DT is valid, the signal level is set to the low level “L” from time t4 to time t5, for example.

The separated video data, audio data, and the like are sequentially stored in SDRAM section 250. 16H and 16K at the time t6 when the next frame pulse falls.
Are read from the SDRAM unit 250 so as to be output as video data DVC and audio data DAU as shown in FIG. The read data is output from the interface unit at a speed corresponding to the data recording / reproducing device 10 and is sent to the data recording / reproducing device 10.
Can be stored. FIG. 16J shows an enable signal VE indicating a period during which the video data DVC shown in FIG. 16H is valid.

By the way, the received serial data CPS
When performing error detection or error correction processing on the header data, “CRC Flag” of header data or “System
When the flag related to the ECC of the bit b7 of the “Item Bitmap” becomes abnormal, error detection and error correction cannot be performed correctly, and data of each item in the payload area may not be read out.

For this reason, as shown in Table 1, even parity for header data “CRC flag” and “CRC flag” and the CRC value of header data, “Sy
E of bit b7 of “Stem Item Bitmap”
Based on the CC on / off flag and the ECC decoding result,
On / off of ECC and CRC is determined.

[0115]

[Table 1]

FIG. 17 is a flowchart showing ON / OFF determination of ECC and CRC in Table 1. In step ST1, ECC decoding is performed assuming that the received data includes parity, and it is determined whether the received data is within a data correctable range. If it is determined in step ST1 that the data is within the correctable range, the process proceeds to step S1.
The process proceeds to T2, and if the data is not within the correctable range, the process proceeds to step ST5.

In step ST2, it is determined whether or not the ECC on / off flag of the "System Item Bitmap" of the received data is in the on state. Here, when it is determined that the ECC on / off flag is on, the process proceeds to step ST3, where it is determined that the ECC is on and the CRC is off, and the process ends. If the ECC on / off flag is not in the on state, the process proceeds to step ST4, where it is determined that the on / off of the ECC and the CRC cannot be determined, and the process ends.

When the process proceeds from step ST1 to step ST5, it is determined in step ST5 whether an error has been detected using even parity for "CRCflag" or CRC of header data. Here, when it is determined that no error is detected, the process proceeds to step ST6, and when an error is detected, the process proceeds to step ST9.

At step ST6, it is determined whether or not "CRC flag" of the header data of the received data is in the ON state. In this step ST6, "CRC
If it is determined that "flag" is on, the process proceeds to step ST7, where it is determined that ECC is off and CRC is on, and the process ends. Step S
At T6, if "CRC flag" is not on, the process proceeds to step ST8, where it is determined that ECC is on and CRC is off, and the process ends.

When the process proceeds from step ST5 to step ST9, in step ST9, it is determined that ECC and CRC cannot be turned on / off, and the process ends.

In this way, even if the ECC on / off flag or the "CRC flag" is in an erroneous state, for example,
The on / off state of the ECC and the CRC can be correctly determined for each frame by using other information.

FIG. 18 shows a circuit configuration for performing error detection and error correction processing in the SDTI core unit 222. The received data is supplied to the ECC-CRC on / off determining unit 301 and the buffer unit 302.

The ECC-CRC on / off determining section 301 performs the processing shown in FIG. 17 to determine whether the ECC or CRC is on or off, and based on the determination result, the signal switching section 30.
3,305 switching operation is controlled. The buffer unit 3
02, the received data is transmitted to the signal switching unit 30 at a timing after the ECC-CRC on / off determination unit 301 completes the determination.
3 to the movable terminal a. Terminal b of signal switching unit 303
Is connected to the data input terminal of the ECC decoder 304, and the terminal c is connected to the terminal c of the signal switching unit 305.

A data output terminal of the ECC decoder 304 is connected to a terminal b of the signal switching unit 305, and a movable terminal a of the signal switching unit 305 is connected to the buffer unit 306.

Here, the ECC-CRC on / off determining section 3
01, the data received by ECC is ON and CR
When it is determined that C is in the off state, the movable terminal a of the signal switching units 303 and 305 is switched to the terminal b. Also, the received data used to determine whether the ECC or CRC is on or off is output from the buffer unit 302 to the signal switching unit 30 based on the determination result of the ECC-CRC on / off determination unit 301.
The signal is output after terminal switching at 3, 305 and supplied to the ECC decoder 304 in the case described above.

The ECC decoder 304 performs an error correction process using the parity. The error-corrected data output from the ECC decoder 304 is output to the signal switching unit 3.
05 to the buffer unit 306.

The ECC-CRC on / off determining section 30
The data received by 1 is the CRC with ECC off.
Is determined to be in the ON state, the signal switching unit 3
The movable terminals a of 03 and 305 are switched to the terminal c. Also, the received data used to determine whether the ECC or CRC is on or off is output from the buffer unit 302 to the signal switching unit 30 based on the determination result of the ECC-CRC on / off determination unit 301.
The signal is output after the terminal is switched at 3, 305, and is supplied to the terminal c side of the signal switching unit 305 without passing through the ECC decoder 304 in the case described above. Further, since the movable terminal a of the signal switching unit 305 is switched to the terminal c side, the data supplied to the terminal c side is stored in the buffer unit 30.
6. Note that the data output from the buffer unit 302 is subjected to error detection processing using CRC, and is supplied to the buffer unit 306.

Here, when it is determined that the ECC is on and the CRC is off, the parity portion is processed as a portion having no signal. When ECC is off, CR
When it is determined that C is in the ON state, the portion excluding the CRC is processed as a signal portion. For this reason, the buffer unit 306 outputs the data portion as a continuous data signal with the parity and CRC portions left-justified. This buffer unit 306
Is divided into data of each item and stored in the SDRAM unit 250 or the like as described above.

The ECC-CRC on / off determining section 30
When it is determined that the ON / OFF of the ECC and the CRC cannot be determined in step S1 of FIG.
And the subsequent processing is processed by the CPU 240.

As described above, according to the above-described embodiment,
When the data indicating the use status of the ECC or the CRC together with the parity of the ECC or the CRC is received, the information indicating the use status of the ECC or the CRC is incorrect information during the data transmission. However, based on the ECC decoding result and the CRC error detection result, it is possible to determine whether ECC or CRC is added as correctly as possible and to perform error detection and error detection and correction processing of the received data. is there.

In the above-described embodiment, data is packaged in frame units.
As a matter of course, data may be packaged in units of pictures, such as an I picture, a B picture, or a P picture.

[0132]

According to the present invention, information indicating the status of use of the error detection data and the error detection and correction data, the error detection result assuming that the error detection data is added, and the error detection and correction data Based on the result of the error correction processing performed assuming that the data has been added, it is determined which of the error detection data and the error detection and correction data has been added. For this reason, even if the information indicating the usage status of the error detection data and the error detection and correction data is incorrect information, it is preferable to use either the error detection data or the error detection and correction data as much as possible. It is possible to correctly determine whether the received data is added, and to correctly perform error detection and error detection and correction processing of the received data.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an SDTI-CP format.

FIG. 2 is a diagram showing a format of a code EAV and header data.

FIG. 3 is a diagram showing a format of a variable-length block.

FIG. 4 is a diagram showing a configuration of a system item.

FIG. 5 is a diagram showing a format when an ECC is turned on.

FIG. 6 is a diagram showing a configuration of a time code.

FIG. 7 is a diagram showing a configuration of a metadata set.

FIG. 8 is a diagram showing a configuration of another item excluding a system item.

FIG. 9 shows M in an SDTI-CP element frame.
It is a figure showing the format of PEG-2 V-ES.

FIG. 10 is a diagram showing a configuration of MPEG-2 picture editing metadata.

FIG. 11 is a diagram showing a configuration of an element data block of an audio item.

FIG. 12 is a diagram illustrating a 5-frame sequence.

FIG. 13 is a diagram showing a configuration of audio editing metadata.

FIG. 14 is a diagram showing a configuration of a data transmission system.

FIG. 15 is a diagram illustrating an outline of a configuration of a data transmission device.

FIG. 16 is a diagram illustrating a data transmission operation.

FIG. 17 is a flowchart showing ON / OFF determination of ECC and CRC.

FIG. 18 is a diagram showing a part of the configuration of an SDTI core unit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Data recording / reproducing apparatus, 12 ... Matrix switcher, 14 ... Data output apparatus, 20 ... Data transmission apparatus, 201, 202, 203, 204 ...
Interface unit, 210: memory management unit, 211, 215: memory control unit, 212, 21
6: memory unit, 213: arbiter unit, 214
... Word count table section, 220 ... SDR
AM control section, 222 ... SDTI core section, 2
25 timing generator, 250 SDRAM
Section, 260 ... signal conversion section, 301 ... ECC-C
RC on / off determining section, 302, 306... Buffer section, 303, 305... Signal switching section, 304.
CC decoder

Claims (5)

[Claims] 1. A section of one line of a video frame is divided into an end synchronization code area in which an end synchronization code is inserted, an auxiliary data area in which auxiliary data is inserted, and a start synchronization code area in which a start synchronization code is inserted. And a payload area into which data including video and / or audio item data is inserted. Either error detection data or error detection and correction data, the error detection data and the error detection In a data receiving method for receiving a transmission packet of a serial digital transfer interface to which information indicating the use status of correction data is added, information indicating the use status of the received error detection data and the use status of the error detection and correction data, An error detection result performed assuming that the error detection data is added, and the error detection correction Based on the error correction processing result performed as use data is added, the data receiving method characterized in that to determine whether any of the error detection data or the error detection and correction data is added. 2. An error correction processing result performed on the assumption that the error detection and correction data is added is a correctable range, and the error detection and correction data is determined by information indicating a use state of the error detection and correction data. 2. The data transmission method according to claim 1, wherein when it is determined that the data is used, it is determined that the error detection and correction data is added. 3. The method according to claim 1, wherein the result of the error correction process performed on the assumption that the data for error detection and correction is added is uncorrectable, and the result of the error detection performed on the assumption that the data for error detection and correction is added is correct. When it is determined that the error detection data is used by the information indicating the use status of the error detection data, it is determined that the error detection data is added, 2. The data transmission method according to claim 1, wherein it is determined that the error detection and correction data is added when it is determined from the information indicating the use state that the error detection data is not used. 4. A section of each one line of a video frame is divided into an end synchronization code area in which an end synchronization code is inserted, an auxiliary data area in which auxiliary data is inserted, and a start synchronization code area in which a start synchronization code is inserted. And a payload area into which data including video and / or audio item data is inserted. Either error detection data or error detection and correction data, the error detection data and the error detection In a data receiving apparatus for receiving a transmission packet of a serial digital transfer interface to which information indicating the use state of correction data is added, information indicating the use state of the error detection data and the error detection and correction data, Of the error detection performed assuming that the Determining means for determining whether the error detection data or the error detection and correction data has been added, based on the result of the error correction processing performed assuming that the data has been added, and decoding means for performing the error correction processing And a signal switching unit for supplying data received when the determination unit determines that the error detection and correction data is added to the decoding unit. 5. A method for temporarily storing data subjected to error correction processing by said decoding means or data supplied from said signal switching means upon determination that said error detection data is added by said determination means. 5. The data according to claim 4, wherein the storage unit continuously outputs the data excluding the error detection data and the error detection and correction data for each video frame. 6. Receiver.